From 47fda276ca6f1e824646245a2c75ac6d60710fc9 Mon Sep 17 00:00:00 2001
From: Uros Majstorovic <majstor@majstor.org>
Date: Mon, 25 Nov 2019 17:01:09 +0100
Subject: added auto/manual cs control for xchg8/16/32

---
 code/fe310/eos/spi.c | 58 ++++++++++++++++++++++++++--------------------------
 code/fe310/eos/spi.h |  3 +++
 2 files changed, 32 insertions(+), 29 deletions(-)

diff --git a/code/fe310/eos/spi.c b/code/fe310/eos/spi.c
index 0191e3f..3c45ad9 100644
--- a/code/fe310/eos/spi.c
+++ b/code/fe310/eos/spi.c
@@ -41,26 +41,6 @@ static void spi_handler_evt(unsigned char type, unsigned char *buffer, uint16_t
     }
 }
 
-void spi_cs_set(void) {
-	/* cs low */
-    if (SPI1_REG(SPI_REG_CSMODE) == SPI_CSMODE_OFF) {
-        GPIO_REG(GPIO_OUTPUT_VAL) &= ~(1 << spi_dev_cs);
-    } else {
-        SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD;
-    }
-    spi_state_flags &= ~SPI_FLAG_CS;
-}
-
-void spi_cs_clear(void) {
-	/* cs high */
-    if (SPI1_REG(SPI_REG_CSMODE) == SPI_CSMODE_OFF) {
-        GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << spi_dev_cs);
-    } else {
-        SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
-    }
-    spi_state_flags |= SPI_FLAG_CS;
-}
-
 static void spi_flush(void) {
     SPI1_REG(SPI_REG_RXCTRL) = SPI_TXWM(1);
     while (!(SPI1_REG(SPI_REG_IP) & SPI_IP_TXWM));
@@ -69,7 +49,7 @@ static void spi_flush(void) {
 
 static void spi_xchg_done(void) {
     spi_state_flags &= ~SPI_FLAG_XCHG;
-    if (!(spi_state_flags & (EOS_SPI_FLAG_MORE | SPI_FLAG_CS))) spi_cs_clear();
+    if (!(spi_state_flags & (EOS_SPI_FLAG_MORE | SPI_FLAG_CS))) eos_spi_cs_clear();
     SPI1_REG(SPI_REG_IE) = 0x0;
 }
 
@@ -135,7 +115,7 @@ void eos_spi_dev_acquire(unsigned char dev) {
 void eos_spi_dev_release(void) {
     if (spi_wait) spi_xchg_wait();
     if (spi_state_flags & EOS_SPI_FLAG_TX) spi_flush();
-    if (!(spi_state_flags & SPI_FLAG_CS)) spi_cs_clear();
+    if (!(spi_state_flags & SPI_FLAG_CS)) eos_spi_cs_clear();
 
     spi_dev = EOS_SPI_DEV_NET;
     eos_net_start();
@@ -153,7 +133,7 @@ void eos_spi_xchg(unsigned char *buffer, uint16_t len, uint8_t flags) {
     _eos_spi_state_idx_tx = 0;
     _eos_spi_state_idx_rx = 0;
 
-    if (spi_state_flags & SPI_FLAG_CS) spi_cs_set();
+    if (spi_state_flags & SPI_FLAG_CS) eos_spi_cs_set();
     SPI1_REG(SPI_REG_TXCTRL) = SPI_TXWM(SPI_SIZE_WM);
     SPI1_REG(SPI_REG_IE) = SPI_IP_TXWM;
 }
@@ -192,6 +172,26 @@ void eos_spi_xchg_handler(void) {
     }
 }
 
+void eos_spi_cs_set(void) {
+	/* cs low */
+    if (SPI1_REG(SPI_REG_CSMODE) == SPI_CSMODE_OFF) {
+        GPIO_REG(GPIO_OUTPUT_VAL) &= ~(1 << spi_dev_cs);
+    } else {
+        SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD;
+    }
+    spi_state_flags &= ~SPI_FLAG_CS;
+}
+
+void eos_spi_cs_clear(void) {
+	/* cs high */
+    if (SPI1_REG(SPI_REG_CSMODE) == SPI_CSMODE_OFF) {
+        GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << spi_dev_cs);
+    } else {
+        SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
+    }
+    spi_state_flags |= SPI_FLAG_CS;
+}
+
 uint8_t eos_spi_xchg8(uint8_t data, uint8_t flags) {
     volatile uint32_t x = 0;
     uint8_t rx = !(flags & EOS_SPI_FLAG_TX);
@@ -201,7 +201,7 @@ uint8_t eos_spi_xchg8(uint8_t data, uint8_t flags) {
 
     spi_state_flags &= 0xF0;
     spi_state_flags |= flags;
-    if (spi_state_flags & SPI_FLAG_CS) spi_cs_set();
+    if ((spi_state_flags & EOS_SPI_FLAG_AUTOCS) && (spi_state_flags & SPI_FLAG_CS)) eos_spi_cs_set();
 
     while (SPI1_REG(SPI_REG_TXFIFO) & SPI_TXFIFO_FULL);
     SPI1_REG(SPI_REG_TXFIFO) = data;
@@ -210,7 +210,7 @@ uint8_t eos_spi_xchg8(uint8_t data, uint8_t flags) {
         while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY);
     }
 
-    if (!(spi_state_flags & (EOS_SPI_FLAG_MORE | SPI_FLAG_CS))) spi_cs_clear();
+    if ((spi_state_flags & EOS_SPI_FLAG_AUTOCS) && !(spi_state_flags & EOS_SPI_FLAG_MORE)) eos_spi_cs_clear();
 
     return x & 0xFF;
 }
@@ -225,7 +225,7 @@ uint16_t eos_spi_xchg16(uint16_t data, uint8_t flags) {
 
     spi_state_flags &= 0xF0;
     spi_state_flags |= flags;
-    if (spi_state_flags & SPI_FLAG_CS) spi_cs_set();
+    if ((spi_state_flags & EOS_SPI_FLAG_AUTOCS) && (spi_state_flags & SPI_FLAG_CS)) eos_spi_cs_set();
 
     while (SPI1_REG(SPI_REG_TXFIFO) & SPI_TXFIFO_FULL);
     SPI1_REG(SPI_REG_TXFIFO) = (data & 0xFF00) >> 8;
@@ -239,7 +239,7 @@ uint16_t eos_spi_xchg16(uint16_t data, uint8_t flags) {
         r |= x & 0xFF;
     }
 
-    if (!(spi_state_flags & (EOS_SPI_FLAG_MORE | SPI_FLAG_CS))) spi_cs_clear();
+    if ((spi_state_flags & EOS_SPI_FLAG_AUTOCS) && !(spi_state_flags & EOS_SPI_FLAG_MORE)) eos_spi_cs_clear();
 
     return x & 0xFF;
 }
@@ -254,7 +254,7 @@ uint32_t eos_spi_xchg32(uint32_t data, uint8_t flags) {
 
     spi_state_flags &= 0xF0;
     spi_state_flags |= flags;
-    if (spi_state_flags & SPI_FLAG_CS) spi_cs_set();
+    if ((spi_state_flags & EOS_SPI_FLAG_AUTOCS) && (spi_state_flags & SPI_FLAG_CS)) eos_spi_cs_set();
 
     while (SPI1_REG(SPI_REG_TXFIFO) & SPI_TXFIFO_FULL);
     SPI1_REG(SPI_REG_TXFIFO) = (data & 0xFF000000) >> 24;
@@ -276,7 +276,7 @@ uint32_t eos_spi_xchg32(uint32_t data, uint8_t flags) {
         r |=  x & 0xFF;
     }
 
-    if (!(spi_state_flags & (EOS_SPI_FLAG_MORE | SPI_FLAG_CS))) spi_cs_clear();
+    if ((spi_state_flags & EOS_SPI_FLAG_AUTOCS) && !(spi_state_flags & EOS_SPI_FLAG_MORE)) eos_spi_cs_clear();
 
     return r;
 }
diff --git a/code/fe310/eos/spi.h b/code/fe310/eos/spi.h
index 79da7ac..2327413 100644
--- a/code/fe310/eos/spi.h
+++ b/code/fe310/eos/spi.h
@@ -9,6 +9,7 @@
 
 #define EOS_SPI_FLAG_TX     0x01
 #define EOS_SPI_FLAG_MORE   0x02
+#define EOS_SPI_FLAG_AUTOCS 0x04
 
 void eos_spi_init(void);
 void eos_spi_dev_acquire(unsigned char dev);
@@ -17,6 +18,8 @@ void eos_spi_dev_release(void);
 void eos_spi_xchg(unsigned char *buffer, uint16_t len, uint8_t flags);
 void eos_spi_xchg_handler(void);
 
+void eos_spi_cs_set(void);
+void eos_spi_cs_clear(void);
 uint8_t eos_spi_xchg8(uint8_t data, uint8_t flags);
 uint16_t eos_spi_xchg16(uint16_t data, uint8_t flags);
 uint32_t eos_spi_xchg32(uint32_t data, uint8_t flags);
-- 
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