From a67f35abdb7ef55c062c26251b7354d9968d385b Mon Sep 17 00:00:00 2001
From: Uros Majstorovic <majstor@majstor.org>
Date: Sun, 29 Jul 2018 10:03:46 +0200
Subject: pin numbers fixed

---
 code/fe310/eos/i2s_def.h    |  2 +-
 code/fe310/eos/net.c        |  6 +++---
 code/fe310/eos/spi_def.h    |  1 +
 code/fe310/eos/trap_entry.S | 12 ++++++++----
 4 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/code/fe310/eos/i2s_def.h b/code/fe310/eos/i2s_def.h
index 2b9d852..e924776 100644
--- a/code/fe310/eos/i2s_def.h
+++ b/code/fe310/eos/i2s_def.h
@@ -5,7 +5,7 @@
 #define I2S_PIN_CK              1   // pin 9
 #define I2S_PIN_CKE             12  // pin 18
 #define I2S_PIN_CKF             18  // pin 2
-#define I2S_PIN_SD              20  // pin 4
+#define I2S_PIN_SD              13  // pin 19
 #define I2S_PIN_WS              11  // pin 17
 
 #define I2S_PIN_LR              13  // pin 19
diff --git a/code/fe310/eos/net.c b/code/fe310/eos/net.c
index e024896..bcfa1f2 100644
--- a/code/fe310/eos/net.c
+++ b/code/fe310/eos/net.c
@@ -189,7 +189,7 @@ static void spi_handler_cts(void) {
     if (_eos_spi_state_flags & SPI_FLAG_RDY) {
         spi_xchg_next(NULL);
     } else {
-        uint32_t iof_mask = ((uint32_t)1 << IOF_SPI1_SS2);
+        uint32_t iof_mask = ((uint32_t)1 << SPI_PIN_CS);
         GPIO_REG(GPIO_IOF_EN) &= ~iof_mask;
     }
 }
@@ -260,7 +260,7 @@ void eos_net_init(void) {
 }
 
 void eos_net_start(uint32_t sckdiv) {
-    uint32_t iof_mask = ((uint32_t)1 << IOF_SPI1_SS2);
+    uint32_t iof_mask = ((uint32_t)1 << SPI_PIN_CS);
 
     GPIO_REG(GPIO_IOF_SEL) &= ~iof_mask;
     GPIO_REG(GPIO_IOF_EN) |= iof_mask;
@@ -290,7 +290,7 @@ void eos_net_stop(void) {
     clear_csr(mstatus, MSTATUS_MIE);
     _eos_spi_state_flags &= ~SPI_FLAG_RDY;
     if (_eos_spi_state_flags & SPI_FLAG_CTS) {
-        uint32_t iof_mask = ((uint32_t)1 << IOF_SPI1_SS2);
+        uint32_t iof_mask = ((uint32_t)1 << SPI_PIN_CS);
         GPIO_REG(GPIO_IOF_EN) &= ~iof_mask;
         done = 1;
     }
diff --git a/code/fe310/eos/spi_def.h b/code/fe310/eos/spi_def.h
index 69ca168..1f63d38 100644
--- a/code/fe310/eos/spi_def.h
+++ b/code/fe310/eos/spi_def.h
@@ -12,6 +12,7 @@
 
 #define SPI_PIN_RTS             0   // pin 8
 #define SPI_PIN_CTS             23  // pin 7
+#define SPI_PIN_CS             	IOF_SPI1_SS0	// pin 10
 
 #define SPI_FLAG_RDY            0x01
 #define SPI_FLAG_RST            0x02
diff --git a/code/fe310/eos/trap_entry.S b/code/fe310/eos/trap_entry.S
index cda534e..82a553a 100644
--- a/code/fe310/eos/trap_entry.S
+++ b/code/fe310/eos/trap_entry.S
@@ -32,13 +32,17 @@
 #define I2S_PWM_CTRL_ADDR_CK  PWM0_CTRL_ADDR
 #define I2S_PWM_CTRL_ADDR_WS  PWM2_CTRL_ADDR
 
-#include "net_def.h"
-#include "spi_def.h"
+#define IOF_SPI1_SS0      2
+#define IOF_SPI1_SS1      8
+#define IOF_SPI1_SS2      9
+#define IOF_SPI1_SS3      10
 
 #define INT_SPI1_BASE     6
 #define INT_GPIO_BASE     8
 
-#define IOF_SPI1_SS2      9
+#include "net_def.h"
+#include "spi_def.h"
+
 
   .section      .data.entry
   .align 2
@@ -642,7 +646,7 @@ spi_handler_cts:
 2:
   lw x8, GPIO_IOF_EN(x19)
   li x9, 1
-  slli x9, x9, IOF_SPI1_SS2
+  slli x9, x9, SPI_PIN_CS
   not x9, x9
   and x8, x8, x9
   sw x8, GPIO_IOF_EN(x19)
-- 
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