From c3c3e5f66fb24c584fefde1c0805e952d539ba9f Mon Sep 17 00:00:00 2001
From: Uros Majstorovic <majstor@majstor.org>
Date: Tue, 5 May 2026 00:05:12 +0200
Subject: JLCPCB order W2025070409252353

---
 hw/expansion/expansion.kicad_pcb | 352 +++++++++++++++++++++++++++++++++++++++
 hw/expansion/expansion.pro       | 248 +++++++++++++++++++++++++++
 hw/expansion/expansion.sch       | 238 ++++++++++++++++++++++++++
 hw/expansion/fp-lib-table        |   3 +
 hw/expansion/sym-lib-table       |   3 +
 5 files changed, 844 insertions(+)
 create mode 100644 hw/expansion/expansion.kicad_pcb
 create mode 100644 hw/expansion/expansion.pro
 create mode 100644 hw/expansion/expansion.sch
 create mode 100644 hw/expansion/fp-lib-table
 create mode 100644 hw/expansion/sym-lib-table

(limited to 'hw/expansion')

diff --git a/hw/expansion/expansion.kicad_pcb b/hw/expansion/expansion.kicad_pcb
new file mode 100644
index 0000000..e974d49
--- /dev/null
+++ b/hw/expansion/expansion.kicad_pcb
@@ -0,0 +1,352 @@
+(kicad_pcb (version 20171130) (host pcbnew "(5.1.9-0-10_14)")
+
+  (general
+    (thickness 1.6)
+    (drawings 8)
+    (tracks 4)
+    (zones 0)
+    (modules 3)
+    (nets 15)
+  )
+
+  (page A4)
+  (title_block
+    (title "mikroPhone expansion breakout")
+    (date 2024-02-02)
+    (rev 4.0)
+  )
+
+  (layers
+    (0 F.Cu signal)
+    (1 GND power)
+    (2 PWR power)
+    (31 B.Cu signal)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user hide)
+    (49 F.Fab user hide)
+  )
+
+  (setup
+    (last_trace_width 0.2)
+    (trace_clearance 0.2)
+    (zone_clearance 0.2032)
+    (zone_45_only no)
+    (trace_min 0.1524)
+    (via_size 0.6)
+    (via_drill 0.3)
+    (via_min_size 0.4)
+    (via_min_drill 0.2)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (edge_width 0.05)
+    (segment_width 0.2)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.12)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes true)
+      (usegerberadvancedattributes true)
+      (creategerberjobfile true)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 GND)
+  (net 2 +3V3)
+  (net 3 /SPI_MOSI)
+  (net 4 /SPI_MISO)
+  (net 5 /SPI_SCK)
+  (net 6 /UART_TX)
+  (net 7 /UART_RX)
+  (net 8 VDD)
+  (net 9 /I2C_SDA)
+  (net 10 /I2C_SCL)
+  (net 11 /GPIO3)
+  (net 12 /GPIO2)
+  (net 13 /INT)
+  (net 14 /GPIO0)
+
+  (net_class Default "This is the default net class."
+    (clearance 0.2)
+    (trace_width 0.2)
+    (via_dia 0.6)
+    (via_drill 0.3)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net +3V3)
+    (add_net /GPIO0)
+    (add_net /GPIO2)
+    (add_net /GPIO3)
+    (add_net /I2C_SCL)
+    (add_net /I2C_SDA)
+    (add_net /INT)
+    (add_net /SPI_MISO)
+    (add_net /SPI_MOSI)
+    (add_net /SPI_SCK)
+    (add_net /UART_RX)
+    (add_net /UART_TX)
+    (add_net GND)
+    (add_net VDD)
+  )
+
+  (module Connector_Molex:Molex_SlimStack_55560-0161_2x08_P0.50mm_Vertical (layer B.Cu) (tedit 60DA23A1) (tstamp 60DA7D5B)
+    (at 231 140.1 180)
+    (descr "Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0161, 16 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator")
+    (tags "connector Molex SlimStack side entry")
+    (path /60DA2442)
+    (attr smd)
+    (fp_text reference J1 (at 3.75 0 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value IN (at 0 3.65) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start 2.725 1.415) (end 2.725 -1.415) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.725 -1.415) (end -2.725 -1.415) (layer B.Fab) (width 0.1))
+    (fp_line (start -2.725 -1.415) (end -2.725 1.415) (layer B.Fab) (width 0.1))
+    (fp_line (start -2.725 1.415) (end 2.725 1.415) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.16 1.525) (end 2.16 2.215) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.16 -1.525) (end 2.835 -1.525) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.835 -1.525) (end 2.835 1.525) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.835 1.525) (end 2.16 1.525) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.16 1.525) (end 2.16 2.215) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.16 -1.525) (end -2.835 -1.525) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.835 -1.525) (end -2.835 1.525) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.835 1.525) (end -2.16 1.525) (layer B.SilkS) (width 0.12))
+    (fp_line (start 3.22 2.95) (end 3.22 -2.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 3.22 -2.95) (end -3.22 -2.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -3.22 -2.95) (end -3.22 2.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -3.22 2.95) (end 3.22 2.95) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (pad 1 smd rect (at 1.75 1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 2 +3V3))
+    (pad 3 smd rect (at 1.25 1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 2 +3V3))
+    (pad 5 smd rect (at 0.75 1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 1 GND))
+    (pad 7 smd rect (at 0.25 1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 3 /SPI_MOSI))
+    (pad 9 smd rect (at -0.25 1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 4 /SPI_MISO))
+    (pad 11 smd rect (at -0.75 1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 5 /SPI_SCK))
+    (pad 13 smd rect (at -1.25 1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 6 /UART_TX))
+    (pad 15 smd rect (at -1.75 1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 7 /UART_RX))
+    (pad 2 smd rect (at 1.75 -1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 8 VDD))
+    (pad 4 smd rect (at 1.25 -1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 1 GND))
+    (pad 6 smd rect (at 0.75 -1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 13 /INT))
+    (pad 8 smd rect (at 0.25 -1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 11 /GPIO3))
+    (pad 10 smd rect (at -0.25 -1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 12 /GPIO2))
+    (pad 12 smd rect (at -0.75 -1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 9 /I2C_SDA))
+    (pad 14 smd rect (at -1.25 -1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 10 /I2C_SCL))
+    (pad 16 smd rect (at -1.75 -1.95 180) (size 0.3 1) (layers B.Cu B.Paste B.Mask)
+      (net 14 /GPIO0))
+    (model ${KISYS3DMOD}/Connector_Molex.3dshapes/Molex_SlimStack_55560-0161_2x08_P0.50mm_Vertical.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module footprints:Spacer_small (layer F.Cu) (tedit 61BFD32E) (tstamp 65BE3852)
+    (at 237 141.2)
+    (path /65BF75AF)
+    (fp_text reference J3 (at 0 2.8) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Spacer (at 0 -2.7) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 2.1) (layers *.Cu *.Mask)
+      (net 1 GND))
+    (pad 1 smd circle (at 0 0) (size 4 4) (layers F.Cu F.Mask)
+      (net 1 GND))
+  )
+
+  (module footprints:Spacer_small (layer F.Cu) (tedit 61BFD32E) (tstamp 65BE3858)
+    (at 217 141.2)
+    (path /65BF7FCD)
+    (fp_text reference J4 (at 0 2.8) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Spacer (at 0 -2.7) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 smd circle (at 0 0) (size 4 4) (layers F.Cu F.Mask)
+      (net 1 GND))
+    (pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 2.1) (layers *.Cu *.Mask)
+      (net 1 GND))
+  )
+
+  (gr_line (start 238.2 143.9) (end 215.8 143.9) (layer Edge.Cuts) (width 0.5) (tstamp 60DA3AA5))
+  (gr_arc (start 238.2 142.4) (end 238.2 143.9) (angle -90) (layer Edge.Cuts) (width 0.5) (tstamp 60DA3A98))
+  (gr_arc (start 215.8 142.4) (end 214.3 142.4) (angle -90) (layer Edge.Cuts) (width 0.5) (tstamp 60DA3A98))
+  (gr_line (start 214.3 120.4) (end 214.3 142.4) (layer Edge.Cuts) (width 0.5))
+  (gr_arc (start 215.8 120.4) (end 215.8 118.9) (angle -90) (layer Edge.Cuts) (width 0.5) (tstamp 60DA3A98))
+  (gr_line (start 238.2 118.9) (end 215.8 118.9) (layer Edge.Cuts) (width 0.5))
+  (gr_line (start 239.7 120.4) (end 239.7 142.4) (layer Edge.Cuts) (width 0.5))
+  (gr_arc (start 238.2 120.4) (end 239.7 120.4) (angle -90) (layer Edge.Cuts) (width 0.5) (tstamp 60DA37D1))
+
+  (via (at 230.25 139.15) (size 0.6) (drill 0.3) (layers F.Cu B.Cu) (net 1))
+  (segment (start 230.25 138.15) (end 230.25 139.15) (width 0.2) (layer B.Cu) (net 1))
+  (via (at 229.75 143.05) (size 0.6) (drill 0.3) (layers F.Cu B.Cu) (net 1))
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+
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+        (xy 235.16825 140.851662) (xy 235.13549 141.215712) (xy 218.861682 141.215712) (xy 218.86451 141.184288) (xy 218.82562 140.820842)
+        (xy 218.716571 140.471967) (xy 218.559013 140.177197) (xy 218.316881 140.008843) (xy 217.125724 141.2) (xy 216.874276 141.2)
+        (xy 215.683119 140.008843) (xy 215.440987 140.177197) (xy 215.271404 140.500998) (xy 215.16825 140.851662) (xy 215.13549 141.215712)
+        (xy 214.8548 141.215712) (xy 214.8548 139.883119) (xy 215.808843 139.883119) (xy 217 141.074276) (xy 218.191157 139.883119)
+        (xy 235.808843 139.883119) (xy 237 141.074276) (xy 238.191157 139.883119) (xy 238.022803 139.640987) (xy 237.699002 139.471404)
+        (xy 237.348338 139.36825) (xy 236.984288 139.33549) (xy 236.620842 139.37438) (xy 236.271967 139.483429) (xy 235.977197 139.640987)
+        (xy 235.808843 139.883119) (xy 218.191157 139.883119) (xy 218.022803 139.640987) (xy 217.699002 139.471404) (xy 217.348338 139.36825)
+        (xy 216.984288 139.33549) (xy 216.620842 139.37438) (xy 216.271967 139.483429) (xy 215.977197 139.640987) (xy 215.808843 139.883119)
+        (xy 214.8548 139.883119) (xy 214.8548 120.427131) (xy 214.87541 120.216928) (xy 214.928579 120.040824) (xy 215.014938 119.878408)
+        (xy 215.1312 119.735856) (xy 215.272939 119.6186) (xy 215.434755 119.531106) (xy 215.610473 119.476712) (xy 215.818957 119.4548)
+        (xy 238.172869 119.4548)
+      )
+    )
+  )
+  (zone (net 2) (net_name +3V3) (layer B.Cu) (tstamp 65BE54EC) (hatch edge 0.508)
+    (connect_pads yes (clearance 0.2032))
+    (min_thickness 0.254)
+    (fill yes (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.381))
+    (polygon
+      (pts
+        (xy 229.1 137.85) (xy 229.1 138.45) (xy 229.9 138.45) (xy 229.9 137.85)
+      )
+    )
+    (filled_polygon
+      (pts
+        (xy 229.768203 138.323) (xy 229.227 138.323) (xy 229.227 137.977) (xy 229.768203 137.977)
+      )
+    )
+  )
+)
diff --git a/hw/expansion/expansion.pro b/hw/expansion/expansion.pro
new file mode 100644
index 0000000..5327bd4
--- /dev/null
+++ b/hw/expansion/expansion.pro
@@ -0,0 +1,248 @@
+update=Saturday, February 03, 2024 at 05:34:54 PM
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=expansion.net
+CopperLayerCount=4
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.1524
+MinViaDiameter=0.4
+MinViaDrill=0.2
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+TrackWidth1=0.2
+ViaDiameter1=0.6
+ViaDrill1=0.3
+dPairWidth1=0.2
+dPairGap1=0.25
+dPairViaGap1=0.25
+SilkLineWidth=0.12
+SilkTextSizeV=1
+SilkTextSizeH=1
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.05
+CourtyardLineWidth=0.05
+OthersLineWidth=0.15
+OthersTextSizeV=1
+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0
+SolderMaskMinWidth=0
+SolderPasteClearance=0
+SolderPasteRatio=-0
+[pcbnew/Layer.F.Cu]
+Name=F.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In1.Cu]
+Name=GND
+Type=1
+Enabled=1
+[pcbnew/Layer.In2.Cu]
+Name=PWR
+Type=1
+Enabled=1
+[pcbnew/Layer.In3.Cu]
+Name=In3.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In4.Cu]
+Name=In4.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In5.Cu]
+Name=In5.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In6.Cu]
+Name=In6.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In7.Cu]
+Name=In7.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In8.Cu]
+Name=In8.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In9.Cu]
+Name=In9.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In10.Cu]
+Name=In10.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In11.Cu]
+Name=In11.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In12.Cu]
+Name=In12.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In13.Cu]
+Name=In13.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In14.Cu]
+Name=In14.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In15.Cu]
+Name=In15.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In16.Cu]
+Name=In16.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In17.Cu]
+Name=In17.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In18.Cu]
+Name=In18.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In19.Cu]
+Name=In19.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In20.Cu]
+Name=In20.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In21.Cu]
+Name=In21.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In22.Cu]
+Name=In22.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In23.Cu]
+Name=In23.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In24.Cu]
+Name=In24.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In25.Cu]
+Name=In25.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In26.Cu]
+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=B.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=0
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.2
+TrackWidth=0.2
+ViaDiameter=0.6
+ViaDrill=0.3
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
diff --git a/hw/expansion/expansion.sch b/hw/expansion/expansion.sch
new file mode 100644
index 0000000..bc01614
--- /dev/null
+++ b/hw/expansion/expansion.sch
@@ -0,0 +1,238 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Connector_Generic:Conn_02x08_Odd_Even J1
+U 1 1 60DA2442
+P 4450 3150
+F 0 "J1" H 4500 3550 50  0000 C CNN
+F 1 "IN" H 4500 2650 50  0000 C CNN
+F 2 "Connector_Molex:Molex_SlimStack_55560-0161_2x08_P0.50mm_Vertical" H 4450 3150 50  0001 C CNN
+F 3 "~" H 4450 3150 50  0001 C CNN
+	1    4450 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:GND #PWR0101
+U 1 1 60DA9CCD
+P 4150 3650
+F 0 "#PWR0101" H 4150 3400 50  0001 C CNN
+F 1 "GND" H 4150 3500 50  0000 C CNN
+F 2 "" H 4150 3650 50  0001 C CNN
+F 3 "" H 4150 3650 50  0001 C CNN
+	1    4150 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:PWR_FLAG #FLG0102
+U 1 1 614F0F2F
+P 3800 2750
+F 0 "#FLG0102" H 3800 2825 50  0001 C CNN
+F 1 "PWR_FLAG" H 3800 2900 50  0000 C CNN
+F 2 "" H 3800 2750 50  0001 C CNN
+F 3 "~" H 3800 2750 50  0001 C CNN
+	1    3800 2750
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:+3.3V #PWR0104
+U 1 1 614F178C
+P 4150 2750
+F 0 "#PWR0104" H 4150 2600 50  0001 C CNN
+F 1 "+3.3V" H 4150 2900 50  0000 C CNN
+F 2 "" H 4150 2750 50  0001 C CNN
+F 3 "" H 4150 2750 50  0001 C CNN
+	1    4150 2750
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4250 2850 4150 2850
+Wire Wire Line
+	4150 2850 4150 2750
+Wire Wire Line
+	4250 2950 4150 2950
+Wire Wire Line
+	4150 2950 4150 2850
+Connection ~ 4150 2850
+Wire Wire Line
+	3800 2750 3800 2850
+Wire Wire Line
+	3800 2850 4150 2850
+Text Label 5250 3350 2    50   ~ 0
+I2C_SDA
+Text Label 3750 3150 0    50   ~ 0
+SPI_MOSI
+Text Label 3750 3250 0    50   ~ 0
+SPI_MISO
+Text Label 3750 3350 0    50   ~ 0
+SPI_SCK
+Wire Wire Line
+	3750 3350 4250 3350
+Wire Wire Line
+	3750 3250 4250 3250
+Wire Wire Line
+	3750 3150 4250 3150
+$Comp
+L power:GND #PWR0107
+U 1 1 61516CA6
+P 4850 3650
+F 0 "#PWR0107" H 4850 3400 50  0001 C CNN
+F 1 "GND" H 4850 3500 50  0000 C CNN
+F 2 "" H 4850 3650 50  0001 C CNN
+F 3 "" H 4850 3650 50  0001 C CNN
+	1    4850 3650
+	1    0    0    -1  
+$EndComp
+Text Label 5250 3450 2    50   ~ 0
+I2C_SCL
+Text Label 5250 3250 2    50   ~ 0
+GPIO2
+Text Label 5250 3150 2    50   ~ 0
+GPIO3
+$Comp
+L power:VDD #PWR0108
+U 1 1 61522E27
+P 4850 2750
+F 0 "#PWR0108" H 4850 2600 50  0001 C CNN
+F 1 "VDD" H 4850 2900 50  0000 C CNN
+F 2 "" H 4850 2750 50  0001 C CNN
+F 3 "" H 4850 2750 50  0001 C CNN
+	1    4850 2750
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4750 2850 4850 2850
+Connection ~ 4850 2850
+Wire Wire Line
+	4850 2850 4850 2750
+Wire Wire Line
+	4750 3150 5250 3150
+Wire Wire Line
+	4750 3250 5250 3250
+Wire Wire Line
+	4750 3350 5250 3350
+Wire Wire Line
+	4750 3450 5250 3450
+$Comp
+L power:PWR_FLAG #FLG0103
+U 1 1 6155AB9A
+P 5200 2750
+F 0 "#FLG0103" H 5200 2825 50  0001 C CNN
+F 1 "PWR_FLAG" H 5200 2900 50  0000 C CNN
+F 2 "" H 5200 2750 50  0001 C CNN
+F 3 "~" H 5200 2750 50  0001 C CNN
+	1    5200 2750
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4850 2850 5200 2850
+Wire Wire Line
+	5200 2850 5200 2750
+$Comp
+L myConn:Spacer J3
+U 1 1 65BF75AF
+P 4500 4500
+F 0 "J3" H 4580 4542 50  0000 L CNN
+F 1 "Spacer" H 4580 4451 50  0000 L CNN
+F 2 "footprints:Spacer_small" H 4500 4500 50  0001 C CNN
+F 3 "~" H 4500 4500 50  0001 C CNN
+	1    4500 4500
+	1    0    0    -1  
+$EndComp
+$Comp
+L myConn:Spacer J4
+U 1 1 65BF7FCD
+P 4500 4700
+F 0 "J4" H 4580 4742 50  0000 L CNN
+F 1 "Spacer" H 4580 4651 50  0000 L CNN
+F 2 "footprints:Spacer_small" H 4500 4700 50  0001 C CNN
+F 3 "~" H 4500 4700 50  0001 C CNN
+	1    4500 4700
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:GND #PWR0112
+U 1 1 65BF84F2
+P 4200 4800
+F 0 "#PWR0112" H 4200 4550 50  0001 C CNN
+F 1 "GND" H 4205 4627 50  0000 C CNN
+F 2 "" H 4200 4800 50  0001 C CNN
+F 3 "" H 4200 4800 50  0001 C CNN
+	1    4200 4800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4300 4500 4200 4500
+Wire Wire Line
+	4200 4500 4200 4700
+Wire Wire Line
+	4300 4700 4200 4700
+Connection ~ 4200 4700
+Wire Wire Line
+	4200 4700 4200 4800
+Text Label 3750 3450 0    50   ~ 0
+UART_TX
+Text Label 3750 3550 0    50   ~ 0
+UART_RX
+Wire Wire Line
+	3750 3450 4250 3450
+NoConn ~ 3750 3550
+NoConn ~ 3750 3450
+NoConn ~ 3750 3350
+NoConn ~ 3750 3250
+NoConn ~ 3750 3150
+NoConn ~ 5250 3150
+NoConn ~ 5250 3250
+NoConn ~ 5250 3350
+NoConn ~ 5250 3450
+Wire Wire Line
+	3750 3550 4250 3550
+Wire Wire Line
+	4250 3050 4150 3050
+Wire Wire Line
+	4150 3050 4150 3600
+Wire Wire Line
+	3850 3600 4150 3600
+Connection ~ 4150 3600
+Wire Wire Line
+	4150 3600 4150 3650
+Wire Wire Line
+	4750 2950 4850 2950
+Wire Wire Line
+	4850 2950 4850 3650
+Wire Wire Line
+	4750 3550 5250 3550
+Text Label 5250 3550 2    50   ~ 0
+GPIO0
+Wire Wire Line
+	4750 3050 5250 3050
+Text Label 5250 3050 2    50   ~ 0
+INT
+NoConn ~ 5250 3050
+NoConn ~ 5250 3550
+$Comp
+L power:PWR_FLAG #FLG?
+U 1 1 67A74496
+P 3850 3650
+F 0 "#FLG?" H 3850 3725 50  0001 C CNN
+F 1 "PWR_FLAG" H 3850 3800 50  0000 C CNN
+F 2 "" H 3850 3650 50  0001 C CNN
+F 3 "~" H 3850 3650 50  0001 C CNN
+	1    3850 3650
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	3850 3600 3850 3650
+$EndSCHEMATC
diff --git a/hw/expansion/fp-lib-table b/hw/expansion/fp-lib-table
new file mode 100644
index 0000000..2322dfd
--- /dev/null
+++ b/hw/expansion/fp-lib-table
@@ -0,0 +1,3 @@
+(fp_lib_table
+  (lib (name footprints)(type KiCad)(uri ${KIPRJMOD}/../footprints.pretty)(options "")(descr ""))
+)
diff --git a/hw/expansion/sym-lib-table b/hw/expansion/sym-lib-table
new file mode 100644
index 0000000..9da3cf7
--- /dev/null
+++ b/hw/expansion/sym-lib-table
@@ -0,0 +1,3 @@
+(sym_lib_table
+  (lib (name myConn)(type Legacy)(uri ${KIPRJMOD}/../library/myConn.lib)(options "")(descr ""))
+)
-- 
cgit v1.2.3