#include <stdlib.h>
#include <stdint.h>
#include <string.h>

#include "platform.h"
#include "ili9806e.h"

#ifdef DRV_DEBUG
#include <stdio.h>
#endif

int ili9806e_init(void) {
    int rv;
    uint8_t chip_id[3];

    drv_spi_cs_set();

    /* LCD Setting */
    drv_spi9bit_write(0, 0xFF);     // change to Page 1 CMD
    drv_spi9bit_write(1, 0xFF);
    drv_spi9bit_write(1, 0x98);
    drv_spi9bit_write(1, 0x06);
    drv_spi9bit_write(1, 0x04);
    drv_spi9bit_write(1, 0x01);

    // drv_spi9bit_write(0, 0x08);  // Output SDA
    // drv_spi9bit_write(1, 0x10);

    drv_spi9bit_write(0, 0xFE);     // enable read
    drv_spi9bit_write(1, 0x81);

    drv_spi9bit_write(0, 0x00);     // RDID4
    drv_spi9bit_read(&chip_id[0]);

    drv_spi9bit_write(0, 0x01);
    drv_spi9bit_read(&chip_id[1]);

    drv_spi9bit_write(0, 0x02);
    drv_spi9bit_read(&chip_id[2]);

#ifdef DRV_DEBUG
    printf("LCD CHIP ID: %.2x%.2x%.2x\n", chip_id[0], chip_id[1], chip_id[2]);
#endif

    drv_spi9bit_write(0, 0xFE);     // disable read
    drv_spi9bit_write(1, 0x00);

    if (memcmp(chip_id, "\x98\x06\x04", sizeof(chip_id))) {
        drv_spi_cs_clear();
        return DRV_ERR_NOTFOUND;
    }

    drv_spi9bit_write(0, 0x20);     // set DE/VSYNC mode
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x21);     // DE = 1 Active
    drv_spi9bit_write(1, 0x01);

    drv_spi9bit_write(0, 0x30);     // resolution setting 480 X 854
    drv_spi9bit_write(1, 0x01);

    drv_spi9bit_write(0, 0x31);     // inversion setting 2-dot
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x40);     // BT AVDD,AVDD
    drv_spi9bit_write(1, 0x16);

    drv_spi9bit_write(0, 0x41);
    drv_spi9bit_write(1, 0x33);     // 22

    drv_spi9bit_write(0, 0x42);
    drv_spi9bit_write(1, 0x03);     // VGL=DDVDH+VCIP-DDVDL, VGH=2DDVDL-VCIP

    drv_spi9bit_write(0, 0x43);
    drv_spi9bit_write(1, 0x09);     // set VGH clamp level

    drv_spi9bit_write(0, 0x44);
    drv_spi9bit_write(1, 0x06);     // set VGL clamp level

    drv_spi9bit_write(0, 0x50);     // VREG1
    drv_spi9bit_write(1, 0x88);

    drv_spi9bit_write(0, 0x51);     // VREG2
    drv_spi9bit_write(1, 0x88);

    drv_spi9bit_write(0, 0x52);     // flicker MSB
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x53);     // flicker LSB
    drv_spi9bit_write(1, 0x49);     // VCOM

    drv_spi9bit_write(0, 0x55);     // flicker
    drv_spi9bit_write(1, 0x49);

    drv_spi9bit_write(0, 0x60);
    drv_spi9bit_write(1, 0x07);

    drv_spi9bit_write(0, 0x61);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x62);
    drv_spi9bit_write(1, 0x07);

    drv_spi9bit_write(0, 0x63);
    drv_spi9bit_write(1, 0x00);

    /* Gamma Setting */
    drv_spi9bit_write(0, 0xA0);     // positive Gamma
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0xA1);
    drv_spi9bit_write(1, 0x09);

    drv_spi9bit_write(0, 0xA2);
    drv_spi9bit_write(1, 0x11);

    drv_spi9bit_write(0, 0xA3);
    drv_spi9bit_write(1, 0x0B);

    drv_spi9bit_write(0, 0xA4);
    drv_spi9bit_write(1, 0x05);

    drv_spi9bit_write(0, 0xA5);
    drv_spi9bit_write(1, 0x08);

    drv_spi9bit_write(0, 0xA6);
    drv_spi9bit_write(1, 0x06);

    drv_spi9bit_write(0, 0xA7);
    drv_spi9bit_write(1, 0x04);

    drv_spi9bit_write(0, 0xA8);
    drv_spi9bit_write(1, 0x09);

    drv_spi9bit_write(0, 0xA9);
    drv_spi9bit_write(1, 0x0C);

    drv_spi9bit_write(0, 0xAA);
    drv_spi9bit_write(1, 0x15);

    drv_spi9bit_write(0, 0xAB);
    drv_spi9bit_write(1, 0x08);

    drv_spi9bit_write(0, 0xAC);
    drv_spi9bit_write(1, 0x0F);

    drv_spi9bit_write(0, 0xAD);
    drv_spi9bit_write(1, 0x12);

    drv_spi9bit_write(0, 0xAE);
    drv_spi9bit_write(1, 0x09);

    drv_spi9bit_write(0, 0xAF);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0xC0);     // negative Gamma
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0xC1);
    drv_spi9bit_write(1, 0x09);

    drv_spi9bit_write(0, 0xC2);
    drv_spi9bit_write(1, 0x10);

    drv_spi9bit_write(0, 0xC3);
    drv_spi9bit_write(1, 0x0C);

    drv_spi9bit_write(0, 0xC4);
    drv_spi9bit_write(1, 0x05);

    drv_spi9bit_write(0, 0xC5);
    drv_spi9bit_write(1, 0x08);

    drv_spi9bit_write(0, 0xC6);
    drv_spi9bit_write(1, 0x06);

    drv_spi9bit_write(0, 0xC7);
    drv_spi9bit_write(1, 0x04);

    drv_spi9bit_write(0, 0xC8);
    drv_spi9bit_write(1, 0x08);

    drv_spi9bit_write(0, 0xC9);
    drv_spi9bit_write(1, 0x0C);

    drv_spi9bit_write(0, 0xCA);
    drv_spi9bit_write(1, 0x14);

    drv_spi9bit_write(0, 0xCB);
    drv_spi9bit_write(1, 0x08);

    drv_spi9bit_write(0, 0xCC);
    drv_spi9bit_write(1, 0x0F);

    drv_spi9bit_write(0, 0xCD);
    drv_spi9bit_write(1, 0x11);

    drv_spi9bit_write(0, 0xCE);
    drv_spi9bit_write(1, 0x09);

    drv_spi9bit_write(0, 0xCF);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0xFF);     // change to Page 6 CMD for GIP timing
    drv_spi9bit_write(1, 0xFF);
    drv_spi9bit_write(1, 0x98);
    drv_spi9bit_write(1, 0x06);
    drv_spi9bit_write(1, 0x04);
    drv_spi9bit_write(1, 0x06);

    drv_spi9bit_write(0, 0x00);
    drv_spi9bit_write(1, 0x20);

    drv_spi9bit_write(0, 0x01);
    drv_spi9bit_write(1, 0x0A);

    drv_spi9bit_write(0, 0x02);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x03);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x04);
    drv_spi9bit_write(1, 0x01);

    drv_spi9bit_write(0, 0x05);
    drv_spi9bit_write(1, 0x01);

    drv_spi9bit_write(0, 0x06);
    drv_spi9bit_write(1, 0x98);

    drv_spi9bit_write(0, 0x07);
    drv_spi9bit_write(1, 0x06);

    drv_spi9bit_write(0, 0x08);
    drv_spi9bit_write(1, 0x01);

    drv_spi9bit_write(0, 0x09);
    drv_spi9bit_write(1, 0x80);

    drv_spi9bit_write(0, 0x0A);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x0B);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x0C);
    drv_spi9bit_write(1, 0x01);

    drv_spi9bit_write(0, 0x0D);
    drv_spi9bit_write(1, 0x01);

    drv_spi9bit_write(0, 0x0E);
    drv_spi9bit_write(1, 0x05);

    drv_spi9bit_write(0, 0x0F);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x10);
    drv_spi9bit_write(1, 0xF0);

    drv_spi9bit_write(0, 0x11);
    drv_spi9bit_write(1, 0xF4);

    drv_spi9bit_write(0, 0x12);
    drv_spi9bit_write(1, 0x01);

    drv_spi9bit_write(0, 0x13);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x14);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x15);
    drv_spi9bit_write(1, 0xC0);

    drv_spi9bit_write(0, 0x16);
    drv_spi9bit_write(1, 0x08);

    drv_spi9bit_write(0, 0x17);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x18);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x19);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x1A);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x1B);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x1C);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x1D);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x20);
    drv_spi9bit_write(1, 0x01);

    drv_spi9bit_write(0, 0x21);
    drv_spi9bit_write(1, 0x23);

    drv_spi9bit_write(0, 0x22);
    drv_spi9bit_write(1, 0x45);

    drv_spi9bit_write(0, 0x23);
    drv_spi9bit_write(1, 0x67);

    drv_spi9bit_write(0, 0x24);
    drv_spi9bit_write(1, 0x01);

    drv_spi9bit_write(0, 0x25);
    drv_spi9bit_write(1, 0x23);

    drv_spi9bit_write(0, 0x26);
    drv_spi9bit_write(1, 0x45);

    drv_spi9bit_write(0, 0x27);
    drv_spi9bit_write(1, 0x67);

    drv_spi9bit_write(0, 0x30);
    drv_spi9bit_write(1, 0x11);

    drv_spi9bit_write(0, 0x31);
    drv_spi9bit_write(1, 0x11);

    drv_spi9bit_write(0, 0x32);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x33);
    drv_spi9bit_write(1, 0xEE);

    drv_spi9bit_write(0, 0x34);
    drv_spi9bit_write(1, 0xFF);

    drv_spi9bit_write(0, 0x35);
    drv_spi9bit_write(1, 0xBB);

    drv_spi9bit_write(0, 0x36);
    drv_spi9bit_write(1, 0xAA);

    drv_spi9bit_write(0, 0x37);
    drv_spi9bit_write(1, 0xDD);

    drv_spi9bit_write(0, 0x38);
    drv_spi9bit_write(1, 0xCC);

    drv_spi9bit_write(0, 0x39);
    drv_spi9bit_write(1, 0x66);

    drv_spi9bit_write(0, 0x3A);
    drv_spi9bit_write(1, 0x77);

    drv_spi9bit_write(0, 0x3B);
    drv_spi9bit_write(1, 0x22);

    drv_spi9bit_write(0, 0x3C);
    drv_spi9bit_write(1, 0x22);

    drv_spi9bit_write(0, 0x3D);
    drv_spi9bit_write(1, 0x22);

    drv_spi9bit_write(0, 0x3E);
    drv_spi9bit_write(1, 0x22);

    drv_spi9bit_write(0, 0x3F);
    drv_spi9bit_write(1, 0x22);

    drv_spi9bit_write(0, 0x40);
    drv_spi9bit_write(1, 0x22);

    drv_spi9bit_write(0, 0xFF);     // change to Page 7 CMD for GIP timing
    drv_spi9bit_write(1, 0xFF);
    drv_spi9bit_write(1, 0x98);
    drv_spi9bit_write(1, 0x06);
    drv_spi9bit_write(1, 0x04);
    drv_spi9bit_write(1, 0x07);

    drv_spi9bit_write(0, 0x17);
    drv_spi9bit_write(1, 0x22);

    drv_spi9bit_write(0, 0x02);
    drv_spi9bit_write(1, 0x77);

    drv_spi9bit_write(0, 0x26);
    drv_spi9bit_write(1, 0xB2);

    drv_spi9bit_write(0, 0xFF);     // change to Page 0 CMD for normal command
    drv_spi9bit_write(1, 0xFF);
    drv_spi9bit_write(1, 0x98);
    drv_spi9bit_write(1, 0x06);
    drv_spi9bit_write(1, 0x04);
    drv_spi9bit_write(1, 0x00);

    drv_spi9bit_write(0, 0x3A);
    drv_spi9bit_write(1, 0x70);     // 24BIT

    drv_spi9bit_write(0, 0x11);
    drv_sleep(120);
    drv_spi9bit_write(0, 0x29);
    drv_sleep(25);

    drv_spi_cs_clear();

    return DRV_OK;
}

void ili9806e_sleep(void) {
    drv_spi_cs_set();

    drv_spi9bit_write(0, 0x28);
    drv_sleep(10);
    drv_spi9bit_write(0, 0x10);

    drv_spi_cs_clear();

}

void ili9806e_wake(void) {
    drv_spi_cs_set();

    drv_spi9bit_write(0, 0x11);
    drv_sleep(120);
    drv_spi9bit_write(0, 0x29);

    drv_spi_cs_clear();
}