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-rw-r--r--fw/fe310/eos/dev/ili9806e.c431
1 files changed, 431 insertions, 0 deletions
diff --git a/fw/fe310/eos/dev/ili9806e.c b/fw/fe310/eos/dev/ili9806e.c
new file mode 100644
index 0000000..b8bc67f
--- /dev/null
+++ b/fw/fe310/eos/dev/ili9806e.c
@@ -0,0 +1,431 @@
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+
+#include "eos.h"
+
+#include "soc/spi.h"
+#include "soc/spi9bit.h"
+#include "soc/timer.h"
+
+#include "ili9806e.h"
+
+int eos_ili9806e_init(void) {
+ int rv;
+ uint8_t chip_id[3];
+
+ eos_spi_cs_set();
+
+ /* LCD Setting */
+ eos_spi9bit_write(0, 0xFF); // change to Page 1 CMD
+ eos_spi9bit_write(1, 0xFF);
+ eos_spi9bit_write(1, 0x98);
+ eos_spi9bit_write(1, 0x06);
+ eos_spi9bit_write(1, 0x04);
+ eos_spi9bit_write(1, 0x01);
+
+ // eos_spi9bit_write(0, 0x08); // Output SDA
+ // eos_spi9bit_write(1, 0x10);
+
+ eos_spi9bit_write(0, 0xFE); // enable read
+ eos_spi9bit_write(1, 0x81);
+
+ eos_spi9bit_write(0, 0x00); // RDID4
+ eos_spi9bit_read(&chip_id[0]);
+
+ eos_spi9bit_write(0, 0x01);
+ eos_spi9bit_read(&chip_id[1]);
+
+ eos_spi9bit_write(0, 0x02);
+ eos_spi9bit_read(&chip_id[2]);
+
+ printf("LCD CHIP ID: %.2x%.2x%.2x\n", chip_id[0], chip_id[1], chip_id[2]);
+
+ eos_spi9bit_write(0, 0xFE); // disable read
+ eos_spi9bit_write(1, 0x00);
+
+ if (memcmp(chip_id, "\x98\x06\x04", sizeof(chip_id))) {
+ eos_spi_cs_clear();
+ return EOS_ERR_ABSENT;
+ }
+
+ eos_spi9bit_write(0, 0x20); // set DE/VSYNC mode
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x21); // DE = 1 Active
+ eos_spi9bit_write(1, 0x01);
+
+ eos_spi9bit_write(0, 0x30); // resolution setting 480 X 854
+ eos_spi9bit_write(1, 0x01);
+
+ eos_spi9bit_write(0, 0x31); // inversion setting 2-dot
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x40); // BT AVDD,AVDD
+ eos_spi9bit_write(1, 0x16);
+
+ eos_spi9bit_write(0, 0x41);
+ eos_spi9bit_write(1, 0x33); // 22
+
+ eos_spi9bit_write(0, 0x42);
+ eos_spi9bit_write(1, 0x03); // VGL=DDVDH+VCIP-DDVDL, VGH=2DDVDL-VCIP
+
+ eos_spi9bit_write(0, 0x43);
+ eos_spi9bit_write(1, 0x09); // set VGH clamp level
+
+ eos_spi9bit_write(0, 0x44);
+ eos_spi9bit_write(1, 0x06); // set VGL clamp level
+
+ eos_spi9bit_write(0, 0x50); // VREG1
+ eos_spi9bit_write(1, 0x88);
+
+ eos_spi9bit_write(0, 0x51); // VREG2
+ eos_spi9bit_write(1, 0x88);
+
+ eos_spi9bit_write(0, 0x52); // flicker MSB
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x53); // flicker LSB
+ eos_spi9bit_write(1, 0x49); // VCOM
+
+ eos_spi9bit_write(0, 0x55); // flicker
+ eos_spi9bit_write(1, 0x49);
+
+ eos_spi9bit_write(0, 0x60);
+ eos_spi9bit_write(1, 0x07);
+
+ eos_spi9bit_write(0, 0x61);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x62);
+ eos_spi9bit_write(1, 0x07);
+
+ eos_spi9bit_write(0, 0x63);
+ eos_spi9bit_write(1, 0x00);
+
+ /* Gamma Setting */
+ eos_spi9bit_write(0, 0xA0); // positive Gamma
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0xA1);
+ eos_spi9bit_write(1, 0x09);
+
+ eos_spi9bit_write(0, 0xA2);
+ eos_spi9bit_write(1, 0x11);
+
+ eos_spi9bit_write(0, 0xA3);
+ eos_spi9bit_write(1, 0x0B);
+
+ eos_spi9bit_write(0, 0xA4);
+ eos_spi9bit_write(1, 0x05);
+
+ eos_spi9bit_write(0, 0xA5);
+ eos_spi9bit_write(1, 0x08);
+
+ eos_spi9bit_write(0, 0xA6);
+ eos_spi9bit_write(1, 0x06);
+
+ eos_spi9bit_write(0, 0xA7);
+ eos_spi9bit_write(1, 0x04);
+
+ eos_spi9bit_write(0, 0xA8);
+ eos_spi9bit_write(1, 0x09);
+
+ eos_spi9bit_write(0, 0xA9);
+ eos_spi9bit_write(1, 0x0C);
+
+ eos_spi9bit_write(0, 0xAA);
+ eos_spi9bit_write(1, 0x15);
+
+ eos_spi9bit_write(0, 0xAB);
+ eos_spi9bit_write(1, 0x08);
+
+ eos_spi9bit_write(0, 0xAC);
+ eos_spi9bit_write(1, 0x0F);
+
+ eos_spi9bit_write(0, 0xAD);
+ eos_spi9bit_write(1, 0x12);
+
+ eos_spi9bit_write(0, 0xAE);
+ eos_spi9bit_write(1, 0x09);
+
+ eos_spi9bit_write(0, 0xAF);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0xC0); // negative Gamma
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0xC1);
+ eos_spi9bit_write(1, 0x09);
+
+ eos_spi9bit_write(0, 0xC2);
+ eos_spi9bit_write(1, 0x10);
+
+ eos_spi9bit_write(0, 0xC3);
+ eos_spi9bit_write(1, 0x0C);
+
+ eos_spi9bit_write(0, 0xC4);
+ eos_spi9bit_write(1, 0x05);
+
+ eos_spi9bit_write(0, 0xC5);
+ eos_spi9bit_write(1, 0x08);
+
+ eos_spi9bit_write(0, 0xC6);
+ eos_spi9bit_write(1, 0x06);
+
+ eos_spi9bit_write(0, 0xC7);
+ eos_spi9bit_write(1, 0x04);
+
+ eos_spi9bit_write(0, 0xC8);
+ eos_spi9bit_write(1, 0x08);
+
+ eos_spi9bit_write(0, 0xC9);
+ eos_spi9bit_write(1, 0x0C);
+
+ eos_spi9bit_write(0, 0xCA);
+ eos_spi9bit_write(1, 0x14);
+
+ eos_spi9bit_write(0, 0xCB);
+ eos_spi9bit_write(1, 0x08);
+
+ eos_spi9bit_write(0, 0xCC);
+ eos_spi9bit_write(1, 0x0F);
+
+ eos_spi9bit_write(0, 0xCD);
+ eos_spi9bit_write(1, 0x11);
+
+ eos_spi9bit_write(0, 0xCE);
+ eos_spi9bit_write(1, 0x09);
+
+ eos_spi9bit_write(0, 0xCF);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0xFF); // change to Page 6 CMD for GIP timing
+ eos_spi9bit_write(1, 0xFF);
+ eos_spi9bit_write(1, 0x98);
+ eos_spi9bit_write(1, 0x06);
+ eos_spi9bit_write(1, 0x04);
+ eos_spi9bit_write(1, 0x06);
+
+ eos_spi9bit_write(0, 0x00);
+ eos_spi9bit_write(1, 0x20);
+
+ eos_spi9bit_write(0, 0x01);
+ eos_spi9bit_write(1, 0x0A);
+
+ eos_spi9bit_write(0, 0x02);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x03);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x04);
+ eos_spi9bit_write(1, 0x01);
+
+ eos_spi9bit_write(0, 0x05);
+ eos_spi9bit_write(1, 0x01);
+
+ eos_spi9bit_write(0, 0x06);
+ eos_spi9bit_write(1, 0x98);
+
+ eos_spi9bit_write(0, 0x07);
+ eos_spi9bit_write(1, 0x06);
+
+ eos_spi9bit_write(0, 0x08);
+ eos_spi9bit_write(1, 0x01);
+
+ eos_spi9bit_write(0, 0x09);
+ eos_spi9bit_write(1, 0x80);
+
+ eos_spi9bit_write(0, 0x0A);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x0B);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x0C);
+ eos_spi9bit_write(1, 0x01);
+
+ eos_spi9bit_write(0, 0x0D);
+ eos_spi9bit_write(1, 0x01);
+
+ eos_spi9bit_write(0, 0x0E);
+ eos_spi9bit_write(1, 0x05);
+
+ eos_spi9bit_write(0, 0x0F);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x10);
+ eos_spi9bit_write(1, 0xF0);
+
+ eos_spi9bit_write(0, 0x11);
+ eos_spi9bit_write(1, 0xF4);
+
+ eos_spi9bit_write(0, 0x12);
+ eos_spi9bit_write(1, 0x01);
+
+ eos_spi9bit_write(0, 0x13);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x14);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x15);
+ eos_spi9bit_write(1, 0xC0);
+
+ eos_spi9bit_write(0, 0x16);
+ eos_spi9bit_write(1, 0x08);
+
+ eos_spi9bit_write(0, 0x17);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x18);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x19);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x1A);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x1B);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x1C);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x1D);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x20);
+ eos_spi9bit_write(1, 0x01);
+
+ eos_spi9bit_write(0, 0x21);
+ eos_spi9bit_write(1, 0x23);
+
+ eos_spi9bit_write(0, 0x22);
+ eos_spi9bit_write(1, 0x45);
+
+ eos_spi9bit_write(0, 0x23);
+ eos_spi9bit_write(1, 0x67);
+
+ eos_spi9bit_write(0, 0x24);
+ eos_spi9bit_write(1, 0x01);
+
+ eos_spi9bit_write(0, 0x25);
+ eos_spi9bit_write(1, 0x23);
+
+ eos_spi9bit_write(0, 0x26);
+ eos_spi9bit_write(1, 0x45);
+
+ eos_spi9bit_write(0, 0x27);
+ eos_spi9bit_write(1, 0x67);
+
+ eos_spi9bit_write(0, 0x30);
+ eos_spi9bit_write(1, 0x11);
+
+ eos_spi9bit_write(0, 0x31);
+ eos_spi9bit_write(1, 0x11);
+
+ eos_spi9bit_write(0, 0x32);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x33);
+ eos_spi9bit_write(1, 0xEE);
+
+ eos_spi9bit_write(0, 0x34);
+ eos_spi9bit_write(1, 0xFF);
+
+ eos_spi9bit_write(0, 0x35);
+ eos_spi9bit_write(1, 0xBB);
+
+ eos_spi9bit_write(0, 0x36);
+ eos_spi9bit_write(1, 0xAA);
+
+ eos_spi9bit_write(0, 0x37);
+ eos_spi9bit_write(1, 0xDD);
+
+ eos_spi9bit_write(0, 0x38);
+ eos_spi9bit_write(1, 0xCC);
+
+ eos_spi9bit_write(0, 0x39);
+ eos_spi9bit_write(1, 0x66);
+
+ eos_spi9bit_write(0, 0x3A);
+ eos_spi9bit_write(1, 0x77);
+
+ eos_spi9bit_write(0, 0x3B);
+ eos_spi9bit_write(1, 0x22);
+
+ eos_spi9bit_write(0, 0x3C);
+ eos_spi9bit_write(1, 0x22);
+
+ eos_spi9bit_write(0, 0x3D);
+ eos_spi9bit_write(1, 0x22);
+
+ eos_spi9bit_write(0, 0x3E);
+ eos_spi9bit_write(1, 0x22);
+
+ eos_spi9bit_write(0, 0x3F);
+ eos_spi9bit_write(1, 0x22);
+
+ eos_spi9bit_write(0, 0x40);
+ eos_spi9bit_write(1, 0x22);
+
+ eos_spi9bit_write(0, 0xFF); // change to Page 7 CMD for GIP timing
+ eos_spi9bit_write(1, 0xFF);
+ eos_spi9bit_write(1, 0x98);
+ eos_spi9bit_write(1, 0x06);
+ eos_spi9bit_write(1, 0x04);
+ eos_spi9bit_write(1, 0x07);
+
+ eos_spi9bit_write(0, 0x17);
+ eos_spi9bit_write(1, 0x22);
+
+ eos_spi9bit_write(0, 0x02);
+ eos_spi9bit_write(1, 0x77);
+
+ eos_spi9bit_write(0, 0x26);
+ eos_spi9bit_write(1, 0xB2);
+
+ eos_spi9bit_write(0, 0xFF); // change to Page 0 CMD for normal command
+ eos_spi9bit_write(1, 0xFF);
+ eos_spi9bit_write(1, 0x98);
+ eos_spi9bit_write(1, 0x06);
+ eos_spi9bit_write(1, 0x04);
+ eos_spi9bit_write(1, 0x00);
+
+ eos_spi9bit_write(0, 0x3A);
+ eos_spi9bit_write(1, 0x70); // 24BIT
+
+ eos_spi9bit_write(0, 0x11);
+ eos_time_sleep(120);
+ eos_spi9bit_write(0, 0x29);
+ eos_time_sleep(25);
+
+ eos_spi_cs_clear();
+
+ return EOS_OK;
+}
+
+void eos_ili9806e_sleep(void) {
+ eos_spi_cs_set();
+
+ eos_spi9bit_write(0, 0x28);
+ eos_time_sleep(10);
+ eos_spi9bit_write(0, 0x10);
+
+ eos_spi_cs_clear();
+
+}
+
+void eos_ili9806e_wake(void) {
+ eos_spi_cs_set();
+
+ eos_spi9bit_write(0, 0x11);
+ eos_time_sleep(120);
+ eos_spi9bit_write(0, 0x29);
+
+ eos_spi_cs_clear();
+}
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