diff options
Diffstat (limited to 'hw/breakout')
| -rw-r--r-- | hw/breakout/breakout.kicad_pcb | 1025 | ||||
| -rw-r--r-- | hw/breakout/breakout.net | 175 | ||||
| -rw-r--r-- | hw/breakout/breakout.pro | 248 | ||||
| -rw-r--r-- | hw/breakout/breakout.sch | 414 |
4 files changed, 1862 insertions, 0 deletions
diff --git a/hw/breakout/breakout.kicad_pcb b/hw/breakout/breakout.kicad_pcb new file mode 100644 index 0000000..7e933a7 --- /dev/null +++ b/hw/breakout/breakout.kicad_pcb @@ -0,0 +1,1025 @@ +(kicad_pcb (version 20171130) (host pcbnew "(5.1.9-0-10_14)") + + (general + (thickness 1.6) + (drawings 30) + (tracks 120) + (zones 0) + (modules 5) + (nets 17) + ) + + (page A4) + (layers + (0 F.Cu signal) + (1 GND power) + (2 PWR power) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.2) + (trace_clearance 0.2) + (zone_clearance 0.2032) + (zone_45_only no) + (trace_min 0.1524) + (via_size 0.6) + (via_drill 0.3) + (via_min_size 0.4) + (via_min_drill 0.2) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (edge_width 0.05) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.12) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 GND) + (net 2 +3V3) + (net 3 /SPI_MOSI) + (net 4 /SPI_MISO) + (net 5 /SPI_SCK) + (net 6 /UART_TX) + (net 7 /UART_RX) + (net 8 VDD) + (net 9 /SPI_CS) + (net 10 /GPIO0) + (net 11 /I2C_SDA) + (net 12 /I2C_SCL) + (net 13 /PCA_IO0) + (net 14 /PCA_IO1) + (net 15 /PCA_IO2) + (net 16 /PCA_IO3) + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.2) + (via_dia 0.6) + (via_drill 0.3) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net +3V3) + (add_net /GPIO0) + (add_net /I2C_SCL) + (add_net /I2C_SDA) + (add_net /PCA_IO0) + (add_net /PCA_IO1) + (add_net /PCA_IO2) + (add_net /PCA_IO3) + (add_net /SPI_CS) + (add_net /SPI_MISO) + (add_net /SPI_MOSI) + (add_net /SPI_SCK) + (add_net /UART_RX) + (add_net /UART_TX) + (add_net GND) + (add_net VDD) + ) + + (module Connector_PinHeader_2.54mm:PinHeader_2x08_P2.54mm_Vertical (layer F.Cu) (tedit 614F4BB0) (tstamp 614F4F46) + (at 125.76 122.35 180) + (descr "Through hole straight pin header, 2x08, 2.54mm pitch, double rows") + (tags "Through hole pin header THT 2x08 2.54mm double row") + (path /60DA3522) + (fp_text reference J2 (at -5 0 270) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Out (at 2.65 0 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -4.15 -1.8) (end 2 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.15 19.55) (end -4.15 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2 19.55) (end -4.15 19.55) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2 -1.8) (end 2 19.55) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.53 -1.33) (end 0.2 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.53 0) (end 1.53 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.07 -1.33) (end -3.67 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.07 1.27) (end -1.07 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.53 1.27) (end -1.07 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start -3.67 -1.33) (end -3.67 19.11) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.53 1.27) (end 1.53 19.11) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.53 19.11) (end -3.67 19.11) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.47 0) (end 0.2 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.47 19.05) (end 1.47 0) (layer F.Fab) (width 0.1)) + (fp_line (start -3.61 19.05) (end 1.47 19.05) (layer F.Fab) (width 0.1)) + (fp_line (start -3.61 -1.27) (end -3.61 19.05) (layer F.Fab) (width 0.1)) + (fp_line (start 0.2 -1.27) (end -3.61 -1.27) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -1.07 8.89 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole rect (at 0.2 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 9 /SPI_CS)) + (pad 2 thru_hole oval (at -2.34 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 16 /PCA_IO3)) + (pad 3 thru_hole oval (at 0.2 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 3 /SPI_MOSI)) + (pad 4 thru_hole oval (at -2.34 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 15 /PCA_IO2)) + (pad 5 thru_hole oval (at 0.2 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 4 /SPI_MISO)) + (pad 6 thru_hole oval (at -2.34 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 14 /PCA_IO1)) + (pad 7 thru_hole oval (at 0.2 7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 5 /SPI_SCK)) + (pad 8 thru_hole oval (at -2.34 7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 13 /PCA_IO0)) + (pad 9 thru_hole oval (at 0.2 10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 GND)) + (pad 10 thru_hole oval (at -2.34 10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 10 /GPIO0)) + (pad 11 thru_hole oval (at 0.2 12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 2 +3V3)) + (pad 12 thru_hole oval (at -2.34 12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 8 VDD)) + (pad 13 thru_hole oval (at 0.2 15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 11 /I2C_SDA)) + (pad 14 thru_hole oval (at -2.34 15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 6 /UART_TX)) + (pad 15 thru_hole oval (at 0.2 17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 12 /I2C_SCL)) + (pad 16 thru_hole oval (at -2.34 17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 7 /UART_RX)) + (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x08_P2.54mm_Vertical.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm (layer F.Cu) (tedit 5A6E12B5) (tstamp 614E3FF2) + (at 134.7 113.4 90) + (descr "8-Lead Plastic WSON, 2x2mm Body, 0.5mm Pitch, WSON-8, http://www.ti.com/lit/ds/symlink/lm27761.pdf") + (tags "WSON 8 1EP") + (path /614E50D1) + (attr smd) + (fp_text reference U1 (at -2.7 0.85 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value PCA9536DP (at -2.2 3.2 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.5 -1.62) (end 1 -1.62) (layer F.SilkS) (width 0.12)) + (fp_line (start 1 1.62) (end -1 1.62) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.95 1.75) (end 1.95 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.95 -1.75) (end 1.95 -1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.95 -1.75) (end 1.95 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.95 -1.75) (end -1.95 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -1.5) (end 1.5 -1.5) (layer F.Fab) (width 0.1)) + (fp_line (start 1.5 -1.5) (end 1.5 1.5) (layer F.Fab) (width 0.1)) + (fp_line (start 1.5 1.5) (end -1.5 1.5) (layer F.Fab) (width 0.1)) + (fp_line (start -1.5 1.5) (end -1.5 -1) (layer F.Fab) (width 0.1)) + (fp_line (start -1 -1.5) (end -1.5 -1) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.7 0.7) (thickness 0.1))) + ) + (pad 3 smd rect (at -1.4 0.25 90) (size 0.6 0.25) (layers F.Cu F.Paste F.Mask) + (net 15 /PCA_IO2)) + (pad 7 smd rect (at 1.4 -0.25 90) (size 0.6 0.25) (layers F.Cu F.Paste F.Mask) + (net 11 /I2C_SDA)) + (pad 8 smd rect (at 1.4 -0.75 90) (size 0.6 0.25) (layers F.Cu F.Paste F.Mask) + (net 2 +3V3)) + (pad 9 smd rect (at 0 0 90) (size 1.6 2) (layers F.Cu F.Mask)) + (pad 1 smd rect (at -1.4 -0.75 90) (size 0.6 0.25) (layers F.Cu F.Paste F.Mask) + (net 13 /PCA_IO0)) + (pad 2 smd rect (at -1.4 -0.25 90) (size 0.6 0.25) (layers F.Cu F.Paste F.Mask) + (net 14 /PCA_IO1)) + (pad 4 smd rect (at -1.4 0.75 90) (size 0.6 0.25) (layers F.Cu F.Paste F.Mask) + (net 1 GND)) + (pad 5 smd rect (at 1.4 0.75 90) (size 0.6 0.25) (layers F.Cu F.Paste F.Mask) + (net 16 /PCA_IO3)) + (pad 6 smd rect (at 1.4 0.25 90) (size 0.6 0.25) (layers F.Cu F.Paste F.Mask) + (net 12 /I2C_SCL)) + (pad "" smd rect (at -0.45 -0.55 90) (size 0.6 0.8) (layers F.Paste)) + (pad "" smd rect (at 0.45 -0.55 90) (size 0.6 0.8) (layers F.Paste)) + (pad "" smd rect (at -0.45 0.55 90) (size 0.6 0.8) (layers F.Paste)) + (pad "" smd rect (at 0.45 0.55 90) (size 0.6 0.8) (layers F.Paste)) + (model ${KISYS3DMOD}/Package_SON.3dshapes/WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Connector_Molex:Molex_SlimStack_55560-0161_2x08_P0.50mm_Vertical (layer F.Cu) (tedit 60DA23A1) (tstamp 60DA7D5B) + (at 133.5 106.05 270) + (descr "Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0161, 16 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator") + (tags "connector Molex SlimStack side entry") + (path /60DA2442) + (attr smd) + (fp_text reference J1 (at 3.35 2.65 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value In (at 0 -4.4 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -3.22 -2.95) (end 3.22 -2.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.22 2.95) (end -3.22 -2.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.22 2.95) (end -3.22 2.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.22 -2.95) (end 3.22 2.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.835 -1.525) (end -2.16 -1.525) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.835 1.525) (end -2.835 -1.525) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.16 1.525) (end -2.835 1.525) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.16 -1.525) (end 2.16 -2.215) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.835 -1.525) (end 2.16 -1.525) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.835 1.525) (end 2.835 -1.525) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.16 1.525) (end 2.835 1.525) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.16 -1.525) (end 2.16 -2.215) (layer F.Fab) (width 0.1)) + (fp_line (start -2.725 -1.415) (end 2.725 -1.415) (layer F.Fab) (width 0.1)) + (fp_line (start -2.725 1.415) (end -2.725 -1.415) (layer F.Fab) (width 0.1)) + (fp_line (start 2.725 1.415) (end -2.725 1.415) (layer F.Fab) (width 0.1)) + (fp_line (start 2.725 -1.415) (end 2.725 1.415) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 smd rect (at 1.75 -1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 2 +3V3)) + (pad 3 smd rect (at 1.25 -1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 2 +3V3)) + (pad 5 smd rect (at 0.75 -1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 3 /SPI_MOSI)) + (pad 7 smd rect (at 0.25 -1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 4 /SPI_MISO)) + (pad 9 smd rect (at -0.25 -1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 5 /SPI_SCK)) + (pad 11 smd rect (at -0.75 -1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 1 GND)) + (pad 13 smd rect (at -1.25 -1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 6 /UART_TX)) + (pad 15 smd rect (at -1.75 -1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 7 /UART_RX)) + (pad 2 smd rect (at 1.75 1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 8 VDD)) + (pad 4 smd rect (at 1.25 1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 8 VDD)) + (pad 6 smd rect (at 0.75 1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 1 GND)) + (pad 8 smd rect (at 0.25 1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 9 /SPI_CS)) + (pad 10 smd rect (at -0.25 1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 10 /GPIO0)) + (pad 12 smd rect (at -0.75 1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 11 /I2C_SDA)) + (pad 14 smd rect (at -1.25 1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 12 /I2C_SCL)) + (pad 16 smd rect (at -1.75 1.95 270) (size 0.3 1) (layers F.Cu F.Paste F.Mask) + (net 1 GND)) + (model ${KISYS3DMOD}/Connector_Molex.3dshapes/Molex_SlimStack_55560-0161_2x08_P0.50mm_Vertical.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitor_SMD:C_0603_1608Metric (layer F.Cu) (tedit 5F68FEEE) (tstamp 614E403F) + (at 132.2 112.8 270) + (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags capacitor) + (path /614E5873) + (attr smd) + (fp_text reference C2 (at 2.45 0 270) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 0.1uF (at 5.4 -0.05 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.14058 0.51) (end 0.14058 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.14058 -0.51) (end 0.14058 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.06))) + ) + (pad 1 smd roundrect (at -0.775 0 270) (size 0.9 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 +3V3)) + (pad 2 smd roundrect (at 0.775 0 270) (size 0.9 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitor_SMD:C_0603_1608Metric (layer F.Cu) (tedit 5F68FEEE) (tstamp 614EE6A1) + (at 134.7 110.05 180) + (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags capacitor) + (path /61713CB1) + (attr smd) + (fp_text reference C1 (at 2.2 -0.05) (layer F.SilkS) + (effects (font (size 0.8 0.8) (thickness 0.15))) + ) + (fp_text value 10uF (at -4.3 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.14058 -0.51) (end 0.14058 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.14058 0.51) (end 0.14058 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.06))) + ) + (pad 1 smd roundrect (at -0.775 0 180) (size 0.9 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 +3V3)) + (pad 2 smd roundrect (at 0.775 0 180) (size 0.9 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (gr_text GPIO0 (at 130.6 112.1 90) (layer F.SilkS) + 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103.524121) (xy 127.347667 103.653279) (xy 127.183279 103.817667) (xy 127.054121 104.010966) + (xy 126.965155 104.225748) (xy 126.9198 104.45376) (xy 126.7402 104.45376) (xy 126.694845 104.225748) (xy 126.605879 104.010966) + (xy 126.476721 103.817667) (xy 126.312333 103.653279) (xy 126.119034 103.524121) (xy 125.904252 103.435155) (xy 125.67624 103.3898) + (xy 125.44376 103.3898) (xy 125.215748 103.435155) (xy 125.000966 103.524121) (xy 124.807667 103.653279) (xy 124.643279 103.817667) + (xy 124.514121 104.010966) (xy 124.425155 104.225748) (xy 124.3798 104.45376) (xy 99.8302 104.45376) (xy 99.8302 104.078376) + (xy 99.850446 103.871885) (xy 99.902176 103.70055) (xy 99.986195 103.542533) (xy 100.099313 103.403836) (xy 100.237209 103.289759) + (xy 100.394641 103.204636) (xy 100.565609 103.151712) (xy 100.77029 103.1302) (xy 135.321624 103.1302) + ) + ) + ) + (zone (net 8) (net_name VDD) (layer F.Cu) (tstamp 614F557F) (hatch edge 0.508) + (connect_pads yes (clearance 0.2032)) + (min_thickness 0.254) + (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 131.8 107.95) (xy 131.3 107.95) (xy 131.3 107.15) (xy 131.8 107.15) + ) + ) + (filled_polygon + (pts + (xy 131.673 107.823) (xy 131.427 107.823) (xy 131.427 107.281797) (xy 131.673 107.281797) + ) + ) + ) +) diff --git a/hw/breakout/breakout.net b/hw/breakout/breakout.net new file mode 100644 index 0000000..3d8bb41 --- /dev/null +++ b/hw/breakout/breakout.net @@ -0,0 +1,175 @@ +(export (version D) + (design + (source /Volumes/rvPhone/repo/hw/breakout/breakout.sch) + (date "Saturday, September 25, 2021 at 06:03:11 PM") + (tool "Eeschema (5.1.9-0-10_14)") + (sheet (number 1) (name /) (tstamps /) + (title_block + (title) + (company) + (rev) + (date) + (source breakout.sch) + (comment (number 1) (value "")) + (comment (number 2) (value "")) + (comment (number 3) (value "")) + (comment (number 4) (value ""))))) + (components + (comp (ref J1) + (value In) + (footprint Connector_Molex:Molex_SlimStack_55560-0161_2x08_P0.50mm_Vertical) + (datasheet ~) + (libsource (lib Connector_Generic) (part Conn_02x08_Odd_Even) (description "Generic connector, double row, 02x08, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)")) + (sheetpath (names /) (tstamps /)) + (tstamp 60DA2442)) + (comp (ref J2) + (value Out) + (footprint Connector_PinHeader_2.54mm:PinHeader_2x08_P2.54mm_Vertical) + (datasheet ~) + (libsource (lib Connector_Generic) (part Conn_02x08_Odd_Even) (description "Generic connector, double row, 02x08, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)")) + (sheetpath (names /) (tstamps /)) + (tstamp 60DA3522)) + (comp (ref U1) + (value PCA9536DP) + (footprint Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm) + (datasheet http://www.nxp.com/documents/data_sheet/PCA9536.pdf) + (libsource (lib Interface_Expansion) (part PCA9536DP) (description "4-bit I2C-bus and SMBus IO port, TSSOP-8")) + (sheetpath (names /) (tstamps /)) + (tstamp 614E50D1)) + (comp (ref C2) + (value 0.1uF) + (footprint Capacitor_SMD:C_0603_1608Metric) + (datasheet ~) + (libsource (lib Device) (part C) (description "Unpolarized capacitor")) + (sheetpath (names /) (tstamps /)) + (tstamp 614E5873)) + (comp (ref C1) + (value 10uF) + (footprint Capacitor_SMD:C_0603_1608Metric) + (datasheet ~) + (libsource (lib Device) (part C) (description "Unpolarized capacitor")) + (sheetpath (names /) (tstamps /)) + (tstamp 61713CB1))) + (libparts + (libpart (lib Connector_Generic) (part Conn_02x08_Odd_Even) + (description "Generic connector, double row, 02x08, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)") + (docs ~) + (footprints + (fp Connector*:*_2x??_*)) + (fields + (field (name Reference) J) + (field (name Value) Conn_02x08_Odd_Even)) + (pins + (pin (num 1) (name Pin_1) (type passive)) + (pin (num 2) (name Pin_2) (type passive)) + (pin (num 3) (name Pin_3) (type passive)) + (pin (num 4) (name Pin_4) (type passive)) + (pin (num 5) (name Pin_5) (type passive)) + (pin (num 6) (name Pin_6) (type passive)) + (pin (num 7) (name Pin_7) (type passive)) + (pin (num 8) (name Pin_8) (type passive)) + (pin (num 9) (name Pin_9) (type passive)) + (pin (num 10) (name Pin_10) (type passive)) + (pin (num 11) (name Pin_11) (type passive)) + (pin (num 12) (name Pin_12) (type passive)) + (pin (num 13) (name Pin_13) (type passive)) + (pin (num 14) (name Pin_14) (type passive)) + (pin (num 15) (name Pin_15) (type passive)) + (pin (num 16) (name Pin_16) (type passive)))) + (libpart (lib Device) (part C) + (description "Unpolarized capacitor") + (docs ~) + (footprints + (fp C_*)) + (fields + (field (name Reference) C) + (field (name Value) C)) + (pins + (pin (num 1) (name ~) (type passive)) + (pin (num 2) (name ~) (type passive)))) + (libpart (lib Interface_Expansion) (part PCA9536DP) + (description "4-bit I2C-bus and SMBus IO port, TSSOP-8") + (docs http://www.nxp.com/documents/data_sheet/PCA9536.pdf) + (footprints + (fp TSSOP*3x3mm*P0.65mm*)) + (fields + (field (name Reference) U) + (field (name Value) PCA9536DP) + (field (name Footprint) Package_SO:TSSOP-8_3x3mm_P0.65mm)) + (pins + (pin (num 1) (name IO0) (type BiDi)) + (pin (num 2) (name IO1) (type BiDi)) + (pin (num 3) (name IO2) (type BiDi)) + (pin (num 4) (name VSS) (type power_in)) + (pin (num 5) (name IO3) (type BiDi)) + (pin (num 6) (name SCL) (type input)) + (pin (num 7) (name SDA) (type BiDi)) + (pin (num 8) (name VDD) (type power_in))))) + (libraries + (library (logical Connector_Generic) + (uri "/Library/Application Support/kicad/library/Connector_Generic.lib")) + (library (logical Device) + (uri "/Library/Application Support/kicad/library/Device.lib")) + (library (logical Interface_Expansion) + (uri "/Library/Application Support/kicad/library/Interface_Expansion.lib"))) + (nets + (net (code 1) (name GND) + (node (ref U1) (pin 4)) + (node (ref J1) (pin 11)) + (node (ref J1) (pin 16)) + (node (ref C1) (pin 2)) + (node (ref J1) (pin 6)) + (node (ref C2) (pin 2)) + (node (ref J2) (pin 9))) + (net (code 2) (name VDD) + (node (ref J2) (pin 12)) + (node (ref J1) (pin 2)) + (node (ref J1) (pin 4))) + (net (code 3) (name /PCA_IO0) + (node (ref J2) (pin 8)) + (node (ref U1) (pin 1))) + (net (code 4) (name /PCA_IO1) + (node (ref J2) (pin 6)) + (node (ref U1) (pin 2))) + (net (code 5) (name /PCA_IO2) + (node (ref J2) (pin 4)) + (node (ref U1) (pin 3))) + (net (code 6) (name /PCA_IO3) + (node (ref J2) (pin 2)) + (node (ref U1) (pin 5))) + (net (code 7) (name +3V3) + (node (ref U1) (pin 8)) + (node (ref C2) (pin 1)) + (node (ref J1) (pin 1)) + (node (ref J1) (pin 3)) + (node (ref J2) (pin 11)) + (node (ref C1) (pin 1))) + (net (code 8) (name /I2C_SDA) + (node (ref U1) (pin 7)) + (node (ref J2) (pin 13)) + (node (ref J1) (pin 12))) + (net (code 9) (name /SPI_MOSI) + (node (ref J2) (pin 3)) + (node (ref J1) (pin 5))) + (net (code 10) (name /SPI_MISO) + (node (ref J1) (pin 7)) + (node (ref J2) (pin 5))) + (net (code 11) (name /SPI_SCK) + (node (ref J1) (pin 9)) + (node (ref J2) (pin 7))) + (net (code 12) (name /UART_TX) + (node (ref J1) (pin 13)) + (node (ref J2) (pin 14))) + (net (code 13) (name /UART_RX) + (node (ref J2) (pin 16)) + (node (ref J1) (pin 15))) + (net (code 14) (name /I2C_SCL) + (node (ref J2) (pin 15)) + (node (ref U1) (pin 6)) + (node (ref J1) (pin 14))) + (net (code 15) (name /GPIO0) + (node (ref J2) (pin 10)) + (node (ref J1) (pin 10))) + (net (code 16) (name /SPI_CS) + (node (ref J2) (pin 1)) + (node (ref J1) (pin 8)))))
\ No newline at end of file diff --git a/hw/breakout/breakout.pro b/hw/breakout/breakout.pro new file mode 100644 index 0000000..d68a4f1 --- /dev/null +++ b/hw/breakout/breakout.pro @@ -0,0 +1,248 @@ +update=Saturday, September 25, 2021 at 05:28:17 PM +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName=Pcbnew +SpiceAjustPassiveValues=0 +LabSize=50 +ERC_TestSimilarLabels=1 +[pcbnew] +version=1 +PageLayoutDescrFile= +LastNetListRead=breakout.net +CopperLayerCount=4 +BoardThickness=1.6 +AllowMicroVias=0 +AllowBlindVias=0 +RequireCourtyardDefinitions=0 +ProhibitOverlappingCourtyards=1 +MinTrackWidth=0.1524 +MinViaDiameter=0.4 +MinViaDrill=0.2 +MinMicroViaDiameter=0.2 +MinMicroViaDrill=0.09999999999999999 +MinHoleToHole=0.25 +TrackWidth1=0.2 +ViaDiameter1=0.6 +ViaDrill1=0.3 +dPairWidth1=0.2 +dPairGap1=0.25 +dPairViaGap1=0.25 +SilkLineWidth=0.12 +SilkTextSizeV=1 +SilkTextSizeH=1 +SilkTextSizeThickness=0.15 +SilkTextItalic=0 +SilkTextUpright=1 +CopperLineWidth=0.2 +CopperTextSizeV=1.5 +CopperTextSizeH=1.5 +CopperTextThickness=0.3 +CopperTextItalic=0 +CopperTextUpright=1 +EdgeCutLineWidth=0.05 +CourtyardLineWidth=0.05 +OthersLineWidth=0.15 +OthersTextSizeV=1 +OthersTextSizeH=1 +OthersTextSizeThickness=0.15 +OthersTextItalic=0 +OthersTextUpright=1 +SolderMaskClearance=0 +SolderMaskMinWidth=0 +SolderPasteClearance=0 +SolderPasteRatio=-0 +[pcbnew/Layer.F.Cu] +Name=F.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.In1.Cu] +Name=GND +Type=1 +Enabled=1 +[pcbnew/Layer.In2.Cu] +Name=PWR +Type=1 +Enabled=1 +[pcbnew/Layer.In3.Cu] +Name=In3.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In4.Cu] +Name=In4.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In5.Cu] +Name=In5.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In6.Cu] +Name=In6.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In7.Cu] +Name=In7.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In8.Cu] +Name=In8.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In9.Cu] +Name=In9.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In10.Cu] +Name=In10.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In11.Cu] +Name=In11.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In12.Cu] +Name=In12.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In13.Cu] +Name=In13.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In14.Cu] +Name=In14.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In15.Cu] +Name=In15.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In16.Cu] +Name=In16.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In17.Cu] +Name=In17.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In18.Cu] +Name=In18.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In19.Cu] +Name=In19.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In20.Cu] +Name=In20.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In21.Cu] +Name=In21.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In22.Cu] +Name=In22.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In23.Cu] +Name=In23.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In24.Cu] +Name=In24.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In25.Cu] +Name=In25.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In26.Cu] +Name=In26.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In27.Cu] +Name=In27.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In28.Cu] +Name=In28.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In29.Cu] +Name=In29.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In30.Cu] +Name=In30.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.B.Cu] +Name=B.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.B.Adhes] +Enabled=1 +[pcbnew/Layer.F.Adhes] +Enabled=1 +[pcbnew/Layer.B.Paste] +Enabled=1 +[pcbnew/Layer.F.Paste] +Enabled=1 +[pcbnew/Layer.B.SilkS] +Enabled=1 +[pcbnew/Layer.F.SilkS] +Enabled=1 +[pcbnew/Layer.B.Mask] +Enabled=1 +[pcbnew/Layer.F.Mask] +Enabled=1 +[pcbnew/Layer.Dwgs.User] +Enabled=1 +[pcbnew/Layer.Cmts.User] +Enabled=1 +[pcbnew/Layer.Eco1.User] +Enabled=1 +[pcbnew/Layer.Eco2.User] +Enabled=1 +[pcbnew/Layer.Edge.Cuts] +Enabled=1 +[pcbnew/Layer.Margin] +Enabled=1 +[pcbnew/Layer.B.CrtYd] +Enabled=1 +[pcbnew/Layer.F.CrtYd] +Enabled=1 +[pcbnew/Layer.B.Fab] +Enabled=1 +[pcbnew/Layer.F.Fab] +Enabled=1 +[pcbnew/Layer.Rescue] +Enabled=0 +[pcbnew/Netclasses] +[pcbnew/Netclasses/Default] +Name=Default +Clearance=0.2 +TrackWidth=0.2 +ViaDiameter=0.6 +ViaDrill=0.3 +uViaDiameter=0.3 +uViaDrill=0.1 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 diff --git a/hw/breakout/breakout.sch b/hw/breakout/breakout.sch new file mode 100644 index 0000000..2df0f0e --- /dev/null +++ b/hw/breakout/breakout.sch @@ -0,0 +1,414 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Connector_Generic:Conn_02x08_Odd_Even J1 +U 1 1 60DA2442 +P 1850 1650 +F 0 "J1" H 1850 2050 50 0000 C CNN +F 1 "In" H 1850 1150 50 0000 C CNN +F 2 "Connector_Molex:Molex_SlimStack_55560-0161_2x08_P0.50mm_Vertical" H 1850 1650 50 0001 C CNN +F 3 "~" H 1850 1650 50 0001 C CNN + 1 1850 1650 + 1 0 0 -1 +$EndComp +$Comp +L Connector_Generic:Conn_02x08_Odd_Even J2 +U 1 1 60DA3522 +P 7000 1650 +F 0 "J2" H 7000 2050 50 0000 C CNN +F 1 "Out" H 7000 1150 50 0000 C CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_2x08_P2.54mm_Vertical" H 7000 1650 50 0001 C CNN +F 3 "~" H 7000 1650 50 0001 C CNN + 1 7000 1650 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR0101 +U 1 1 60DA9CCD +P 1550 2150 +F 0 "#PWR0101" H 1550 1900 50 0001 C CNN +F 1 "GND" H 1555 1977 50 0000 C CNN +F 2 "" H 1550 2150 50 0001 C CNN +F 3 "" H 1550 2150 50 0001 C CNN + 1 1550 2150 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG0101 +U 1 1 60DB0F71 +P 2550 2150 +F 0 "#FLG0101" H 2550 2225 50 0001 C CNN +F 1 "PWR_FLAG" H 2550 2323 50 0000 C CNN +F 2 "" H 2550 2150 50 0001 C CNN +F 3 "~" H 2550 2150 50 0001 C CNN + 1 2550 2150 + -1 0 0 1 +$EndComp +$Comp +L Interface_Expansion:PCA9536DP U1 +U 1 1 614E50D1 +P 5050 1800 +F 0 "U1" H 4700 2050 50 0000 C CNN +F 1 "PCA9536DP" H 4750 1450 50 0000 C CNN +F 2 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