From 5ae72474e3116df141c5700902e54e516b68e6e0 Mon Sep 17 00:00:00 2001 From: Uros Majstorovic Date: Fri, 1 Oct 2021 04:16:49 +0200 Subject: HW REV 3.0 --- hw/panel/panel_empty.pro | 260 ----------------------------------------------- 1 file changed, 260 deletions(-) delete mode 100644 hw/panel/panel_empty.pro (limited to 'hw/panel/panel_empty.pro') diff --git a/hw/panel/panel_empty.pro b/hw/panel/panel_empty.pro deleted file mode 100644 index 43e8e35..0000000 --- a/hw/panel/panel_empty.pro +++ /dev/null @@ -1,260 +0,0 @@ -update=Wednesday, January 27, 2021 at 02:12:42 PM -version=1 -last_client=pcbnew -[general] -version=1 -RootSch= -BoardNm= -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -[pcbnew] -version=1 -PageLayoutDescrFile= -LastNetListRead= -CopperLayerCount=4 -BoardThickness=1.6 -AllowMicroVias=0 -AllowBlindVias=0 -RequireCourtyardDefinitions=0 -ProhibitOverlappingCourtyards=1 -MinTrackWidth=0.1524 -MinViaDiameter=0.5 -MinViaDrill=0.2 -MinMicroViaDiameter=0.2 -MinMicroViaDrill=0.09999999999999999 -MinHoleToHole=0.25 -TrackWidth1=0.2 -ViaDiameter1=0.6 -ViaDrill1=0.3 -dPairWidth1=0.2 -dPairGap1=0.25 -dPairViaGap1=0.25 -SilkLineWidth=0.05 -SilkTextSizeV=0.6 -SilkTextSizeH=0.6 -SilkTextSizeThickness=0.125 -SilkTextItalic=0 -SilkTextUpright=1 -CopperLineWidth=0.2 -CopperTextSizeV=0.5 -CopperTextSizeH=0.5 -CopperTextThickness=0.125 -CopperTextItalic=0 -CopperTextUpright=1 -EdgeCutLineWidth=0.15 -CourtyardLineWidth=0.05 -OthersLineWidth=0.15 -OthersTextSizeV=1 -OthersTextSizeH=1 -OthersTextSizeThickness=0.15 -OthersTextItalic=0 -OthersTextUpright=1 -SolderMaskClearance=0.045 -SolderMaskMinWidth=0.11 -SolderPasteClearance=0 -SolderPasteRatio=-0 -[pcbnew/Layer.F.Cu] -Name=F.Cu -Type=0 -Enabled=1 -[pcbnew/Layer.In1.Cu] -Name=GND -Type=1 -Enabled=1 -[pcbnew/Layer.In2.Cu] -Name=PWR -Type=1 -Enabled=1 -[pcbnew/Layer.In3.Cu] -Name=In3.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In4.Cu] -Name=In4.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In5.Cu] -Name=In5.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In6.Cu] -Name=In6.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In7.Cu] -Name=In7.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In8.Cu] -Name=In8.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In9.Cu] -Name=In9.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In10.Cu] -Name=In10.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In11.Cu] -Name=In11.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In12.Cu] -Name=In12.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In13.Cu] -Name=In13.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In14.Cu] -Name=In14.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In15.Cu] -Name=In15.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In16.Cu] -Name=In16.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In17.Cu] -Name=In17.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In18.Cu] -Name=In18.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In19.Cu] -Name=In19.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In20.Cu] -Name=In20.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In21.Cu] -Name=In21.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In22.Cu] -Name=In22.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In23.Cu] -Name=In23.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In24.Cu] -Name=In24.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In25.Cu] -Name=In25.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In26.Cu] -Name=In26.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In27.Cu] -Name=In27.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In28.Cu] -Name=In28.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In29.Cu] -Name=In29.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.In30.Cu] -Name=In30.Cu -Type=0 -Enabled=0 -[pcbnew/Layer.B.Cu] -Name=B.Cu -Type=0 -Enabled=1 -[pcbnew/Layer.B.Adhes] -Enabled=1 -[pcbnew/Layer.F.Adhes] -Enabled=1 -[pcbnew/Layer.B.Paste] -Enabled=1 -[pcbnew/Layer.F.Paste] -Enabled=1 -[pcbnew/Layer.B.SilkS] -Enabled=1 -[pcbnew/Layer.F.SilkS] -Enabled=1 -[pcbnew/Layer.B.Mask] -Enabled=1 -[pcbnew/Layer.F.Mask] -Enabled=1 -[pcbnew/Layer.Dwgs.User] -Enabled=1 -[pcbnew/Layer.Cmts.User] -Enabled=1 -[pcbnew/Layer.Eco1.User] -Enabled=1 -[pcbnew/Layer.Eco2.User] -Enabled=1 -[pcbnew/Layer.Edge.Cuts] -Enabled=1 -[pcbnew/Layer.Margin] -Enabled=1 -[pcbnew/Layer.B.CrtYd] -Enabled=1 -[pcbnew/Layer.F.CrtYd] -Enabled=1 -[pcbnew/Layer.B.Fab] -Enabled=1 -[pcbnew/Layer.F.Fab] -Enabled=1 -[pcbnew/Layer.Rescue] -Enabled=0 -[pcbnew/Netclasses] -[pcbnew/Netclasses/Default] -Name=Default -Clearance=0.2 -TrackWidth=0.2 -ViaDiameter=0.6 -ViaDrill=0.3 -uViaDiameter=0.3 -uViaDrill=0.1 -dPairWidth=0.2 -dPairGap=0.25 -dPairViaGap=0.25 -[pcbnew/Netclasses/1] -Name=DISPLAY -Clearance=0.1524 -TrackWidth=0.1524 -ViaDiameter=0.508 -ViaDrill=0.254 -uViaDiameter=0.3 -uViaDrill=0.1 -dPairWidth=0.175 -dPairGap=0.1524 -dPairViaGap=0.25 -[pcbnew/Netclasses/2] -Name=POWER -Clearance=0.2 -TrackWidth=0.25 -ViaDiameter=0.6 -ViaDrill=0.3 -uViaDiameter=0.3 -uViaDrill=0.1 -dPairWidth=0.2 -dPairGap=0.25 -dPairViaGap=0.25 -- cgit v1.2.3