#define SPI_DIV_NET             16
#define SPI_DIV_EVE             4
#define SPI_DIV_SDC             1024
#define SPI_DIV_CAM             24

#define SPI_CSID_NET            0
#define SPI_CSID_EVE            3
#define SPI_CSID_SDC            -1
#define SPI_CSID_CAM            2

#define SPI_CSPIN_NET           -1
#define SPI_CSPIN_EVE           -1
#define SPI_CSPIN_SDC           0
#define SPI_CSPIN_CAM           -1

#define SPI_CSPIN_LCD           21

// SS2 used as I2S_PIN_INT
// #define SPI_IOF_MASK            ((1 << IOF_SPI1_SCK) | (1 << IOF_SPI1_MOSI) | (1 << IOF_SPI1_MISO) | (1 << IOF_SPI1_SS0) | (1 << IOF_SPI1_SS2) | (1 << IOF_SPI1_SS3))
#define SPI_IOF_MASK            ((1 << IOF_SPI1_SCK) | (1 << IOF_SPI1_MOSI) | (1 << IOF_SPI1_MISO) | (1 << IOF_SPI1_SS0) | (1 << IOF_SPI1_SS3))

#define NET_PIN_RTS             20
#define NET_PIN_CTS             22

#define EVE_PIN_INTR            1

#define I2S_PIN_CK              1       /* PWM 0.1 */
#define I2S_PIN_SR_CK           18
#define I2S_PIN_SR_SEL          11      /* PWM 2.1 */
#define I2S_PIN_WS_MIC          19      /* PWM 1.1 */
#define I2S_PIN_WS_SPK          21      /* PWM 1.2 */
#define I2S_PIN_SD_IN           17
#define I2S_PIN_SD_OUT          16
#define I2S_PIN_INT             9

#define CTP_PIN_INT             23
#define CTP_PIN_RST             19