diff options
| author | Uros Majstorovic <majstor@majstor.org> | 2020-08-05 02:52:42 +0200 |
|---|---|---|
| committer | Uros Majstorovic <majstor@majstor.org> | 2020-08-05 02:52:42 +0200 |
| commit | 0894a1e7664504312a9cdfc826eef89030aaaa1b (patch) | |
| tree | 51e37e46d7862437583dbe02e6ebf03997a664be /code/fe310/bsp/include/sifive/devices/uart.h | |
| parent | dff71bc297b744856e303ad9a175de92c9acae0d (diff) | |
new directory sructure for fe310 fw
Diffstat (limited to 'code/fe310/bsp/include/sifive/devices/uart.h')
| -rw-r--r-- | code/fe310/bsp/include/sifive/devices/uart.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/code/fe310/bsp/include/sifive/devices/uart.h b/code/fe310/bsp/include/sifive/devices/uart.h new file mode 100644 index 0000000..71bea6f --- /dev/null +++ b/code/fe310/bsp/include/sifive/devices/uart.h @@ -0,0 +1,27 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_UART_H +#define _SIFIVE_UART_H + +/* Register offsets */ +#define UART_REG_TXFIFO 0x00 +#define UART_REG_RXFIFO 0x04 +#define UART_REG_TXCTRL 0x08 +#define UART_REG_RXCTRL 0x0c +#define UART_REG_IE 0x10 +#define UART_REG_IP 0x14 +#define UART_REG_DIV 0x18 + +/* TXCTRL register */ +#define UART_TXEN 0x1 +#define UART_TXWM(x) (((x) & 0xffff) << 16) + +/* RXCTRL register */ +#define UART_RXEN 0x1 +#define UART_RXWM(x) (((x) & 0xffff) << 16) + +/* IP register */ +#define UART_IP_TXWM 0x1 +#define UART_IP_RXWM 0x2 + +#endif /* _SIFIVE_UART_H */ |