diff options
author | Uros Majstorovic <majstor@majstor.org> | 2019-12-04 06:11:35 +0100 |
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committer | Uros Majstorovic <majstor@majstor.org> | 2019-12-04 06:11:35 +0100 |
commit | 31578e285a21a749a49e3ac146feb8b02fcc7b52 (patch) | |
tree | e67f619360352a87fb6e0f410f5246468fbc1073 /code/fe310/include/sifive/devices/uart.h | |
parent | 2c981aec5e5c10f9fd036dfb48105b16f16e4233 (diff) |
added new metal sdk
Diffstat (limited to 'code/fe310/include/sifive/devices/uart.h')
-rw-r--r-- | code/fe310/include/sifive/devices/uart.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/code/fe310/include/sifive/devices/uart.h b/code/fe310/include/sifive/devices/uart.h new file mode 100644 index 0000000..71bea6f --- /dev/null +++ b/code/fe310/include/sifive/devices/uart.h @@ -0,0 +1,27 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_UART_H +#define _SIFIVE_UART_H + +/* Register offsets */ +#define UART_REG_TXFIFO 0x00 +#define UART_REG_RXFIFO 0x04 +#define UART_REG_TXCTRL 0x08 +#define UART_REG_RXCTRL 0x0c +#define UART_REG_IE 0x10 +#define UART_REG_IP 0x14 +#define UART_REG_DIV 0x18 + +/* TXCTRL register */ +#define UART_TXEN 0x1 +#define UART_TXWM(x) (((x) & 0xffff) << 16) + +/* RXCTRL register */ +#define UART_RXEN 0x1 +#define UART_RXWM(x) (((x) & 0xffff) << 16) + +/* IP register */ +#define UART_IP_TXWM 0x1 +#define UART_IP_RXWM 0x2 + +#endif /* _SIFIVE_UART_H */ |