removed EOS_WITH_SPI_ASM from asm trap_entry

2 files changed, 1 insertions, 394 deletions

diff --git a/code/fe310/eos/Makefile b/code/fe310/eos/Makefile
index f097327..a3fb640 100644
--- a/code/fe310/eos/Makefile
+++ b/code/fe310/eos/Makefile
@@ -5,7 +5,7 @@ FE310_HOME = /opt/my/freedom-e-sdk
 CC = $(FE310_HOME)/work/build/riscv-gnu-toolchain/riscv64-unknown-elf/prefix/bin/riscv64-unknown-elf-gcc
 AR = $(FE310_HOME)/work/build/riscv-gnu-toolchain/riscv64-unknown-elf/prefix/bin/riscv64-unknown-elf-ar
 
-CFLAGS = $(CFLAGS_PL) -I../.. # -DEOS_WITH_SPI_ASM
+CFLAGS = $(CFLAGS_PL) -I../..
  
 obj = trap_entry.o eos.o msgq.o event.o interrupt.o timer.o i2s.o net.o ecp.o
 
diff --git a/code/fe310/eos/trap_entry.S b/code/fe310/eos/trap_entry.S
index 1908327..26e93cb 100644
--- a/code/fe310/eos/trap_entry.S
+++ b/code/fe310/eos/trap_entry.S
@@ -69,14 +69,6 @@ eos_trap_entry:
   beq x9, x18, i2s_handler_ws
   li x18, I2S_IRQ_SD_ID
   beq x9, x18, i2s_handler_sd
-#ifdef EOS_WITH_SPI_ASM
-  li x18, INT_SPI1_BASE
-  beq x9, x18, spi_handler_xchg
-  li x18, INT_GPIO_BASE + SPI_PIN_CTS
-  beq x9, x18, spi_handler_cts
-  li x18, INT_GPIO_BASE + SPI_PIN_RTS
-  beq x9, x18, spi_handler_rts
-#endif
   j handler
 
 evtq_push:
@@ -374,391 +366,6 @@ eos_flash_set:
   sw a0, SPI_REG_FCTRL(a3)
   ret
 
-#ifdef EOS_WITH_SPI_ASM
-
-# x9 - cmd, x18 - buffer, x19 - len, x20 - &flags, x21 - flags
-spi_xchg_start:
-  ori x21, x21, SPI_FLAG_INIT
-  andi x21, x21, ~SPI_FLAG_CTS
-  la x22, _eos_spi_state_next_cnt
-  lbu x23, 0(x22)
-  beqz x23, 1f
-  la x22, _eos_spi_state_next_buf
-  lw x23, 0(x22)
-  bnez x23, 1f
-  ori x9, x9, EOS_NET_CMD_FLAG_ONEW
-
-1:
-  andi x22, x9, EOS_NET_CMD_FLAG_ONEW
-  beqz x22, 2f
-  ori x21, x21, SPI_FLAG_ONEW
-2:
-  sw x21, 0(x20)
-
-  la x20, _eos_spi_state_cmd
-  sb x9, 0(x20)
-  la x20, _eos_spi_state_buf
-  sw x18, 0(x20)
-  la x20, _eos_spi_state_len_tx
-  sw x19, 0(x20)
-  la x20, _eos_spi_state_len_rx
-  sw x0, 0(x20)
-  la x20, _eos_spi_state_idx_tx
-  sw x0, 0(x20)
-  la x20, _eos_spi_state_idx_rx
-  sw x0, 0(x20)
-
-  li x20, SPI1_CTRL_ADDR
-  li x21, SPI_CSMODE_HOLD
-  sw x21, SPI_REG_CSMODE(x20)
-
-  slli x21, x9, 3
-  srli x22, x19, 8
-  or x21, x21, x22
-  andi x21, x21, 0xff
-  sw x21, SPI_REG_TXFIFO(x20)
-
-  andi x21, x19, 0xff
-  sw x21, SPI_REG_TXFIFO(x20)
-
-  li x21, 1
-  sw x21, SPI_REG_RXCTRL(x20)
-  li x21, SPI_IP_RXWM
-  sw x21, SPI_REG_IE(x20)
-  jalr x0, x8
-
-spi_handler_xchg:
-  li x19, SPI1_CTRL_ADDR
-  la x18, _eos_spi_state_flags
-  lbu x20, 0(x18)
-  andi x8, x20, SPI_FLAG_RST
-  beqz x8, 0f
-
-  andi x20, x20, ~SPI_FLAG_RST
-  sb x20, 0(x18)
-  lw x0, SPI_REG_RXFIFO(x19)
-  li x8, SPI_CSMODE_AUTO
-  sw x8, SPI_REG_CSMODE(x19)
-  sw x0, SPI_REG_IE(x19)
-  j spi_handler_xchg_exit
-
-0:
-  andi x8, x20, SPI_FLAG_INIT
-  beqz x8, 6f
-
-  andi x20, x20, ~SPI_FLAG_INIT
-  sb x20, 0(x18)
-  li x8, SPI_SIZE_WM
-  sw x8, SPI_REG_TXCTRL(x19)
-  li x8, SPI_IP_TXWM
-  sw x8, SPI_REG_IE(x19)
-  lw x8, SPI_REG_RXFIFO(x19)
-  lw x9, SPI_REG_RXFIFO(x19)
-  andi x8, x8, 0xff
-  andi x9, x9, 0xff
-  la x18, _eos_spi_state_cmd
-  lbu x23, 0(x18)
-  andi x23, x23, EOS_NET_CMD_FLAG_ONEW
-  beqz x23, 1f
-  mv x8, x0
-  mv x9, x0
-1:
-  srli x23, x8, 3
-  sb x23, 0(x18)
-  andi x22, x8, 0x07
-  slli x22, x22, 8
-  or x22, x22, x9
-  la x18, _eos_spi_state_len_rx
-  sw x22, 0(x18)
-  la x18, _eos_spi_state_len_tx
-  lw x21, 0(x18)
-  bgeu x21, x22, 2f
-  mv x21, x22
-
-2:
-  li x8, 6
-  bgeu x21, x8, 3f
-  mv x21, x8
-  j 4f
-3:
-  addi x8, x21, 2
-  li x9, 4
-  remu x18, x8, x9
-  beqz x18, 4f
-  divu x21, x8, x9
-  addi x21, x21, 1
-  mul x21, x21, x9
-  addi x21, x21, -2
-
-4:
-  li x8, SPI_SIZE_BUF + 1
-  bltu x21, x8, 5f
-  li x8, SPI_CSMODE_AUTO
-  sw x8, SPI_REG_CSMODE(x19)
-  sw x0, SPI_REG_IE(x19)
-
-  j spi_handler_xchg_exit
-
-5:
-  la x18, _eos_spi_state_len
-  sw x21, 0(x18)
-  j spi_handler_xchg_exit
-
-6:
-  la x18, _eos_spi_state_len
-  lw x20, 0(x18)
-  la x18, _eos_spi_state_idx_tx
-  lw x21, 0(x18)
-  la x18, _eos_spi_state_idx_rx
-  lw x22, 0(x18)
-  la x18, _eos_spi_state_buf
-  lw x23, 0(x18)
-
-  sub x9, x20, x21
-  li x8, SPI_SIZE_CHUNK
-  bltu x8, x9, 7f
-  mv x8, x9
-7:
-  addi x8, x8, -1
-  add x9, x23, x21
-
-8:
-  bltz x8, 9f
-  lw x18, SPI_REG_TXFIFO(x19)
-  bltz x18, 9f
-  lbu x18, 0(x9)
-  sw x18, SPI_REG_TXFIFO(x19)
-  addi x8, x8, -1
-  addi x9, x9, 1
-  addi x21, x21, 1
-  j 8b
-
-9:
-  sub x8, x21, x22
-  addi x8, x8, -1
-  add x9, x23, x22
-
-10:
-  bltz x8, 11f
-  lw x18, SPI_REG_RXFIFO(x19)
-  bltz x18, 11f
-  sb x18, 0(x9)
-  addi x8, x8, -1
-  addi x9, x9, 1
-  addi x22, x22, 1
-  j 10b
-
-11:
-  la x18, _eos_spi_state_idx_tx
-  sw x21, 0(x18)
-  la x18, _eos_spi_state_idx_rx
-  sw x22, 0(x18)
-
-  bne x22, x20, 15f
-  li x8, SPI_CSMODE_AUTO
-  sw x8, SPI_REG_CSMODE(x19)
-  sw x0, SPI_REG_IE(x19)
-  la x18, _eos_spi_state_cmd
-  lbu x21, 0(x18)
-  beqz x21, 12f
-
-  # push to event queue
-  jal x20, evtq_push
-  beqz x8, 14f
-  ori x21, x21, EOS_EVT_NET
-  sb x21, MSGQ_ITEM_OFF_CMD(x8)
-  sw x23, MSGQ_ITEM_OFF_BUF(x8)
-  la x18, _eos_spi_state_len_rx
-  lw x22, 0(x18)
-  sh x22, MSGQ_ITEM_OFF_SIZE(x8)
-  j spi_handler_xchg_exit
-
-12:
-  la x18, _eos_spi_state_flags
-  lbu x8, 0(x18)
-  andi x19, x8, SPI_FLAG_ONEW
-  bnez x19, 13f
-  la x19, _eos_spi_state_next_cnt
-  lbu x9, 0(x19)
-  beqz x9, 14f
-13:
-  la x19, _eos_spi_state_next_buf
-  lw x9, 0(x19)
-  bnez x9, 14f
-  andi x8, x8, ~SPI_FLAG_ONEW
-  sb x8, 0(x18)
-  sw x23, 0(x19)
-
-  j spi_handler_xchg_exit
-
-14:
-  # push to spi buf queue
-  la x19, _eos_spi_buf_q
-  lbu x8, SPI_BUFQ_OFF_IDXW(x19)
-
-  andi x9, x8, SPI_SIZE_BUFQ - 1
-  slli x9, x9, 2
-  add x9, x19, x9
-  sw x23, SPI_BUFQ_OFF_ARRAY(x9)
-
-  addi x8, x8, 1
-  sb x8, SPI_BUFQ_OFF_IDXW(x19)
-
-  j spi_handler_xchg_exit
-
-15:
-  bne x21, x20, spi_handler_xchg_exit
-  sub x8, x20, x22
-  addi x8, x8, -1
-  li x9, SPI_SIZE_WM - 1
-  bltu x8, x9, 16f
-  mv x8, x9
-16:
-  sw x8, SPI_REG_RXCTRL(x19)
-  li x9, SPI_IP_RXWM
-  sw x9, SPI_REG_IE(x19)
-
-spi_handler_xchg_exit:
-  # complete
-  li x18, INT_SPI1_BASE
-  li x19, PLIC_CLAIM
-  sw x18, 0(x19)
-
-  # exit
-  j trap_exit_data
-
-spi_handler_cts:
-  li x8, 1
-  slli x8, x8, SPI_PIN_CTS
-  li x19, GPIO_CTRL_ADDR
-  sw x8, GPIO_RISE_IP(x19)
-
-  la x20, _eos_spi_state_flags
-  lbu x21, 0(x20)
-  ori x21, x21, SPI_FLAG_CTS
-  sb x21, 0(x20)
-  andi x9, x21, SPI_FLAG_RDY
-  beqz x9, 2f
-
-  # pop from send q
-  la x9, _eos_spi_send_q
-  lbu x18, MSGQ_OFF_IDXR(x9)
-  lbu x19, MSGQ_OFF_IDXW(x9)
-  beq x18, x19, 1f
-  lbu x8, MSGQ_OFF_SIZE(x9)
-
-  addi x8, x8, -1
-  and x8, x8, x18
-  li x19, MSGQ_ITEM_SIZE
-  mul x8, x8, x19
-  lw x19, MSGQ_OFF_ARRAY(x9)
-  add x8, x19, x8
-  addi x18, x18, 1
-  sb x18, MSGQ_OFF_IDXR(x9)
-
-  lbu x9, MSGQ_ITEM_OFF_CMD(x8)
-  lw x18, MSGQ_ITEM_OFF_BUF(x8)
-  lhu x19, MSGQ_ITEM_OFF_SIZE(x8)
-  beqz x18, 1f
-  jal x8, spi_xchg_start
-
-  j spi_handler_cts_exit
-
-1:
-  andi x9, x21, SPI_FLAG_RTS
-  beqz x9, spi_handler_cts_exit
-
-  # pop from spi buf queue
-  la x9, _eos_spi_buf_q
-  lbu x18, SPI_BUFQ_OFF_IDXR(x9)
-  lbu x19, SPI_BUFQ_OFF_IDXW(x9)
-  beq x18, x19, spi_handler_cts_exit
-
-  andi x8, x18, SPI_SIZE_BUFQ - 1
-  slli x8, x8, 2
-  add x8, x9, x8
-  addi x18, x18, 1
-  sb x18, SPI_BUFQ_OFF_IDXR(x9)
-  mv x9, x0
-  lw x18, SPI_BUFQ_OFF_ARRAY(x8)
-  mv x19, x0
-  beqz x18, spi_handler_cts_exit
-  jal x8, spi_xchg_start
-
-  j spi_handler_cts_exit
-
-2:
-  lw x8, GPIO_IOF_EN(x19)
-  li x9, 1
-  slli x9, x9, SPI_PIN_CS
-  not x9, x9
-  and x8, x8, x9
-  sw x8, GPIO_IOF_EN(x19)
-
-spi_handler_cts_exit:
-  # complete
-  li x18, INT_GPIO_BASE + SPI_PIN_CTS
-  li x19, PLIC_CLAIM
-  sw x18, 0(x19)
-
-  # exit
-  j trap_exit_data
-
-spi_handler_rts:
-  li x8, 1
-  slli x8, x8, SPI_PIN_RTS
-  li x18, GPIO_CTRL_ADDR
-  la x19, _eos_spi_state_flags
-
-  lw x9, GPIO_RISE_IP(x18)
-  and x9, x9, x8
-  beqz x9, 1f
-
-  sw x8, GPIO_RISE_IP(x18)
-  lbu x8, 0(x19)
-  ori x8, x8, SPI_FLAG_RTS
-  sb x8, 0(x19)
-
-  andi x9, x8, SPI_FLAG_RDY
-  beqz x9, spi_handler_rts_exit
-  andi x9, x8, SPI_FLAG_CTS
-  beqz x9, spi_handler_rts_exit
-
-  andi x8, x8, ~SPI_FLAG_CTS
-  ori x8, x8, SPI_FLAG_RST
-  sb x8, 0(x19)
-
-  li x19, SPI1_CTRL_ADDR
-  li x8, SPI_CSMODE_HOLD
-  sw x8, SPI_REG_CSMODE(x19)
-  sw x0, SPI_REG_TXFIFO(x19)
-  sw x0, SPI_REG_RXCTRL(x19)
-  li x8, SPI_IP_RXWM
-  sw x8, SPI_REG_IE(x19)
-
-  j spi_handler_rts_exit
-
-1:
-  lw x9, GPIO_FALL_IP(x18)
-  and x9, x9, x8
-  beqz x9, spi_handler_rts_exit
-
-  sw x8, GPIO_FALL_IP(x18)
-  lbu x8, 0(x19)
-  andi x8, x8, ~SPI_FLAG_RTS
-  sb x8, 0(x19)
-
-spi_handler_rts_exit:
-  # complete
-  li x18, INT_GPIO_BASE + SPI_PIN_RTS
-  li x19, PLIC_CLAIM
-  sw x18, 0(x19)
-
-  # exit
-  j trap_exit_data
-
-#endif  /* EOS_WITH_SPI_ASM */
-
 trap_exit_data:
   # Remain in M-mode after mret
   li x18, MSTATUS_MPP