fixed irq handlers for ci/sd

4 files changed, 45 insertions, 14 deletions

diff --git a/code/fe310/eos/i2s.c b/code/fe310/eos/i2s.c
index 64152dd..3b1772c 100644
--- a/code/fe310/eos/i2s.c
+++ b/code/fe310/eos/i2s.c
@@ -112,13 +112,13 @@ void eos_i2s_init(void) {
     I2S_PWM_REG_CK(PWM_COUNT)   = 0;
     I2S_PWM_REG_CK(PWM_CMP0)    = _eos_i2s_ck_period - 1;
     I2S_PWM_REG_CK(PWM_CMP1)    = I2S_PWM_REG_CK(PWM_CMP0) / 2;
-    I2S_PWM_REG_CK(PWM_CMP2)    = I2S_PWM_REG_CK(PWM_CMP0) / 2;
+    I2S_PWM_REG_CK(PWM_CMP2)    = I2S_PWM_REG_CK(PWM_CMP0) / 8;
 
     I2S_PWM_REG_WS(PWM_CFG)     = 0;
     I2S_PWM_REG_WS(PWM_COUNT)   = 0;
     I2S_PWM_REG_WS(PWM_CMP0)    = _eos_i2s_ck_period * 64 - 1;
     I2S_PWM_REG_WS(PWM_CMP1)    = I2S_PWM_REG_WS(PWM_CMP0) / 2;
-    I2S_PWM_REG_WS(PWM_CMP2)    = I2S_PWM_REG_WS(PWM_CMP0) - 1024;
+    I2S_PWM_REG_WS(PWM_CMP2)    = I2S_PWM_REG_WS(PWM_CMP0) - _eos_i2s_ck_period;
 
     eos_intr_set(I2S_IRQ_SD_ID, I2S_IRQ_SD_PRIORITY, NULL);
     eos_intr_set(I2S_IRQ_CK_ID, I2S_IRQ_CK_PRIORITY, NULL);
diff --git a/code/fe310/eos/i2s_def.h b/code/fe310/eos/i2s_def.h
index 6f831e2..4b7620e 100644
--- a/code/fe310/eos/i2s_def.h
+++ b/code/fe310/eos/i2s_def.h
@@ -19,7 +19,8 @@
 #define I2S_IRQ_CI_PRIORITY     6
 #define I2S_IRQ_MASK            5
 
-#define I2S_SMPL_WIDTH          13
+#define I2S_SMPL_BITS           13
+#define I2S_SMPL_BITS_S         5
 
 #define I2S_ABUF_SIZE_CHUNK     64
 
diff --git a/code/fe310/eos/timer.c b/code/fe310/eos/timer.c
index 5e1b381..b287317 100644
--- a/code/fe310/eos/timer.c
+++ b/code/fe310/eos/timer.c
@@ -38,6 +38,10 @@ void eos_timer_handle(void) {
     if (*mtimecmp == 0) clear_csr(mie, MIP_MTIP);
 }
 
+void handle_m_time_interrupt(void) {
+    return eos_timer_handle();
+}
+
 void eos_timer_init(void) {
     volatile uint64_t *mtimecmp = (uint64_t *) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
     *mtimecmp = 0;
diff --git a/code/fe310/eos/trap_entry.S b/code/fe310/eos/trap_entry.S
index 7d834f6..0efac2c 100644
--- a/code/fe310/eos/trap_entry.S
+++ b/code/fe310/eos/trap_entry.S
@@ -15,6 +15,10 @@
 
 #define PWM_CFG           0x00
 #define PWM_COUNT         0x08
+#define PWM_CMP0          0x20
+#define PWM_CMP1          0x24
+#define PWM_CMP2          0x28
+#define PWM_CMP3          0x2C
 
 #define PWM_CFG_CMP0IP    0x10000000
 #define PWM_CFG_CMP1IP    0x20000000
@@ -63,6 +67,12 @@ eos_trap_entry:
   j handler
 
 handler_sd:
+  # exit if too early
+  li x18, I2S_PWM_CTRL_ADDR_CK
+  lw x8, PWM_COUNT(x18)
+  lw x9, PWM_CMP2(x18)
+  blt x8, x9, handler_sd_exit_
+
   # read mic value -> x8
   li x18, GPIO_CTRL_ADDR
   lw x8, GPIO_INPUT_VAL(x18)
@@ -84,8 +94,10 @@ handler_sd:
   addi sp, sp, -1*REGBYTES
   STORE x20, 0*REGBYTES(sp)
 
-  # bit <= 0 -> exit
+  # bit <= 0 or bit > 32 -> exit
+  li x18, 32
   bge x0, x9, handler_sd_exit
+  bge x9, x18, handler_sd_exit
 
   # sample |= sd gpio value << (32 - bit) -> x8
   # sample_mask |= 1 << (32 - bit) -> x20
@@ -108,8 +120,8 @@ handler_sd:
   sw x19, 0(x18)
   mv x8, x19
 
-  # bit < I2S_SMPL_WIDTH -> exit
-  li x18, I2S_SMPL_WIDTH
+  # bit < I2S_SMPL_BITS -> exit
+  li x18, I2S_SMPL_BITS
   blt x9, x18, handler_sd_exit
 
   # disable ck irq
@@ -127,15 +139,21 @@ handler_sd:
   sw x0, 0(x18)
   
   # correct for missed bits
-  la x18, sd_sample_save
+  # la x18, sd_sample_save
+  # don't correct
+  # j 0f
   li x19, 0x80000000
-  srai x19, x19, I2S_SMPL_WIDTH-1
+  srai x19, x19, I2S_SMPL_BITS_S-1
   and x20, x20, x19
   beq x19, x20, 0f
-  lw x8, 0(x18)
+  # drop missing
+  # bne x19, x20, handler_sd_exit
+  # lw x8, 0(x18)
+  # zero missing frame
+  mv x8, x0
 0:
-  sw x8, 0(x18)
-  srai x8, x8, 32-I2S_SMPL_WIDTH
+  # sw x8, 0(x18)
+  srai x8, x8, 32-I2S_SMPL_BITS
 
   # aLaw encode -> x8
   li x18, 0x800
@@ -227,6 +245,7 @@ handler_sd_exit:
   LOAD x20, 0*REGBYTES(sp)
   addi sp, sp, 1*REGBYTES
 
+handler_sd_exit_:
   # complete
   li x18, I2S_IRQ_SD_ID
   li x19, PLIC_CLAIM
@@ -250,7 +269,7 @@ handler_ck:
   j trap_exit_data
   
 handler_ws:
-  # enable wsc irq
+  # enable ci irq
   li x18, PLIC_PRIORITY
   li x19, I2S_IRQ_CI_PRIORITY
   sw x19, 4*I2S_IRQ_CI_ID(x18)
@@ -264,7 +283,13 @@ handler_ws:
   j trap_exit_data
 
 handler_ci:
-  # disable wsc/enable ck irq
+  # exit if too early
+  li x18, I2S_PWM_CTRL_ADDR_WS
+  lw x8, PWM_COUNT(x18)
+  lw x9, PWM_CMP2(x18)
+  blt x8, x9, handler_ci_exit
+
+  # disable ci/enable ck irq
   li x18, PLIC_PRIORITY
   sw x0, 4*I2S_IRQ_CI_ID(x18)
   li x19, I2S_IRQ_CK_PRIORITY
@@ -274,7 +299,8 @@ handler_ci:
   li x18, PLIC_THRESHOLD
   li x19, I2S_IRQ_MASK
   sw x19, 0(x18)
-  
+
+handler_ci_exit:
   # complete
   li x18, I2S_IRQ_CI_ID
   li x19, PLIC_CLAIM