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authorUros Majstorovic <majstor@majstor.org>2022-09-30 02:55:19 +0200
committerUros Majstorovic <majstor@majstor.org>2022-09-30 02:55:19 +0200
commit5f69ce2fe3d33c7497470af0b2ee145a5733121c (patch)
treed3e5f521c4f5415b5588ca0353d03a85ab4adbec /hw/prog
parent1c1d32afec4f9ef8f9bed283f5be728314bd29b9 (diff)
added FT2232H programmer adapter board
Diffstat (limited to 'hw/prog')
-rw-r--r--hw/prog/fp-lib-table3
-rw-r--r--hw/prog/prog.kicad_pcb879
-rw-r--r--hw/prog/prog.net233
-rw-r--r--hw/prog/prog.pro248
-rw-r--r--hw/prog/prog.sch242
5 files changed, 1605 insertions, 0 deletions
diff --git a/hw/prog/fp-lib-table b/hw/prog/fp-lib-table
new file mode 100644
index 0000000..2322dfd
--- /dev/null
+++ b/hw/prog/fp-lib-table
@@ -0,0 +1,3 @@
+(fp_lib_table
+ (lib (name footprints)(type KiCad)(uri ${KIPRJMOD}/../footprints.pretty)(options "")(descr ""))
+)
diff --git a/hw/prog/prog.kicad_pcb b/hw/prog/prog.kicad_pcb
new file mode 100644
index 0000000..d48b531
--- /dev/null
+++ b/hw/prog/prog.kicad_pcb
@@ -0,0 +1,879 @@
+(kicad_pcb (version 20171130) (host pcbnew "(5.1.9-0-10_14)")
+
+ (general
+ (thickness 1.6)
+ (drawings 7)
+ (tracks 34)
+ (zones 0)
+ (modules 2)
+ (nets 52)
+ )
+
+ (page A4)
+ (layers
+ (0 F.Cu signal)
+ (31 B.Cu signal)
+ (32 B.Adhes user)
+ (33 F.Adhes user)
+ (34 B.Paste user)
+ (35 F.Paste user)
+ (36 B.SilkS user)
+ (37 F.SilkS user)
+ (38 B.Mask user)
+ (39 F.Mask user)
+ (40 Dwgs.User user)
+ (41 Cmts.User user)
+ (42 Eco1.User user)
+ (43 Eco2.User user)
+ (44 Edge.Cuts user)
+ (45 Margin user)
+ (46 B.CrtYd user)
+ (47 F.CrtYd user)
+ (48 B.Fab user)
+ (49 F.Fab user)
+ )
+
+ (setup
+ (last_trace_width 0.25)
+ (trace_clearance 0.2)
+ (zone_clearance 0.2032)
+ (zone_45_only no)
+ (trace_min 0.2)
+ (via_size 0.8)
+ (via_drill 0.4)
+ (via_min_size 0.4)
+ (via_min_drill 0.3)
+ (uvia_size 0.3)
+ (uvia_drill 0.1)
+ (uvias_allowed no)
+ (uvia_min_size 0.2)
+ (uvia_min_drill 0.1)
+ (edge_width 0.05)
+ (segment_width 0.2)
+ (pcb_text_width 0.3)
+ (pcb_text_size 1.5 1.5)
+ (mod_edge_width 0.12)
+ (mod_text_size 1 1)
+ (mod_text_width 0.15)
+ (pad_size 1.524 1.524)
+ (pad_drill 0.762)
+ (pad_to_mask_clearance 0)
+ (aux_axis_origin 0 0)
+ (visible_elements FFFFFF7F)
+ (pcbplotparams
+ (layerselection 0x010fc_ffffffff)
+ (usegerberextensions false)
+ (usegerberattributes true)
+ (usegerberadvancedattributes true)
+ (creategerberjobfile true)
+ (excludeedgelayer true)
+ (linewidth 0.100000)
+ (plotframeref false)
+ (viasonmask false)
+ (mode 1)
+ (useauxorigin false)
+ (hpglpennumber 1)
+ (hpglpenspeed 20)
+ (hpglpendiameter 15.000000)
+ (psnegative false)
+ (psa4output false)
+ (plotreference true)
+ (plotvalue true)
+ (plotinvisibletext false)
+ (padsonsilk false)
+ (subtractmaskfromsilk false)
+ (outputformat 1)
+ (mirror false)
+ (drillshape 1)
+ (scaleselection 1)
+ (outputdirectory ""))
+ )
+
+ (net 0 "")
+ (net 1 /BD0)
+ (net 2 /BD1)
+ (net 3 GND)
+ (net 4 /AD0)
+ (net 5 /AD2)
+ (net 6 /AD3)
+ (net 7 /AD1)
+ (net 8 /AD5)
+ (net 9 /FE310.UART.TX)
+ (net 10 /FE310.UART.RX)
+ (net 11 "Net-(J1-Pad12)")
+ (net 12 "Net-(J2-Pada23)")
+ (net 13 "Net-(J2-Pada22)")
+ (net 14 "Net-(J2-Pada13)")
+ (net 15 "Net-(J2-Pada19)")
+ (net 16 "Net-(J2-Pada18)")
+ (net 17 "Net-(J2-Pada2)")
+ (net 18 "Net-(J2-Pada20)")
+ (net 19 "Net-(J2-Pada26)")
+ (net 20 "Net-(J2-Pada7)")
+ (net 21 "Net-(J2-Pada12)")
+ (net 22 "Net-(J2-Pada15)")
+ (net 23 "Net-(J2-Pada16)")
+ (net 24 "Net-(J2-Pada6)")
+ (net 25 "Net-(J2-Pada21)")
+ (net 26 "Net-(J2-Pada17)")
+ (net 27 "Net-(J2-Pada25)")
+ (net 28 "Net-(J2-Pada24)")
+ (net 29 "Net-(J2-Pada4)")
+ (net 30 "Net-(J2-Padb6)")
+ (net 31 "Net-(J2-Padb5)")
+ (net 32 "Net-(J2-Padb4)")
+ (net 33 "Net-(J2-Padb24)")
+ (net 34 "Net-(J2-Padb23)")
+ (net 35 "Net-(J2-Padb22)")
+ (net 36 "Net-(J2-Padb21)")
+ (net 37 "Net-(J2-Padb20)")
+ (net 38 "Net-(J2-Padb19)")
+ (net 39 "Net-(J2-Padb18)")
+ (net 40 "Net-(J2-Padb17)")
+ (net 41 "Net-(J2-Padb16)")
+ (net 42 "Net-(J2-Padb15)")
+ (net 43 "Net-(J2-Padb14)")
+ (net 44 "Net-(J2-Padb13)")
+ (net 45 "Net-(J2-Padb12)")
+ (net 46 "Net-(J2-Padb11)")
+ (net 47 "Net-(J2-Padb10)")
+ (net 48 "Net-(J2-Padb9)")
+ (net 49 "Net-(J2-Padb8)")
+ (net 50 "Net-(J2-Padb7)")
+ (net 51 "Net-(J2-Padb2)")
+
+ (net_class Default "This is the default net class."
+ (clearance 0.2)
+ (trace_width 0.25)
+ (via_dia 0.8)
+ (via_drill 0.4)
+ (uvia_dia 0.3)
+ (uvia_drill 0.1)
+ (add_net /AD0)
+ (add_net /AD1)
+ (add_net /AD2)
+ (add_net /AD3)
+ (add_net /AD5)
+ (add_net /BD0)
+ (add_net /BD1)
+ (add_net /FE310.UART.RX)
+ (add_net /FE310.UART.TX)
+ (add_net GND)
+ (add_net "Net-(J1-Pad12)")
+ (add_net "Net-(J2-Pada12)")
+ (add_net "Net-(J2-Pada13)")
+ (add_net "Net-(J2-Pada15)")
+ (add_net "Net-(J2-Pada16)")
+ (add_net "Net-(J2-Pada17)")
+ (add_net "Net-(J2-Pada18)")
+ (add_net "Net-(J2-Pada19)")
+ (add_net "Net-(J2-Pada2)")
+ (add_net "Net-(J2-Pada20)")
+ (add_net "Net-(J2-Pada21)")
+ (add_net "Net-(J2-Pada22)")
+ (add_net "Net-(J2-Pada23)")
+ (add_net "Net-(J2-Pada24)")
+ (add_net "Net-(J2-Pada25)")
+ (add_net "Net-(J2-Pada26)")
+ (add_net "Net-(J2-Pada4)")
+ (add_net "Net-(J2-Pada6)")
+ (add_net "Net-(J2-Pada7)")
+ (add_net "Net-(J2-Padb10)")
+ (add_net "Net-(J2-Padb11)")
+ (add_net "Net-(J2-Padb12)")
+ (add_net "Net-(J2-Padb13)")
+ (add_net "Net-(J2-Padb14)")
+ (add_net "Net-(J2-Padb15)")
+ (add_net "Net-(J2-Padb16)")
+ (add_net "Net-(J2-Padb17)")
+ (add_net "Net-(J2-Padb18)")
+ (add_net "Net-(J2-Padb19)")
+ (add_net "Net-(J2-Padb2)")
+ (add_net "Net-(J2-Padb20)")
+ (add_net "Net-(J2-Padb21)")
+ (add_net "Net-(J2-Padb22)")
+ (add_net "Net-(J2-Padb23)")
+ (add_net "Net-(J2-Padb24)")
+ (add_net "Net-(J2-Padb4)")
+ (add_net "Net-(J2-Padb5)")
+ (add_net "Net-(J2-Padb6)")
+ (add_net "Net-(J2-Padb7)")
+ (add_net "Net-(J2-Padb8)")
+ (add_net "Net-(J2-Padb9)")
+ )
+
+ (module Connector_FFC-FPC:Hirose_FH12-12S-0.5SH_1x12-1MP_P0.50mm_Horizontal (layer F.Cu) (tedit 633603EB) (tstamp 63367DA9)
+ (at 125.6 77.5 180)
+ (descr "Hirose FH12, FFC/FPC connector, FH12-12S-0.5SH, 12 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator")
+ (tags "connector Hirose FH12 horizontal")
+ (path /6339B3FE)
+ (attr smd)
+ (fp_text reference J1 (at 4.7 -2.6) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value Phone (at 0 5.6) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_line (start -6.05 -3) (end 6.05 -3) (layer F.CrtYd) (width 0.05))
+ (fp_line (start -6.05 4.9) (end -6.05 -3) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 6.05 4.9) (end -6.05 4.9) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 6.05 -3) (end 6.05 4.9) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 2.75 -0.492893) (end 2.25 -1.2) (layer F.Fab) (width 0.1))
+ (fp_line (start 3.25 -1.2) (end 2.75 -0.492893) (layer F.Fab) (width 0.1))
+ (fp_line (start 3.16 -1.3) (end 3.16 -2.5) (layer F.SilkS) (width 0.12))
+ (fp_line (start -4.65 4.5) (end -4.65 2.76) (layer F.SilkS) (width 0.12))
+ (fp_line (start 4.65 4.5) (end -4.65 4.5) (layer F.SilkS) (width 0.12))
+ (fp_line (start 4.65 2.76) (end 4.65 4.5) (layer F.SilkS) (width 0.12))
+ (fp_line (start -4.65 -1.3) (end -4.65 0.04) (layer F.SilkS) (width 0.12))
+ (fp_line (start -3.16 -1.3) (end -4.65 -1.3) (layer F.SilkS) (width 0.12))
+ (fp_line (start 4.65 -1.3) (end 4.65 0.04) (layer F.SilkS) (width 0.12))
+ (fp_line (start 3.16 -1.3) (end 4.65 -1.3) (layer F.SilkS) (width 0.12))
+ (fp_line (start -4.45 4.4) (end 0 4.4) (layer F.Fab) (width 0.1))
+ (fp_line (start -4.45 3.7) (end -4.45 4.4) (layer F.Fab) (width 0.1))
+ (fp_line (start -3.95 3.7) (end -4.45 3.7) (layer F.Fab) (width 0.1))
+ (fp_line (start -3.95 3.4) (end -3.95 3.7) (layer F.Fab) (width 0.1))
+ (fp_line (start -4.55 3.4) (end -3.95 3.4) (layer F.Fab) (width 0.1))
+ (fp_line (start -4.55 -1.2) (end -4.55 3.4) (layer F.Fab) (width 0.1))
+ (fp_line (start 0 -1.2) (end -4.55 -1.2) (layer F.Fab) (width 0.1))
+ (fp_line (start 4.45 4.4) (end 0 4.4) (layer F.Fab) (width 0.1))
+ (fp_line (start 4.45 3.7) (end 4.45 4.4) (layer F.Fab) (width 0.1))
+ (fp_line (start 3.95 3.7) (end 4.45 3.7) (layer F.Fab) (width 0.1))
+ (fp_line (start 3.95 3.4) (end 3.95 3.7) (layer F.Fab) (width 0.1))
+ (fp_line (start 4.55 3.4) (end 3.95 3.4) (layer F.Fab) (width 0.1))
+ (fp_line (start 4.55 -1.2) (end 4.55 3.4) (layer F.Fab) (width 0.1))
+ (fp_line (start 0 -1.2) (end 4.55 -1.2) (layer F.Fab) (width 0.1))
+ (fp_text user %R (at 0 3.7) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (pad MP smd rect (at -4.65 1.4 180) (size 1.8 2.2) (layers F.Cu F.Paste F.Mask))
+ (pad MP smd rect (at 4.65 1.4 180) (size 1.8 2.2) (layers F.Cu F.Paste F.Mask))
+ (pad 1 smd rect (at 2.75 -1.85 180) (size 0.3 1.3) (layers F.Cu F.Paste F.Mask)
+ (net 1 /BD0))
+ (pad 2 smd rect (at 2.25 -1.85 180) (size 0.3 1.3) (layers F.Cu F.Paste F.Mask)
+ (net 2 /BD1))
+ (pad 3 smd rect (at 1.75 -1.85 180) (size 0.3 1.3) (layers F.Cu F.Paste F.Mask)
+ (net 3 GND))
+ (pad 4 smd rect (at 1.25 -1.85 180) (size 0.3 1.3) (layers F.Cu F.Paste F.Mask)
+ (net 4 /AD0))
+ (pad 5 smd rect (at 0.75 -1.85 180) (size 0.3 1.3) (layers F.Cu F.Paste F.Mask)
+ (net 5 /AD2))
+ (pad 6 smd rect (at 0.25 -1.85 180) (size 0.3 1.3) (layers F.Cu F.Paste F.Mask)
+ (net 6 /AD3))
+ (pad 7 smd rect (at -0.25 -1.85 180) (size 0.3 1.3) (layers F.Cu F.Paste F.Mask)
+ (net 7 /AD1))
+ (pad 8 smd rect (at -0.75 -1.85 180) (size 0.3 1.3) (layers F.Cu F.Paste F.Mask)
+ (net 8 /AD5))
+ (pad 9 smd rect (at -1.25 -1.85 180) (size 0.3 1.3) (layers F.Cu F.Paste F.Mask)
+ (net 3 GND))
+ (pad 10 smd rect (at -1.75 -1.85 180) (size 0.3 1.3) (layers F.Cu F.Paste F.Mask)
+ (net 9 /FE310.UART.TX))
+ (pad 11 smd rect (at -2.25 -1.85 180) (size 0.3 1.3) (layers F.Cu F.Paste F.Mask)
+ (net 10 /FE310.UART.RX))
+ (pad 12 smd rect (at -2.75 -1.85 180) (size 0.3 1.3) (layers F.Cu F.Paste F.Mask)
+ (net 11 "Net-(J1-Pad12)"))
+ (model ${KISYS3DMOD}/Connector_FFC-FPC.3dshapes/Hirose_FH12-12S-0.5SH_1x12-1MP_P0.50mm_Horizontal.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module footprints:FT2232H-56Q-MMDL (layer F.Cu) (tedit 6335F5EE) (tstamp 63367E03)
+ (at 135.5 112.7 180)
+ (path /6338AFA6)
+ (fp_text reference J2 (at 4 0) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value FT2232H (at 9.85 1.35) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_line (start 1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
+ (fp_line (start -1.27 -1.33) (end -3.87 -1.33) (layer F.SilkS) (width 0.12))
+ (fp_line (start 1.8 -1.8) (end 1.8 32.25) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 1.33 0) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
+ (fp_line (start -4.35 -1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
+ (fp_line (start -1.27 1.27) (end -1.27 -1.33) (layer F.SilkS) (width 0.12))
+ (fp_line (start -4.35 32.25) (end -4.35 -1.8) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 1.8 32.25) (end -4.35 32.25) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 1.33 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.12))
+ (fp_line (start -3.81 -1.27) (end -3.81 31.75) (layer F.Fab) (width 0.1))
+ (fp_line (start -3.81 31.75) (end 1.27 31.75) (layer F.Fab) (width 0.1))
+ (fp_line (start 0 -1.27) (end -3.81 -1.27) (layer F.Fab) (width 0.1))
+ (fp_line (start -3.87 -1.33) (end -3.87 31.81) (layer F.SilkS) (width 0.12))
+ (fp_line (start 1.27 31.75) (end 1.27 0) (layer F.Fab) (width 0.1))
+ (fp_line (start 1.27 0) (end 0 -1.27) (layer F.Fab) (width 0.1))
+ (fp_line (start 1.33 31.81) (end -3.87 31.81) (layer F.SilkS) (width 0.12))
+ (fp_line (start 1.33 1.27) (end 1.33 31.81) (layer F.SilkS) (width 0.12))
+ (fp_line (start 19.08 31.75) (end 24.16 31.75) (layer F.Fab) (width 0.1))
+ (fp_line (start 19.08 -1.27) (end 19.08 31.75) (layer F.Fab) (width 0.1))
+ (fp_line (start 22.89 -1.27) (end 19.08 -1.27) (layer F.Fab) (width 0.1))
+ (fp_line (start 24.22 1.27) (end 21.62 1.27) (layer F.SilkS) (width 0.12))
+ (fp_line (start 19.02 -1.33) (end 19.02 31.81) (layer F.SilkS) (width 0.12))
+ (fp_line (start 24.22 1.27) (end 24.22 31.81) (layer F.SilkS) (width 0.12))
+ (fp_line (start 24.22 31.81) (end 19.02 31.81) (layer F.SilkS) (width 0.12))
+ (fp_line (start 24.16 0) (end 22.89 -1.27) (layer F.Fab) (width 0.1))
+ (fp_line (start 24.16 31.75) (end 24.16 0) (layer F.Fab) (width 0.1))
+ (fp_line (start 18.54 -1.8) (end 24.69 -1.8) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 18.54 32.25) (end 18.54 -1.8) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 24.69 32.25) (end 18.54 32.25) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 24.69 -1.8) (end 24.69 32.25) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 24.22 -1.33) (end 22.89 -1.33) (layer F.SilkS) (width 0.12))
+ (fp_line (start 24.22 0) (end 24.22 -1.33) (layer F.SilkS) (width 0.12))
+ (fp_line (start 21.62 -1.33) (end 19.02 -1.33) (layer F.SilkS) (width 0.12))
+ (fp_line (start 21.62 1.27) (end 21.62 -1.33) (layer F.SilkS) (width 0.12))
+ (pad a23 thru_hole oval (at 0 27.94 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 12 "Net-(J2-Pada23)"))
+ (pad a22 thru_hole oval (at -2.54 25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 13 "Net-(J2-Pada22)"))
+ (pad a9 thru_hole oval (at 0 10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 7 /AD1))
+ (pad a13 thru_hole oval (at 0 15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 14 "Net-(J2-Pada13)"))
+ (pad a19 thru_hole oval (at 0 22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 15 "Net-(J2-Pada19)"))
+ (pad a18 thru_hole oval (at -2.54 20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 16 "Net-(J2-Pada18)"))
+ (pad a2 thru_hole oval (at -2.54 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 17 "Net-(J2-Pada2)"))
+ (pad a20 thru_hole oval (at -2.54 22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 18 "Net-(J2-Pada20)"))
+ (pad a5 thru_hole oval (at 0 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 3 GND))
+ (pad a26 thru_hole oval (at -2.54 30.48 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 19 "Net-(J2-Pada26)"))
+ (pad a3 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 3 GND))
+ (pad a1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 3 GND))
+ (pad a14 thru_hole oval (at -2.54 15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 8 /AD5))
+ (pad a7 thru_hole oval (at 0 7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 20 "Net-(J2-Pada7)"))
+ (pad a12 thru_hole oval (at -2.54 12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 21 "Net-(J2-Pada12)"))
+ (pad a15 thru_hole oval (at 0 17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 22 "Net-(J2-Pada15)"))
+ (pad a16 thru_hole oval (at -2.54 17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 23 "Net-(J2-Pada16)"))
+ (pad a6 thru_hole oval (at -2.54 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 24 "Net-(J2-Pada6)"))
+ (pad a21 thru_hole oval (at 0 25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 25 "Net-(J2-Pada21)"))
+ (pad a17 thru_hole oval (at 0 20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+ (net 26 "Net-(J2-Pada17)"))
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+ )
+ )
+ )
+)
diff --git a/hw/prog/prog.net b/hw/prog/prog.net
new file mode 100644
index 0000000..8e48926
--- /dev/null
+++ b/hw/prog/prog.net
@@ -0,0 +1,233 @@
+(export (version D)
+ (design
+ (source /Volumes/rvPhone/repo/hw/prog/prog.sch)
+ (date "Friday, September 30, 2022 at 02:46:32 AM")
+ (tool "Eeschema (5.1.9-0-10_14)")
+ (sheet (number 1) (name /) (tstamps /)
+ (title_block
+ (title)
+ (company)
+ (rev)
+ (date)
+ (source prog.sch)
+ (comment (number 1) (value ""))
+ (comment (number 2) (value ""))
+ (comment (number 3) (value ""))
+ (comment (number 4) (value "")))))
+ (components
+ (comp (ref J2)
+ (value FT2232H)
+ (footprint footprints:FT2232H-56Q-MMDL)
+ (datasheet ~)
+ (libsource (lib Connector_Generic) (part Conn_02x26_Row_Letter_First) (description "Generic connector, double row, 02x26, row letter first pin numbering scheme (pin number consists of a letter for the row and a number for the pin index in this row. a1, ..., aN; b1, ..., bN), script generated (kicad-library-utils/schlib/autogen/connector/)"))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 6338AFA6))
+ (comp (ref J1)
+ (value Phone)
+ (footprint Connector_FFC-FPC:Hirose_FH12-12S-0.5SH_1x12-1MP_P0.50mm_Horizontal)
+ (datasheet ~)
+ (libsource (lib Connector_Generic) (part Conn_01x12) (description "Generic connector, single row, 01x12, script generated (kicad-library-utils/schlib/autogen/connector/)"))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 6339B3FE)))
+ (libparts
+ (libpart (lib Connector_Generic) (part Conn_01x12)
+ (description "Generic connector, single row, 01x12, script generated (kicad-library-utils/schlib/autogen/connector/)")
+ (docs ~)
+ (footprints
+ (fp Connector*:*_1x??_*))
+ (fields
+ (field (name Reference) J)
+ (field (name Value) Conn_01x12))
+ (pins
+ (pin (num 1) (name Pin_1) (type passive))
+ (pin (num 2) (name Pin_2) (type passive))
+ (pin (num 3) (name Pin_3) (type passive))
+ (pin (num 4) (name Pin_4) (type passive))
+ (pin (num 5) (name Pin_5) (type passive))
+ (pin (num 6) (name Pin_6) (type passive))
+ (pin (num 7) (name Pin_7) (type passive))
+ (pin (num 8) (name Pin_8) (type passive))
+ (pin (num 9) (name Pin_9) (type passive))
+ (pin (num 10) (name Pin_10) (type passive))
+ (pin (num 11) (name Pin_11) (type passive))
+ (pin (num 12) (name Pin_12) (type passive))))
+ (libpart (lib Connector_Generic) (part Conn_02x26_Row_Letter_First)
+ (description "Generic connector, double row, 02x26, row letter first pin numbering scheme (pin number consists of a letter for the row and a number for the pin index in this row. a1, ..., aN; b1, ..., bN), script generated (kicad-library-utils/schlib/autogen/connector/)")
+ (docs ~)
+ (footprints
+ (fp Connector*:*_2x??_*))
+ (fields
+ (field (name Reference) J)
+ (field (name Value) Conn_02x26_Row_Letter_First))
+ (pins
+ (pin (num a1) (name Pin_a1) (type passive))
+ (pin (num a2) (name Pin_a2) (type passive))
+ (pin (num a3) (name Pin_a3) (type passive))
+ (pin (num a4) (name Pin_a4) (type passive))
+ (pin (num a5) (name Pin_a5) (type passive))
+ (pin (num a6) (name Pin_a6) (type passive))
+ (pin (num a7) (name Pin_a7) (type passive))
+ (pin (num a8) (name Pin_a8) (type passive))
+ (pin (num a9) (name Pin_a9) (type passive))
+ (pin (num a10) (name Pin_a10) (type passive))
+ (pin (num a11) (name Pin_a11) (type passive))
+ (pin (num a12) (name Pin_a12) (type passive))
+ (pin (num a13) (name Pin_a13) (type passive))
+ (pin (num a14) (name Pin_a14) (type passive))
+ (pin (num a15) (name Pin_a15) (type passive))
+ (pin (num a16) (name Pin_a16) (type passive))
+ (pin (num a17) (name Pin_a17) (type passive))
+ (pin (num a18) (name Pin_a18) (type passive))
+ (pin (num a19) (name Pin_a19) (type passive))
+ (pin (num a20) (name Pin_a20) (type passive))
+ (pin (num a21) (name Pin_a21) (type passive))
+ (pin (num a22) (name Pin_a22) (type passive))
+ (pin (num a23) (name Pin_a23) (type passive))
+ (pin (num a24) (name Pin_a24) (type passive))
+ (pin (num a25) (name Pin_a25) (type passive))
+ (pin (num a26) (name Pin_a26) (type passive))
+ (pin (num b1) (name Pin_b1) (type passive))
+ (pin (num b2) (name Pin_b2) (type passive))
+ (pin (num b3) (name Pin_b3) (type passive))
+ (pin (num b4) (name Pin_b4) (type passive))
+ (pin (num b5) (name Pin_b5) (type passive))
+ (pin (num b6) (name Pin_b6) (type passive))
+ (pin (num b7) (name Pin_b7) (type passive))
+ (pin (num b8) (name Pin_b8) (type passive))
+ (pin (num b9) (name Pin_b9) (type passive))
+ (pin (num b10) (name Pin_b10) (type passive))
+ (pin (num b11) (name Pin_b11) (type passive))
+ (pin (num b12) (name Pin_b12) (type passive))
+ (pin (num b13) (name Pin_b13) (type passive))
+ (pin (num b14) (name Pin_b14) (type passive))
+ (pin (num b15) (name Pin_b15) (type passive))
+ (pin (num b16) (name Pin_b16) (type passive))
+ (pin (num b17) (name Pin_b17) (type passive))
+ (pin (num b18) (name Pin_b18) (type passive))
+ (pin (num b19) (name Pin_b19) (type passive))
+ (pin (num b20) (name Pin_b20) (type passive))
+ (pin (num b21) (name Pin_b21) (type passive))
+ (pin (num b22) (name Pin_b22) (type passive))
+ (pin (num b23) (name Pin_b23) (type passive))
+ (pin (num b24) (name Pin_b24) (type passive))
+ (pin (num b25) (name Pin_b25) (type passive))
+ (pin (num b26) (name Pin_b26) (type passive)))))
+ (libraries
+ (library (logical Connector_Generic)
+ (uri "/Library/Application Support/kicad/library/Connector_Generic.lib")))
+ (nets
+ (net (code 1) (name /AD3)
+ (node (ref J2) (pin a11))
+ (node (ref J1) (pin 6)))
+ (net (code 2) (name "Net-(J2-Pada12)")
+ (node (ref J2) (pin a12)))
+ (net (code 3) (name "Net-(J2-Pada13)")
+ (node (ref J2) (pin a13)))
+ (net (code 4) (name "Net-(J2-Pada15)")
+ (node (ref J2) (pin a15)))
+ (net (code 5) (name "Net-(J2-Pada16)")
+ (node (ref J2) (pin a16)))
+ (net (code 6) (name "Net-(J2-Pada17)")
+ (node (ref J2) (pin a17)))
+ (net (code 7) (name "Net-(J2-Pada18)")
+ (node (ref J2) (pin a18)))
+ (net (code 8) (name "Net-(J2-Pada19)")
+ (node (ref J2) (pin a19)))
+ (net (code 9) (name "Net-(J2-Pada2)")
+ (node (ref J2) (pin a2)))
+ (net (code 10) (name "Net-(J2-Pada20)")
+ (node (ref J2) (pin a20)))
+ (net (code 11) (name "Net-(J2-Pada21)")
+ (node (ref J2) (pin a21)))
+ (net (code 12) (name "Net-(J2-Pada22)")
+ (node (ref J2) (pin a22)))
+ (net (code 13) (name "Net-(J2-Pada23)")
+ (node (ref J2) (pin a23)))
+ (net (code 14) (name "Net-(J2-Pada24)")
+ (node (ref J2) (pin a24)))
+ (net (code 15) (name "Net-(J2-Pada25)")
+ (node (ref J2) (pin a25)))
+ (net (code 16) (name "Net-(J2-Pada26)")
+ (node (ref J2) (pin a26)))
+ (net (code 17) (name "Net-(J2-Pada4)")
+ (node (ref J2) (pin a4)))
+ (net (code 18) (name "Net-(J2-Pada6)")
+ (node (ref J2) (pin a6)))
+ (net (code 19) (name "Net-(J2-Pada7)")
+ (node (ref J2) (pin a7)))
+ (net (code 20) (name "Net-(J2-Padb10)")
+ (node (ref J2) (pin b10)))
+ (net (code 21) (name "Net-(J2-Padb11)")
+ (node (ref J2) (pin b11)))
+ (net (code 22) (name "Net-(J2-Padb12)")
+ (node (ref J2) (pin b12)))
+ (net (code 23) (name "Net-(J2-Padb13)")
+ (node (ref J2) (pin b13)))
+ (net (code 24) (name "Net-(J2-Padb14)")
+ (node (ref J2) (pin b14)))
+ (net (code 25) (name "Net-(J2-Padb15)")
+ (node (ref J2) (pin b15)))
+ (net (code 26) (name "Net-(J2-Padb16)")
+ (node (ref J2) (pin b16)))
+ (net (code 27) (name "Net-(J2-Padb17)")
+ (node (ref J2) (pin b17)))
+ (net (code 28) (name "Net-(J2-Padb18)")
+ (node (ref J2) (pin b18)))
+ (net (code 29) (name "Net-(J2-Padb19)")
+ (node (ref J2) (pin b19)))
+ (net (code 30) (name "Net-(J2-Padb2)")
+ (node (ref J2) (pin b2)))
+ (net (code 31) (name "Net-(J2-Padb20)")
+ (node (ref J2) (pin b20)))
+ (net (code 32) (name "Net-(J2-Padb21)")
+ (node (ref J2) (pin b21)))
+ (net (code 33) (name "Net-(J2-Padb22)")
+ (node (ref J2) (pin b22)))
+ (net (code 34) (name "Net-(J2-Padb23)")
+ (node (ref J2) (pin b23)))
+ (net (code 35) (name "Net-(J2-Padb24)")
+ (node (ref J2) (pin b24)))
+ (net (code 36) (name /BD1)
+ (node (ref J1) (pin 2))
+ (node (ref J2) (pin b26)))
+ (net (code 37) (name "Net-(J2-Padb4)")
+ (node (ref J2) (pin b4)))
+ (net (code 38) (name "Net-(J2-Padb5)")
+ (node (ref J2) (pin b5)))
+ (net (code 39) (name "Net-(J2-Padb6)")
+ (node (ref J2) (pin b6)))
+ (net (code 40) (name "Net-(J2-Padb7)")
+ (node (ref J2) (pin b7)))
+ (net (code 41) (name "Net-(J2-Padb8)")
+ (node (ref J2) (pin b8)))
+ (net (code 42) (name "Net-(J2-Padb9)")
+ (node (ref J2) (pin b9)))
+ (net (code 43) (name /AD2)
+ (node (ref J1) (pin 5))
+ (node (ref J2) (pin a10)))
+ (net (code 44) (name GND)
+ (node (ref J2) (pin a1))
+ (node (ref J2) (pin a3))
+ (node (ref J2) (pin a5))
+ (node (ref J2) (pin b1))
+ (node (ref J2) (pin b3))
+ (node (ref J1) (pin 3))
+ (node (ref J1) (pin 9)))
+ (net (code 45) (name /FE310.UART.TX)
+ (node (ref J1) (pin 10)))
+ (net (code 46) (name /FE310.UART.RX)
+ (node (ref J1) (pin 11)))
+ (net (code 47) (name "Net-(J1-Pad12)")
+ (node (ref J1) (pin 12)))
+ (net (code 48) (name /BD0)
+ (node (ref J1) (pin 1))
+ (node (ref J2) (pin b25)))
+ (net (code 49) (name /AD5)
+ (node (ref J2) (pin a14))
+ (node (ref J1) (pin 8)))
+ (net (code 50) (name /AD0)
+ (node (ref J2) (pin a8))
+ (node (ref J1) (pin 4)))
+ (net (code 51) (name /AD1)
+ (node (ref J2) (pin a9))
+ (node (ref J1) (pin 7))))) \ No newline at end of file
diff --git a/hw/prog/prog.pro b/hw/prog/prog.pro
new file mode 100644
index 0000000..d97e0d9
--- /dev/null
+++ b/hw/prog/prog.pro
@@ -0,0 +1,248 @@
+update=Thursday, September 29, 2022 at 10:44:18 PM
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=prog.net
+CopperLayerCount=2
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.2
+MinViaDiameter=0.4
+MinViaDrill=0.3
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+TrackWidth1=0.25
+ViaDiameter1=0.8
+ViaDrill1=0.4
+dPairWidth1=0.2
+dPairGap1=0.25
+dPairViaGap1=0.25
+SilkLineWidth=0.12
+SilkTextSizeV=1
+SilkTextSizeH=1
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.05
+CourtyardLineWidth=0.05
+OthersLineWidth=0.15
+OthersTextSizeV=1
+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0
+SolderMaskMinWidth=0
+SolderPasteClearance=0
+SolderPasteRatio=0
+[pcbnew/Layer.F.Cu]
+Name=F.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In1.Cu]
+Name=In1.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In2.Cu]
+Name=In2.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In3.Cu]
+Name=In3.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In4.Cu]
+Name=In4.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In5.Cu]
+Name=In5.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In6.Cu]
+Name=In6.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In7.Cu]
+Name=In7.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In8.Cu]
+Name=In8.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In9.Cu]
+Name=In9.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In10.Cu]
+Name=In10.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In11.Cu]
+Name=In11.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In12.Cu]
+Name=In12.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In13.Cu]
+Name=In13.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In14.Cu]
+Name=In14.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In15.Cu]
+Name=In15.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In16.Cu]
+Name=In16.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In17.Cu]
+Name=In17.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In18.Cu]
+Name=In18.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In19.Cu]
+Name=In19.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In20.Cu]
+Name=In20.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In21.Cu]
+Name=In21.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In22.Cu]
+Name=In22.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In23.Cu]
+Name=In23.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In24.Cu]
+Name=In24.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In25.Cu]
+Name=In25.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In26.Cu]
+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=B.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=1
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.2
+TrackWidth=0.25
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
diff --git a/hw/prog/prog.sch b/hw/prog/prog.sch
new file mode 100644
index 0000000..9bdbe93
--- /dev/null
+++ b/hw/prog/prog.sch
@@ -0,0 +1,242 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Connector_Generic:Conn_02x26_Row_Letter_First J2
+U 1 1 6338AFA6
+P 3850 2600
+F 0 "J2" H 3900 4017 50 0000 C CNN
+F 1 "FT2232H" H 3900 3926 50 0000 C CNN
+F 2 "footprints:FT2232H-56Q-MMDL" H 3850 2600 50 0001 C CNN
+F 3 "~" H 3850 2600 50 0001 C CNN
+ 1 3850 2600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3650 1400 3450 1400
+Wire Wire Line
+ 3650 1600 3450 1600
+Wire Wire Line
+ 3450 1400 3450 1600
+Wire Wire Line
+ 3650 1800 3450 1800
+Wire Wire Line
+ 3450 1800 3450 1600
+Connection ~ 3450 1600
+Wire Wire Line
+ 4150 1400 4350 1400
+Wire Wire Line
+ 4350 1400 4350 1600
+Wire Wire Line
+ 4350 1600 4150 1600
+Text Label 3150 2700 0 50 ~ 0
+AD5
+Wire Wire Line
+ 3650 2400 3150 2400
+Text Label 3150 2100 0 50 ~ 0
+AD0
+Text Label 3150 2200 0 50 ~ 0
+AD1
+Text Label 3150 2300 0 50 ~ 0
+AD2
+Text Label 3150 2400 0 50 ~ 0
+AD3
+Wire Wire Line
+ 4150 3900 4650 3900
+Text Label 4650 3900 2 50 ~ 0
+BD1
+Text Label 4650 3800 2 50 ~ 0
+BD0
+$Comp
+L power:GND #PWR0101
+U 1 1 63392EC5
+P 3450 1850
+F 0 "#PWR0101" H 3450 1600 50 0001 C CNN
+F 1 "GND" H 3455 1677 50 0000 C CNN
+F 2 "" H 3450 1850 50 0001 C CNN
+F 3 "" H 3450 1850 50 0001 C CNN
+ 1 3450 1850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3450 1800 3450 1850
+Connection ~ 3450 1800
+$Comp
+L power:GND #PWR0102
+U 1 1 6339365E
+P 4350 1650
+F 0 "#PWR0102" H 4350 1400 50 0001 C CNN
+F 1 "GND" H 4355 1477 50 0000 C CNN
+F 2 "" H 4350 1650 50 0001 C CNN
+F 3 "" H 4350 1650 50 0001 C CNN
+ 1 4350 1650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4350 1650 4350 1600
+Connection ~ 4350 1600
+NoConn ~ 3650 1500
+NoConn ~ 4150 1500
+NoConn ~ 3650 1700
+NoConn ~ 4150 1700
+NoConn ~ 4150 1800
+NoConn ~ 3650 1900
+NoConn ~ 3650 2000
+NoConn ~ 3650 2500
+NoConn ~ 3650 2600
+NoConn ~ 3650 2800
+NoConn ~ 3650 2900
+NoConn ~ 3650 3000
+NoConn ~ 3650 3100
+NoConn ~ 3650 3200
+NoConn ~ 3650 3300
+NoConn ~ 3650 3400
+NoConn ~ 3650 3500
+NoConn ~ 3650 3600
+NoConn ~ 3650 3700
+NoConn ~ 3650 3800
+NoConn ~ 3650 3900
+NoConn ~ 4150 3700
+NoConn ~ 4150 3600
+NoConn ~ 4150 3500
+NoConn ~ 4150 3400
+NoConn ~ 4150 3300
+NoConn ~ 4150 3200
+NoConn ~ 4150 3100
+NoConn ~ 4150 3000
+NoConn ~ 4150 2900
+NoConn ~ 4150 2800
+NoConn ~ 4150 2700
+NoConn ~ 4150 2600
+NoConn ~ 4150 2500
+NoConn ~ 4150 2400
+NoConn ~ 4150 2300
+NoConn ~ 4150 2200
+NoConn ~ 4150 2100
+NoConn ~ 4150 2000
+NoConn ~ 4150 1900
+$Comp
+L Connector_Generic:Conn_01x12 J1
+U 1 1 6339B3FE
+P 1550 2500
+F 0 "J1" H 1468 3217 50 0000 C CNN
+F 1 "Phone" H 1468 3126 50 0000 C CNN
+F 2 "Connector_FFC-FPC:Hirose_FH12-12S-0.5SH_1x12-1MP_P0.50mm_Horizontal" H 1550 2500 50 0001 C CNN
+F 3 "~" H 1550 2500 50 0001 C CNN
+ 1 1550 2500
+ -1 0 0 -1
+$EndComp
+Text Label 2500 2000 2 50 ~ 0
+ESP.UART.RX
+Wire Wire Line
+ 1750 2900 2500 2900
+Wire Wire Line
+ 1750 2800 1850 2800
+Wire Wire Line
+ 1850 2800 1850 2200
+Wire Wire Line
+ 1850 2200 1750 2200
+NoConn ~ 1750 3100
+Wire Wire Line
+ 1750 3000 2500 3000
+Text Label 2500 2100 2 50 ~ 0
+ESP.UART.TX
+Text Label 2500 2300 2 50 ~ 0
+JTAG.TCK
+Text Label 2500 2400 2 50 ~ 0
+JTAG.TDO
+Text Label 2500 2500 2 50 ~ 0
+JTAG.TMS
+Text Label 2500 2600 2 50 ~ 0
+JTAG.TDI
+Text Label 2500 2700 2 50 ~ 0
+JTAG.TRST
+Text Label 2500 2900 2 50 ~ 0
+FE310.UART.TX
+Text Label 2500 3000 2 50 ~ 0
+FE310.UART.RX
+Wire Wire Line
+ 1850 2800 1850 3200
+Connection ~ 1850 2800
+$Comp
+L power:GND #PWR0103
+U 1 1 633AA622
+P 1850 3200
+F 0 "#PWR0103" H 1850 2950 50 0001 C CNN
+F 1 "GND" H 1855 3027 50 0000 C CNN
+F 2 "" H 1850 3200 50 0001 C CNN
+F 3 "" H 1850 3200 50 0001 C CNN
+ 1 1850 3200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2850 2300 2850 2100
+Wire Wire Line
+ 2850 2100 3650 2100
+Wire Wire Line
+ 1750 2300 2850 2300
+Wire Wire Line
+ 2950 2200 2950 2600
+Wire Wire Line
+ 2950 2200 3650 2200
+Wire Wire Line
+ 1750 2600 2950 2600
+Wire Wire Line
+ 3650 2300 3050 2300
+Wire Wire Line
+ 3050 2300 3050 2400
+Wire Wire Line
+ 3050 2400 1750 2400
+Wire Wire Line
+ 4650 4000 4650 3900
+Wire Wire Line
+ 1750 2100 2650 2100
+Wire Wire Line
+ 4750 3800 4750 4100
+Wire Wire Line
+ 4750 4100 2750 4100
+Wire Wire Line
+ 4150 3800 4750 3800
+Wire Wire Line
+ 1750 2000 2750 2000
+Wire Wire Line
+ 3150 2500 3150 2400
+Wire Wire Line
+ 1750 2700 3650 2700
+Wire Wire Line
+ 1750 2500 3150 2500
+Wire Wire Line
+ 2650 4000 4650 4000
+Wire Wire Line
+ 2650 2100 2650 4000
+Wire Wire Line
+ 2750 4100 2750 2000
+NoConn ~ 2500 2900
+NoConn ~ 2500 3000
+$Comp
+L power:PWR_FLAG #FLG0101
+U 1 1 633C2B15
+P 1850 1800
+F 0 "#FLG0101" H 1850 1875 50 0001 C CNN
+F 1 "PWR_FLAG" H 1850 1973 50 0000 C CNN
+F 2 "" H 1850 1800 50 0001 C CNN
+F 3 "~" H 1850 1800 50 0001 C CNN
+ 1 1850 1800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1850 2200 1850 1800
+Connection ~ 1850 2200
+$EndSCHEMATC