summaryrefslogtreecommitdiff
path: root/hw/rvPhone/rvPhone.pro
diff options
context:
space:
mode:
authorUros Majstorovic <majstor@majstor.org>2020-12-04 06:55:06 +0100
committerUros Majstorovic <majstor@majstor.org>2020-12-04 06:55:06 +0100
commit3a855f8235295e9091342ced6074d3bab0d79677 (patch)
treeb3276de041f5fdafc18aa0fcb27a372c9a50beb5 /hw/rvPhone/rvPhone.pro
parent90338a896c8c17e9e3a8e0cc3334bb6a8db85720 (diff)
stereo audio out; lvds display; LSM9DS1 added
Diffstat (limited to 'hw/rvPhone/rvPhone.pro')
-rw-r--r--hw/rvPhone/rvPhone.pro230
1 files changed, 217 insertions, 13 deletions
diff --git a/hw/rvPhone/rvPhone.pro b/hw/rvPhone/rvPhone.pro
index d0e8788..6ff2985 100644
--- a/hw/rvPhone/rvPhone.pro
+++ b/hw/rvPhone/rvPhone.pro
@@ -1,4 +1,4 @@
-update=Wednesday, August 05, 2020 at 12:24:50 AM
+update=Friday, December 04, 2020 at 01:18:44 AM
version=1
last_client=kicad
[cvpcb]
@@ -6,19 +6,19 @@ version=1
NetIExt=net
[general]
version=1
+[eeschema]
+version=1
+LibDir=
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
-NetFmtName=
-SpiceForceRefPrefix=0
-SpiceUseNetNumbers=0
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
LabSize=60
-[eeschema]
-version=1
-LibDir=
+ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
@@ -64,15 +64,219 @@ OthersTextUpright=1
SolderMaskClearance=0.045
SolderMaskMinWidth=0.11
SolderPasteClearance=0
-SolderPasteRatio=0
+SolderPasteRatio=-0
+[pcbnew/Layer.F.Cu]
+Name=F.Cu
+Type=0
+Enabled=1
[pcbnew/Layer.In1.Cu]
Name=GND
Type=1
+Enabled=1
[pcbnew/Layer.In2.Cu]
Name=PWR
Type=1
+Enabled=1
+[pcbnew/Layer.In3.Cu]
+Name=In3.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In4.Cu]
+Name=In4.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In5.Cu]
+Name=In5.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In6.Cu]
+Name=In6.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In7.Cu]
+Name=In7.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In8.Cu]
+Name=In8.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In9.Cu]
+Name=In9.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In10.Cu]
+Name=In10.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In11.Cu]
+Name=In11.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In12.Cu]
+Name=In12.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In13.Cu]
+Name=In13.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In14.Cu]
+Name=In14.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In15.Cu]
+Name=In15.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In16.Cu]
+Name=In16.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In17.Cu]
+Name=In17.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In18.Cu]
+Name=In18.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In19.Cu]
+Name=In19.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In20.Cu]
+Name=In20.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In21.Cu]
+Name=In21.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In22.Cu]
+Name=In22.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In23.Cu]
+Name=In23.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In24.Cu]
+Name=In24.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In25.Cu]
+Name=In25.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In26.Cu]
+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=B.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=0
[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.2
+TrackWidth=0.25
+ViaDiameter=0.6
+ViaDrill=0.3
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
[pcbnew/Netclasses/1]
+Name=AUDIO
+Clearance=0.2
+TrackWidth=0.2
+ViaDiameter=0.6
+ViaDrill=0.3
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[pcbnew/Netclasses/2]
+Name=BT81X
+Clearance=0.1524
+TrackWidth=0.1524
+ViaDiameter=0.508
+ViaDrill=0.254
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[pcbnew/Netclasses/3]
+Name=CTP
+Clearance=0.2
+TrackWidth=0.2
+ViaDiameter=0.6
+ViaDrill=0.3
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[pcbnew/Netclasses/4]
Name=DISPLAY
Clearance=0.1524
TrackWidth=0.1524
@@ -83,18 +287,18 @@ uViaDrill=0.1
dPairWidth=0.175
dPairGap=0.1524
dPairViaGap=0.25
-[pcbnew/Netclasses/2]
+[pcbnew/Netclasses/5]
Name=FE310
Clearance=0.1524
TrackWidth=0.1524
-ViaDiameter=0.6096
-ViaDrill=0.3048
+ViaDiameter=0.508
+ViaDrill=0.254
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
-[pcbnew/Netclasses/3]
+[pcbnew/Netclasses/6]
Name=FE310_L
Clearance=0.2
TrackWidth=0.2
@@ -105,7 +309,7 @@ uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
-[pcbnew/Netclasses/4]
+[pcbnew/Netclasses/7]
Name=MODEM_USB
Clearance=0.1524
TrackWidth=0.1524