summaryrefslogtreecommitdiff
path: root/hw/stencil/stencil.pro
diff options
context:
space:
mode:
authorUros Majstorovic <majstor@majstor.org>2026-05-05 00:05:12 +0200
committerUros Majstorovic <majstor@majstor.org>2026-05-05 00:05:12 +0200
commitc3c3e5f66fb24c584fefde1c0805e952d539ba9f (patch)
tree804f42ba8ca1cc9792b140dec693a801f1d8c9f3 /hw/stencil/stencil.pro
parentf4c5fb24507080506741b8ac2c6b027b401d02c8 (diff)
JLCPCB order W2025070409252353
Diffstat (limited to 'hw/stencil/stencil.pro')
-rw-r--r--hw/stencil/stencil.pro33
1 files changed, 33 insertions, 0 deletions
diff --git a/hw/stencil/stencil.pro b/hw/stencil/stencil.pro
new file mode 100644
index 0000000..152769c
--- /dev/null
+++ b/hw/stencil/stencil.pro
@@ -0,0 +1,33 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]