diff options
Diffstat (limited to 'fw/fe310/eos/dev')
34 files changed, 1149 insertions, 722 deletions
diff --git a/fw/fe310/eos/dev/aon.c b/fw/fe310/eos/dev/aon.c index 3d8aaf6..abf75d3 100644 --- a/fw/fe310/eos/dev/aon.c +++ b/fw/fe310/eos/dev/aon.c @@ -6,24 +6,90 @@ #include "aon.h" -#ifdef EOS_DEBUG -#include <stdio.h> -#endif - #define AON_EVE_REG 0 -#define AON_EVE_MASK 0x03 +#define AON_NET_REG 0 +#define AON_APP_REG 0 + +#define AON_EVE_PWM_MASK 0x000000FF +#define AON_EVE_PWR_MASK 0x00000300 +#define AON_EVE_LCD_MASK 0x00000400 +#define AON_NET_MASK 0x00000800 +#define AON_APP_MASK 0x00001000 + +void eos_aon_save4eve_pwm(uint8_t brightness) { + uint32_t reg; + + reg = eos_aon_get_reg(AON_EVE_REG); + reg &= ~AON_EVE_PWM_MASK; + reg |= brightness; + + eos_aon_set_reg(AON_EVE_REG, reg); +} + +uint8_t eos_aon_load4eve_pwm(void) { + uint32_t reg; + + reg = eos_aon_get_reg(AON_EVE_REG) & AON_EVE_PWM_MASK; + return reg; +} + +void eos_aon_save4eve_pwr(uint8_t power_state) { + uint32_t reg; + + reg = eos_aon_get_reg(AON_EVE_REG); + reg &= ~AON_EVE_PWR_MASK; + reg |= ((uint32_t)power_state << 8) & AON_EVE_PWR_MASK; + + eos_aon_set_reg(AON_EVE_REG, reg); +} -void eos_aon_save4eve(uint8_t power_state) { +uint8_t eos_aon_load4eve_pwr(void) { + uint32_t reg; + + reg = eos_aon_get_reg(AON_EVE_REG) & AON_EVE_PWR_MASK; + reg = reg >> 8; + return reg; +} + +void eos_aon_save4eve_lcd(int absent) { uint32_t reg; - power_state &= AON_EVE_MASK; reg = eos_aon_get_reg(AON_EVE_REG); - reg &= ~AON_EVE_MASK; - reg |= power_state; + reg &= ~AON_EVE_LCD_MASK; + if (absent) reg |= AON_EVE_LCD_MASK; + + eos_aon_set_reg(AON_EVE_REG, reg); +} + +int eos_aon_load4eve_lcd(void) { + return !!(eos_aon_get_reg(AON_EVE_REG) & AON_EVE_LCD_MASK); +} + +void eos_aon_save4net(int absent) { + uint32_t reg; + + reg = eos_aon_get_reg(AON_NET_REG); + reg &= ~AON_NET_MASK; + if (absent) reg |= AON_NET_MASK; - eos_aon_set_reg(0, power_state); + eos_aon_set_reg(AON_NET_REG, reg); } -uint8_t eos_aon_load4eve(void) { - return (eos_aon_get_reg(AON_EVE_REG) & AON_EVE_MASK); +int eos_aon_load4net(void) { + return !!(eos_aon_get_reg(AON_NET_REG) & AON_NET_MASK); } + +void eos_aon_save4app(int ctp_sel) { + uint32_t reg; + + reg = eos_aon_get_reg(AON_APP_REG); + reg &= ~AON_APP_MASK; + if (ctp_sel) reg |= AON_APP_MASK; + + eos_aon_set_reg(AON_APP_REG, reg); + +} + +int eos_aon_load4app(void) { + return !!(eos_aon_get_reg(AON_APP_REG) & AON_APP_MASK); +}
\ No newline at end of file diff --git a/fw/fe310/eos/dev/aon.h b/fw/fe310/eos/dev/aon.h index 22ba84a..eb3953c 100644 --- a/fw/fe310/eos/dev/aon.h +++ b/fw/fe310/eos/dev/aon.h @@ -1,4 +1,16 @@ #include <stdint.h> -void eos_aon_save4eve(uint8_t power_state); -uint8_t eos_aon_load4eve(void);
\ No newline at end of file +void eos_aon_save4eve_pwm(uint8_t brightness); +uint8_t eos_aon_load4eve_pwm(void); + +void eos_aon_save4eve_pwr(uint8_t power_state); +uint8_t eos_aon_load4eve_pwr(void); + +void eos_aon_save4eve_lcd(int absent); +int eos_aon_load4eve_lcd(void); + +void eos_aon_save4net(int absent); +int eos_aon_load4net(void); + +void eos_aon_save4app(int ctp_sel); +int eos_aon_load4app(void);
\ No newline at end of file diff --git a/fw/fe310/eos/dev/app.c b/fw/fe310/eos/dev/app.c index 3c215f4..4c6b7cd 100644 --- a/fw/fe310/eos/dev/app.c +++ b/fw/fe310/eos/dev/app.c @@ -2,13 +2,21 @@ #include <stdint.h> #include "eos.h" +#include "log.h" +#include "eve/eve.h" +#include "eve/eve_touch_engine.h" + +#include "egpio.h" +#include "egpio_priv.h" +#include "eve.h" + +#include "aon.h" +#include "ctp.h" +#include "lcd.h" #include "hpamp.h" -#include "app.h" -#ifdef EOS_DEBUG -#include <stdio.h> -#endif +#include "app.h" void eos_app_hp_change(int hp_det) { if (hp_det) { @@ -16,10 +24,91 @@ void eos_app_hp_change(int hp_det) { rv = eos_hpamp_init(); if (rv) { -#ifdef EOS_DEBUG - printf("I2S HP CHANGE: PCM1770 INIT ERR:%d\n", rv); -#endif + EOS_LOG(EOS_LOG_ERR, "I2S HP CHANGE: PCM1770 INIT ERR:%d\n", rv); return; } } } + +int eos_app_give(void) { + int rv, _rv; + + if (!eos_egpio_get_val(EGPIO_PIN_DISP_SEL)) return EOS_ERR; + + eos_aon_save4app(eos_egpio_get_val(EGPIO_PIN_CTP_SEL)); + + rv = eos_egpio_intr_disable(); + if (rv) return rv; + + rv = eve_select(); + if (rv) goto app_give_err_select; + + _eos_eve_sleep(); + + rv = eos_lcd_give(); + if (rv) goto app_give_err; + + rv = eos_egpio_set_val(EGPIO_PIN_CTP_SEL, 0); + if (rv) goto app_give_err; + + rv = eos_egpio_set_val(EGPIO_PIN_DISP_SEL, 0); + if (rv) goto app_give_err; + + eve_pwr_sleep(); + +app_give_err: + if (rv) _eos_eve_wake(); + eve_deselect(); + +app_give_err_select: + _rv = eos_egpio_intr_set(); + if (!rv && _rv) return _rv; + + return rv; +} + +int eos_app_take(void) { + int rv, _rv, ctp_sel; + + if (eos_egpio_get_val(EGPIO_PIN_DISP_SEL)) return EOS_ERR; + + ctp_sel = eos_aon_load4app(); + + rv = eos_egpio_intr_disable(); + if (rv) return rv; + + rv = eve_select(); + if (rv) goto app_take_err_select; + + eve_pwr_wake(); + + rv = eos_egpio_set_val(EGPIO_PIN_DISP_SEL, 1); + if (rv) goto app_take_err; + + rv = eos_egpio_set_val(EGPIO_PIN_CTP_SEL, ctp_sel); + if (rv) goto app_take_err; + + if (!ctp_sel) { + eve_touch_reset_engine(); + } + + rv = eos_lcd_take(); + if (rv) goto app_take_err; + + _eos_eve_wake(); + +app_take_err: + if (rv) eve_pwr_sleep(); + eve_deselect(); + + if (!rv && ctp_sel) { + _rv = _eos_ctp_reset(); + if (_rv) rv = _rv; + } + +app_take_err_select: + _rv = eos_egpio_intr_set(); + if (!rv && _rv) return _rv; + + return rv; +} diff --git a/fw/fe310/eos/dev/app.h b/fw/fe310/eos/dev/app.h index 4ee2e8d..e88ba20 100644 --- a/fw/fe310/eos/dev/app.h +++ b/fw/fe310/eos/dev/app.h @@ -1,3 +1,5 @@ #include <stdint.h> -void eos_app_hp_change(int hp_det);
\ No newline at end of file +void eos_app_hp_change(int hp_det); +int eos_app_give(void); +int eos_app_take(void);
\ No newline at end of file diff --git a/fw/fe310/eos/dev/batt.c b/fw/fe310/eos/dev/batt.c index 6f1eb97..45e6af0 100644 --- a/fw/fe310/eos/dev/batt.c +++ b/fw/fe310/eos/dev/batt.c @@ -2,14 +2,12 @@ #include <stdint.h> #include "eos.h" +#include "log.h" + #include "soc/pwr.h" #include "drv/bq25895.h" -#ifdef EOS_DEBUG -#include <stdio.h> -#endif - int eos_batt_init(void) { uint8_t wakeup_cause; int rst, rv; @@ -31,10 +29,10 @@ int eos_batt_init(void) { if (rv) return rv; #ifdef EOS_DEBUG - printf("BQ25895:\n"); + EOS_LOG(EOS_LOG_INFO, "BQ25895:\n"); for (i=0; i<0x15; i++) { rv = bq25895_reg_read(i, &data); - if (!rv) printf(" REG%.2X: %.2X\n", i, data); + if (!rv) EOS_LOG(EOS_LOG_INFO, " REG%.2X: %.2X\n", i, data); } #endif diff --git a/fw/fe310/eos/dev/cam.h b/fw/fe310/eos/dev/cam.h index 5153464..b0e1368 100644 --- a/fw/fe310/eos/dev/cam.h +++ b/fw/fe310/eos/dev/cam.h @@ -2,6 +2,9 @@ #include "drv/ov2640.h" #include "drv/arducam.h" +#include "egpio.h" +#include "egpio_priv.h" + #define eos_cam_init ov2640_init #define eos_cam_set_pixfmt ov2640_set_pixfmt #define eos_cam_set_framesize ov2640_set_pixfmt @@ -12,3 +15,6 @@ #define eos_cam_fbuf_size arducam_fbuf_size #define eos_cam_fbuf_read arducam_fbuf_read #define eos_cam_fbuf_done arducam_fbuf_done + +#define eos_cam_en() eos_egpio_set_val(EGPIO_PIN_CAM_EN, 1) +#define eos_cam_dis() eos_egpio_set_val(EGPIO_PIN_CAM_EN, 0) diff --git a/fw/fe310/eos/dev/ctp.c b/fw/fe310/eos/dev/ctp.c index fcc3c68..e58f929 100644 --- a/fw/fe310/eos/dev/ctp.c +++ b/fw/fe310/eos/dev/ctp.c @@ -10,17 +10,13 @@ #include "eve/eve_touch_engine.h" #include "egpio.h" +#include "egpio_priv.h" #include "eve.h" -#include "pwr.h" #include "drv/fxl6408.h" #include "drv/gt911.h" #include "ctp.h" -#ifdef EOS_DEBUG -#include <stdio.h> -#endif - int eos_ctp_init(void) { uint8_t wakeup_cause; int rv, rst; @@ -36,7 +32,15 @@ int eos_ctp_init(void) { return rv; } +int _eos_ctp_reset(void) { + if (eos_i2s_running() || !eos_egpio_get_val(EGPIO_PIN_CTP_SEL)) return EOS_ERR_BUSY; + + gt911_reset(); + return EOS_OK; +} + int eos_ctp_reset(void) { + uint8_t status = 0; int rv; if (eos_i2s_running() || !eos_egpio_get_val(EGPIO_PIN_DISP_SEL) || !eos_egpio_get_val(EGPIO_PIN_CTP_SEL)) return EOS_ERR_BUSY; @@ -52,10 +56,17 @@ int eos_ctp_reset(void) { return EOS_OK; } +int _eos_ctp_sleep(void) { + if (eos_i2s_running() || !eos_egpio_get_val(EGPIO_PIN_CTP_SEL)) return EOS_ERR_BUSY; + + return gt911_sleep(); +} + int eos_ctp_sleep(void) { int rv; if (eos_i2s_running() || !eos_egpio_get_val(EGPIO_PIN_DISP_SEL) || !eos_egpio_get_val(EGPIO_PIN_CTP_SEL)) return EOS_ERR_BUSY; + if (!gt911_running()) return EOS_ERR; rv = eos_egpio_intr_disable(); if (rv) return rv; @@ -69,10 +80,18 @@ int eos_ctp_sleep(void) { return EOS_OK; } +int _eos_ctp_wake(void) { + if (eos_i2s_running() || !eos_egpio_get_val(EGPIO_PIN_CTP_SEL)) return EOS_ERR_BUSY; + + gt911_wake(); + return EOS_OK; +} + int eos_ctp_wake(void) { int rv; if (eos_i2s_running() || !eos_egpio_get_val(EGPIO_PIN_DISP_SEL) || !eos_egpio_get_val(EGPIO_PIN_CTP_SEL)) return EOS_ERR_BUSY; + if (gt911_running()) return EOS_ERR; rv = eos_egpio_fxl_set_pin(EGPIO_PIN_CTP_INT, FXL6408_REG_PULL_DIR, 1); if (rv) return rv; @@ -86,7 +105,7 @@ int eos_ctp_wake(void) { } int eos_ctp_give(void) { - int rv; + int rv, _rv; if (!eos_egpio_get_val(EGPIO_PIN_DISP_SEL)) return EOS_ERR_BUSY; if (!eos_egpio_get_val(EGPIO_PIN_CTP_SEL)) return EOS_ERR; @@ -94,23 +113,24 @@ int eos_ctp_give(void) { rv = eos_egpio_intr_disable(); if (rv) return rv; - rv = eve_select(); - if (rv) return rv; - rv = eos_egpio_set_val(EGPIO_PIN_CTP_SEL, 0); - if (rv) return rv; + if (rv) goto ctp_give_err; + + rv = eve_select(); + if (rv) goto ctp_give_err; eve_touch_set_engine(EVE_TOUCH_ENGINE_GOODIX); eve_deselect(); - rv = eos_egpio_intr_set(); - if (rv) return rv; +ctp_give_err: + _rv = eos_egpio_intr_set(); + if (!rv && _rv) return _rv; - return EOS_OK; + return rv; } int eos_ctp_take(void) { - int rv; + int rv, _rv; if (eos_i2s_running() || !eos_egpio_get_val(EGPIO_PIN_DISP_SEL)) return EOS_ERR_BUSY; if (eos_egpio_get_val(EGPIO_PIN_CTP_SEL)) return EOS_ERR; @@ -119,26 +139,26 @@ int eos_ctp_take(void) { if (rv) return rv; rv = eve_select(); - if (rv) return rv; + if (rv) goto ctp_take_err; eve_touch_set_engine(EVE_TOUCH_ENGINE_HOST); eve_deselect(); rv = eos_egpio_set_val(EGPIO_PIN_CTP_SEL, 1); - if (rv) return rv; + if (rv) goto ctp_take_err; gt911_reset(); - rv = eos_egpio_intr_set(); - if (rv) return rv; +ctp_take_err: + _rv = eos_egpio_intr_set(); + if (!rv && _rv) return _rv; - return EOS_OK; + return rv; } int eos_ctp_handle_intr(void) { uint8_t status; uint8_t points[GT911_SIZE_PBUF * GT911_MAX_POINTS]; - static int clear_tag0 = 0; int i, num_points; int rv; uint32_t start; @@ -150,11 +170,11 @@ int eos_ctp_handle_intr(void) { num_points = status & 0xf; if (num_points > 5) { rv = EOS_ERR; - goto handle_intr_fin; + goto handle_intr_fin1; } rv = eve_select(); - if (rv) goto handle_intr_fin; + if (rv) goto handle_intr_fin1; start = eos_get_tick(); while (!eve_touch_ehost_ready()) { @@ -163,20 +183,14 @@ int eos_ctp_handle_intr(void) { if (eos_tdelta_ms(start) > EVE_CMD_EXEC_TO) { rv = EOS_ERR_TIMEOUT; - eve_deselect(); - goto handle_intr_fin; + goto handle_intr_fin0; } if (num_points) { - if (clear_tag0) { - eve_touch_clear_tag0(); - clear_tag0 = 0; - } rv = gt911_get_points(num_points, points); if (rv) { rv = EOS_ERR; - eve_deselect(); - goto handle_intr_fin; + goto handle_intr_fin0; } for (i=0; i<num_points; i++) { @@ -193,20 +207,14 @@ int eos_ctp_handle_intr(void) { } } else { eve_touch_ehost_enter(0, 0x8000, 0x8000); - clear_tag0 = 1; } eve_touch_ehost_end(); +handle_intr_fin0: eve_deselect(); - -handle_intr_fin: +handle_intr_fin1: gt911_set_status(0); - if (rv) { -#ifdef EOS_DEBUG - printf("CTP HANDLE INTR ERR:%d\n", rv); -#endif - return rv; - } + if (rv) return rv; - return 1; + return status; } diff --git a/fw/fe310/eos/dev/ctp.h b/fw/fe310/eos/dev/ctp.h index 72a0a75..c17f1e4 100644 --- a/fw/fe310/eos/dev/ctp.h +++ b/fw/fe310/eos/dev/ctp.h @@ -1,7 +1,14 @@ #include <stdint.h> int eos_ctp_init(void); + +int _eos_ctp_reset(void); int eos_ctp_reset(void); + +int _eos_ctp_sleep(void); int eos_ctp_sleep(void); + +int _eos_ctp_wake(void); int eos_ctp_wake(void); + int eos_ctp_handle_intr(void);
\ No newline at end of file diff --git a/fw/fe310/eos/dev/drv/arducam.c b/fw/fe310/eos/dev/drv/arducam.c index a50830a..8ac3823 100644 --- a/fw/fe310/eos/dev/drv/arducam.c +++ b/fw/fe310/eos/dev/drv/arducam.c @@ -36,21 +36,21 @@ #define ARDUCAM_VAL_GPIO_PWREN 0x04 static uint8_t reg_read(uint8_t addr) { - uint8_t ret; + uint8_t rv; - drv_spi_cs_set(); + drv_spi_set_cs(); drv_spi_xchg8(addr, 0); - ret = drv_spi_xchg8(0, 0); - drv_spi_cs_clear(); + rv = drv_spi_xchg8(0, 0); + drv_spi_clear_cs(); - return ret; + return rv; } static void reg_write(uint8_t addr, uint8_t val) { - drv_spi_cs_set(); + drv_spi_set_cs(); drv_spi_xchg8(addr | 0x80, 0); drv_spi_xchg8(val, 0); - drv_spi_cs_clear(); + drv_spi_clear_cs(); } void arducam_capture(void) { @@ -70,25 +70,25 @@ void arducam_capture_wait(void) { } uint32_t arducam_fbuf_size(void) { - uint32_t ret; + uint32_t rv; - ret = reg_read(ARDUCAM_REG_FIFO_SIZE1); - ret |= reg_read(ARDUCAM_REG_FIFO_SIZE2) << 8; - ret |= (reg_read(ARDUCAM_REG_FIFO_SIZE3) & 0x7f) << 16; - return ret; + rv = reg_read(ARDUCAM_REG_FIFO_SIZE1); + rv |= reg_read(ARDUCAM_REG_FIFO_SIZE2) << 8; + rv |= (reg_read(ARDUCAM_REG_FIFO_SIZE3) & 0x7f) << 16; + return rv; } void arducam_fbuf_read(uint8_t *buffer, uint16_t sz, int first) { int i; - drv_spi_cs_set(); + drv_spi_set_cs(); drv_spi_xchg8(ARDUCAM_REG_READ_BURST, 0); if (first) drv_spi_xchg8(0, 0); for (i=0; i<sz; i++) { buffer[i] = drv_spi_xchg8(0, 0); } - drv_spi_cs_clear(); + drv_spi_clear_cs(); } void arducam_fbuf_done(void) { diff --git a/fw/fe310/eos/dev/drv/gt911.c b/fw/fe310/eos/dev/drv/gt911.c index cd71d9a..8eb4358 100644 --- a/fw/fe310/eos/dev/drv/gt911.c +++ b/fw/fe310/eos/dev/drv/gt911.c @@ -124,6 +124,10 @@ void gt911_wake(void) { drv_gpio_set(GPIO_INPUT_EN, GT911_PIN_INT); } +int gt911_running(void) { + return drv_gpio_get(GPIO_INPUT_EN, GT911_PIN_INT); +} + int gt911_cfg_read(uint8_t *cfg_buf) { int rv; @@ -148,20 +152,20 @@ int gt911_cfg_print(void) { rv = gt911_cfg_read(cfg_buf); if (rv) return rv; - printf("GT911 CFG:\n"); + DRV_LOG(DRV_LOG_INFO, "GT911 CFG:\n"); for (i=0; i<GT911_SIZE_CFG-2; i++) { - printf("%.2X", cfg_buf[i]); + DRV_LOG(DRV_LOG_INFO, "%.2X", cfg_buf[i]); if (i % 8 == 7) { - printf("\n"); + DRV_LOG(DRV_LOG_INFO, "\n"); } else { - printf(" "); + DRV_LOG(DRV_LOG_INFO, " "); } } rv = gt911_fw_ver(cfg_buf); if (rv) return rv; - printf("GT911 FW VER:%.2X%.2X\n", cfg_buf[1], cfg_buf[0]); + DRV_LOG(DRV_LOG_INFO, "GT911 FW VER:%.2X%.2X\n", cfg_buf[1], cfg_buf[0]); return DRV_OK; } diff --git a/fw/fe310/eos/dev/drv/gt911.h b/fw/fe310/eos/dev/drv/gt911.h index 9db6981..61a6593 100644 --- a/fw/fe310/eos/dev/drv/gt911.h +++ b/fw/fe310/eos/dev/drv/gt911.h @@ -10,6 +10,7 @@ void gt911_reset(void); int gt911_sleep(void); void gt911_wake(void); +int gt911_running(void); int gt911_cfg_read(uint8_t *cfg_buf); int gt911_cfg_write(uint8_t *cfg_buf); diff --git a/fw/fe310/eos/dev/drv/ili9806e.c b/fw/fe310/eos/dev/drv/ili9806e.c index 45aabb7..b57a14c 100644 --- a/fw/fe310/eos/dev/drv/ili9806e.c +++ b/fw/fe310/eos/dev/drv/ili9806e.c @@ -5,15 +5,11 @@ #include "platform.h" #include "ili9806e.h" -#ifdef DRV_DEBUG -#include <stdio.h> -#endif - int ili9806e_init(void) { int rv; uint8_t chip_id[3]; - drv_spi_cs_set(); + drv_spi_set_cs(); /* LCD Setting */ drv_spi9bit_write(0, 0xFF); // change to Page 1 CMD @@ -38,15 +34,13 @@ int ili9806e_init(void) { drv_spi9bit_write(0, 0x02); drv_spi9bit_read(&chip_id[2]); -#ifdef DRV_DEBUG - printf("LCD CHIP ID: %.2x%.2x%.2x\n", chip_id[0], chip_id[1], chip_id[2]); -#endif + DRV_LOG(DRV_LOG_INFO, "LCD CHIP ID: %.2x%.2x%.2x\n", chip_id[0], chip_id[1], chip_id[2]); drv_spi9bit_write(0, 0xFE); // disable read drv_spi9bit_write(1, 0x00); if (memcmp(chip_id, "\x98\x06\x04", sizeof(chip_id))) { - drv_spi_cs_clear(); + drv_spi_clear_cs(); return DRV_ERR_NOTFOUND; } @@ -404,28 +398,28 @@ int ili9806e_init(void) { drv_spi9bit_write(0, 0x29); drv_sleep(25); - drv_spi_cs_clear(); + drv_spi_clear_cs(); return DRV_OK; } void ili9806e_sleep(void) { - drv_spi_cs_set(); + drv_spi_set_cs(); drv_spi9bit_write(0, 0x28); drv_sleep(10); drv_spi9bit_write(0, 0x10); - drv_spi_cs_clear(); + drv_spi_clear_cs(); } void ili9806e_wake(void) { - drv_spi_cs_set(); + drv_spi_set_cs(); drv_spi9bit_write(0, 0x11); drv_sleep(120); drv_spi9bit_write(0, 0x29); - drv_spi_cs_clear(); + drv_spi_clear_cs(); } diff --git a/fw/fe310/eos/dev/drv/pcm1770.c b/fw/fe310/eos/dev/drv/pcm1770.c index c617ae9..eec7bd0 100644 --- a/fw/fe310/eos/dev/drv/pcm1770.c +++ b/fw/fe310/eos/dev/drv/pcm1770.c @@ -5,8 +5,8 @@ #include "pcm1770.h" void pcm1770_reg_write(uint8_t addr, uint8_t val) { - drv_spi_cs_set(); + drv_spi_set_cs(); drv_spi_xchg8(addr, 0); drv_spi_xchg8(val, 0); - drv_spi_cs_clear(); + drv_spi_clear_cs(); } diff --git a/fw/fe310/eos/dev/drv/platform.h b/fw/fe310/eos/dev/drv/platform.h index d1f7248..a2405d5 100644 --- a/fw/fe310/eos/dev/drv/platform.h +++ b/fw/fe310/eos/dev/drv/platform.h @@ -1,6 +1,7 @@ #include "board.h" #include "eos.h" +#include "log.h" #include "soc/timer.h" #include "soc/i2c.h" #include "soc/spi.h" @@ -16,17 +17,18 @@ #define DRV_ERR EOS_ERR #define DRV_ERR_NOTFOUND EOS_ERR_NOTFOUND -/* should define theese for non-EOS platforms: -#define GPIO_INPUT_EN -#define GPIO_OUTPUT_EN -#define GPIO_OUTPUT_VAL -*/ +#define DRV_LOG_DEBUG EOS_LOG_DEBUG +#define DRV_LOG_INFO EOS_LOG_INFO +#define DRV_LOG_ERR EOS_LOG_ERR +#define DRV_LOG_NONE EOS_LOG_NONE +#define DRV_LOG_LEVEL EOS_LOG_LEVEL +#define DRV_LOG(l, ...) EOS_LOG(l, __VA_ARGS__) #define GT911_PIN_INT CTP_PIN_INT #define GT911_PIN_RST CTP_PIN_RST -#define drv_spi_cs_set eos_spi_cs_set -#define drv_spi_cs_clear eos_spi_cs_clear +#define drv_spi_set_cs eos_spi_set_cs +#define drv_spi_clear_cs eos_spi_clear_cs #define drv_spi_xchg8 eos_spi_xchg8 #define drv_spi9bit_read eos_spi9bit_read #define drv_spi9bit_write eos_spi9bit_write @@ -38,5 +40,12 @@ #define drv_sleep eos_sleep +/* should define theese for non-EOS platforms: +#define GPIO_INPUT_EN +#define GPIO_OUTPUT_EN +#define GPIO_OUTPUT_VAL +*/ + +#define drv_gpio_get eos_gpio_get #define drv_gpio_set eos_gpio_set #define drv_gpio_clear eos_gpio_clear diff --git a/fw/fe310/eos/dev/drv/sdc_platform.h b/fw/fe310/eos/dev/drv/sdc_platform.h index 5d562c2..daf2670 100644 --- a/fw/fe310/eos/dev/drv/sdc_platform.h +++ b/fw/fe310/eos/dev/drv/sdc_platform.h @@ -1,19 +1,31 @@ /* included from sdcard.h - needs relative includes */ #include "../../eos.h" +#include "../../log.h" #include "../../soc/timer.h" #include "../../soc/spi.h" #include "../sdc_crypto.h" +#ifdef EOS_DEBUG +#define SDC_DEBUG +#endif + #define SDC_OK EOS_OK #define SDC_ERR EOS_ERR #define SDC_ERR_BUSY EOS_ERR_BUSY +#define SDC_LOG_DEBUG EOS_LOG_DEBUG +#define SDC_LOG_INFO EOS_LOG_INFO +#define SDC_LOG_ERR EOS_LOG_ERR +#define SDC_LOG_NONE EOS_LOG_NONE +#define SDC_LOG_LEVEL EOS_LOG_LEVEL +#define SDC_LOG(l, ...) EOS_LOG(l, __VA_ARGS__) + #define sdc_spi_xchg8 eos_spi_xchg8 #define sdc_spi_xchg16 eos_spi_xchg16 #define sdc_spi_xchg32 eos_spi_xchg32 -#define sdc_spi_cs_set eos_spi_cs_set -#define sdc_spi_cs_clear eos_spi_cs_clear +#define sdc_spi_set_cs eos_spi_set_cs +#define sdc_spi_clear_cs eos_spi_clear_cs #define sdc_sleep eos_sleep #define sdc_get_tick eos_get_tick #define sdc_tdelta_ms eos_tdelta_ms diff --git a/fw/fe310/eos/dev/drv/sdcard.c b/fw/fe310/eos/dev/drv/sdcard.c index 96b01ae..7d21b3d 100644 --- a/fw/fe310/eos/dev/drv/sdcard.c +++ b/fw/fe310/eos/dev/drv/sdcard.c @@ -126,18 +126,18 @@ static void sdc_buf_recv(unsigned char *buffer, uint16_t len) { } static void sdc_select(void) { - sdc_spi_cs_set(); + sdc_spi_set_cs(); sdc_spi_xchg8(0xff, 0); } static void sdc_deselect(void) { - sdc_spi_cs_clear(); + sdc_spi_clear_cs(); sdc_spi_xchg8(0xff, 0); } static int sdc_xchg_cmd(uint8_t cmd, uint32_t arg, uint8_t flags) { int i; - uint8_t ret; + uint8_t rv; uint8_t crc = 0x7f; cmd |= 0x40; @@ -156,11 +156,11 @@ static int sdc_xchg_cmd(uint8_t cmd, uint32_t arg, uint8_t flags) { i = SDC_NCR; do { - ret = sdc_xchg8(0xff); - } while ((ret & 0x80) && --i); - if (ret & 0x80) return SDC_ERR_BUSY; + rv = sdc_xchg8(0xff); + } while ((rv & 0x80) && --i); + if (rv & 0x80) return SDC_ERR_BUSY; - return ret; + return rv; } static int sdc_ready(uint32_t timeout) { @@ -256,11 +256,12 @@ int sdc_init(uint32_t timeout) { uint32_t start; start = sdc_get_tick(); - sdc_sleep(5); - for (i=10; i--;) sdc_xchg8(0xff); /* 80 dummy cycles */ + do { + if (sdc_tdelta_ms(start) > timeout) return SDC_ERR_BUSY; + for (i=10; i--;) sdc_xchg8(0xff); /* 80 dummy cycles */ - rv = sdc_cmd(GO_IDLE_STATE, 0, SDC_CMD_FLAG_CRC, SDC_TIMEOUT_CMD); - if (rv != SDC_R1_IDLE_STATE) return SDC_RV2ERR(rv); + rv = sdc_cmd(GO_IDLE_STATE, 0, SDC_CMD_FLAG_CRC, SDC_TIMEOUT_CMD); + } while (rv != SDC_R1_IDLE_STATE); sdc_select(); rv = sdc_cmd(SEND_IF_COND, 0x1aa, SDC_CMD_FLAG_CRC | SDC_CMD_FLAG_NOCS, sdc_nto(start, timeout)); @@ -341,11 +342,11 @@ int sdc_init(uint32_t timeout) { if (rv) return rv; #ifdef SDC_DEBUG - printf("SDCARD CSD: "); + SDC_LOG(SDC_LOG_INFO, "SDCARD CSD: "); for (i=0; i<16; i++) { - printf("%.2x ", csd[i]); + SDC_LOG(SDC_LOG_INFO, "%.2x ", csd[i]); } - printf("\n"); + SDC_LOG(SDC_LOG_INFO, "\n"); #endif if (csd[10] & 0x40) _type |= SDC_CAP_ERASE_EN; } @@ -366,7 +367,7 @@ void sdc_clear(void) { sdc_type = SDC_TYPE_NONE; } -int sdc_get_sect_count(uint32_t timeout, uint32_t *sectors) { +int sdc_get_sect_count(uint32_t *sectors, uint32_t timeout) { int rv; uint8_t csd[16]; uint32_t start; @@ -393,7 +394,7 @@ int sdc_get_sect_count(uint32_t timeout, uint32_t *sectors) { return SDC_OK; } -int sdc_get_blk_size(uint32_t timeout, uint32_t *size) { +int sdc_get_blk_size(uint32_t *size, uint32_t timeout) { int rv; uint8_t rbl[64]; /* SD Status or CSD register */ uint32_t start; diff --git a/fw/fe310/eos/dev/drv/sdcard.h b/fw/fe310/eos/dev/drv/sdcard.h index 39891bb..b4da896 100644 --- a/fw/fe310/eos/dev/drv/sdcard.h +++ b/fw/fe310/eos/dev/drv/sdcard.h @@ -20,8 +20,8 @@ uint8_t sdc_get_type(void); uint8_t sdc_get_cap(void); void sdc_clear(void); -int sdc_get_sect_count(uint32_t timeout, uint32_t *sectors); -int sdc_get_blk_size(uint32_t timeout, uint32_t *size); +int sdc_get_sect_count(uint32_t *sectors, uint32_t timeout); +int sdc_get_blk_size(uint32_t *size, uint32_t timeout); int sdc_sync(uint32_t timeout); int sdc_erase(uint32_t blk_start, uint32_t blk_end, uint32_t timeout); int sdc_sect_read(uint32_t sect, unsigned int count, uint8_t *buffer); diff --git a/fw/fe310/eos/dev/egpio.c b/fw/fe310/eos/dev/egpio.c index 7358082..076986a 100644 --- a/fw/fe310/eos/dev/egpio.c +++ b/fw/fe310/eos/dev/egpio.c @@ -6,6 +6,8 @@ #include "board.h" #include "eos.h" +#include "log.h" + #include "event.h" #include "soc/interrupt.h" @@ -18,24 +20,31 @@ #include "sdcard.h" #include "ctp.h" #include "eve.h" + #include "app.h" #include "drv/fxl6408.h" #include "egpio.h" +#include "egpio_priv.h" /* FXL chip only */ -static const uint8_t egpio_switch[2] = { - EGPIO_BIT_SDCARD_DET | EGPIO_BIT_BTN_WAKE, +static const uint8_t egpio_switch[EGPIO_MAX_FXL_CHIP] = { + EGPIO_BIT_SDCARD_NDET | EGPIO_BIT_BTN_WAKE, EGPIO_BIT_MIC_MUTE | EGPIO_BIT_HP_NDET, }; static uint8_t egpio_pinval[EGPIO_MAX_CHIP]; +static uint8_t egpio_intmask[EGPIO_MAX_FXL_CHIP]; static uint8_t egpio_alt_pin; static uint32_t wake_start; static eos_egpio_intr_handler_t egpio_intr_handler; static eos_egpio_ext_handler_t egpio_ext_handler; +static int egpio_fxl_set_mask(uint8_t chip_id, uint8_t mask); +static int egpio_set_val(uint8_t pin, int val); +static int egpio_get_val(uint8_t pin); + #define EGPIO_ALT_EVEAUDIO_DIS 0x01 #define EGPIO_ALT_LSGAIN_SEL 0x02 #define EGPIO_ALT_AUDIO_SEL 0x04 @@ -43,8 +52,8 @@ static eos_egpio_ext_handler_t egpio_ext_handler; #define BITSET(var, bit, val) { var = (val) ? (var | (bit)) : (var & ~(bit)); } #define PINSWITCH(STPIN, SETPIN) { \ int rv; \ - BITSET(egpio_alt_pin, pin2alt_bit(STPIN), _eos_egpio_get_val(STPIN)); \ - rv = _eos_egpio_set_val(SETPIN, !!(egpio_alt_pin & pin2alt_bit(SETPIN))); \ + BITSET(egpio_alt_pin, pin2alt_bit(STPIN), egpio_get_val(STPIN)); \ + rv = egpio_set_val(SETPIN, !!(egpio_alt_pin & pin2alt_bit(SETPIN))); \ if (rv) return rv; \ } @@ -65,20 +74,22 @@ static int handle_egpio_intr(uint8_t chip_id, uint8_t intr) { int rv; switch (chip_id) { - case 0: { + case EGPIO_CHIP_FXL0: { if (intr & EGPIO_BIT_BAT_INT) { uint8_t fault0, fault1; rv = eos_batt_read_fault(&fault0, &fault1); if (rv) return rv; - if (egpio_intr_handler) egpio_intr_handler(EGPIO_INT_TYPE_BAT, fault1, fault0); + if (egpio_intr_handler) egpio_intr_handler(EOS_EGPIO_INT_TYPE_BAT, fault1, fault0); } if (intr & EGPIO_BIT_CTP_INT) { - eos_ctp_handle_intr(); + rv = eos_ctp_handle_intr(); + if (rv < 0) return rv; } if (intr & EGPIO_BIT_EVE_INT) { - eos_eve_handle_intr(); + rv = eos_eve_handle_intr(); + if (rv < 0) return rv; } if (intr & EGPIO_BIT_BTN_WAKE) { int btn_wake, tdelta; @@ -89,27 +100,29 @@ static int handle_egpio_intr(uint8_t chip_id, uint8_t intr) { } else { tdelta = eos_tdelta_ms(wake_start); } - if (egpio_intr_handler) egpio_intr_handler(EGPIO_INT_TYPE_WAKE, btn_wake, btn_wake ? tdelta : 0); + if (egpio_intr_handler) egpio_intr_handler(EOS_EGPIO_INT_TYPE_WAKE, btn_wake, btn_wake ? tdelta : 0); } - if (intr & EGPIO_BIT_SDCARD_DET) { - int sdc_det = eos_egpio_get_val(EGPIO_PIN_SDCARD_DET); + if (intr & EGPIO_BIT_SDCARD_NDET) { + int sdc_det; - eos_sdc_insert(sdc_det); - if (egpio_intr_handler) egpio_intr_handler(EGPIO_INT_TYPE_SDCARD, sdc_det, 0); + sdc_det = !eos_egpio_get_val(EGPIO_PIN_SDCARD_NDET); + rv = eos_sdc_insert(sdc_det, 0); + if (rv) EOS_LOG(EOS_LOG_ERR, "SDC INSERT ERR:%d\n", rv); + if (egpio_intr_handler) egpio_intr_handler(EOS_EGPIO_INT_TYPE_SDCARD, sdc_det, rv); } break; } - case 1: { + case EGPIO_CHIP_FXL1: { if (intr & EGPIO_BIT_MIC_MUTE) { - if (egpio_intr_handler) egpio_intr_handler(EGPIO_INT_TYPE_MUTE, eos_egpio_get_val(EGPIO_PIN_MIC_MUTE), 0); + if (egpio_intr_handler) egpio_intr_handler(EOS_EGPIO_INT_TYPE_MUTE, eos_egpio_get_val(EGPIO_PIN_MIC_MUTE), 0); } if (intr & EGPIO_BIT_HP_NDET) { int hp_det, i2s_running, app_audio; hp_det = !eos_egpio_get_val(EGPIO_PIN_HP_NDET); i2s_running = eos_i2s_running(); - app_audio = !_eos_egpio_get_val(EGPIO_PIN_AUDIO_SEL); + app_audio = !egpio_get_val(EGPIO_PIN_AUDIO_SEL); if (i2s_running || app_audio) { if (i2s_running) { eos_i2s_hp_change(hp_det); @@ -125,7 +138,7 @@ static int handle_egpio_intr(uint8_t chip_id, uint8_t intr) { PINSWITCH(EGPIO_PIN_EVEAUDIO_DIS, EGPIO_PIN_LSGAIN_SEL); } } - if (egpio_intr_handler) egpio_intr_handler(EGPIO_INT_TYPE_HP, hp_det, 0); + if (egpio_intr_handler) egpio_intr_handler(EOS_EGPIO_INT_TYPE_HP, hp_det, 0); } break; } @@ -135,14 +148,18 @@ static int handle_egpio_intr(uint8_t chip_id, uint8_t intr) { } static int handle_egpio_evt(uint8_t chip_id) { - uint8_t intr_reg, def_reg; + uint8_t intr_reg, mask_reg; int rv; rv = fxl6408_reg_read(chip_id, FXL6408_REG_INT_STATE, &intr_reg); - if (rv) return rv;; - if (!intr_reg) return 0; + if (rv) return rv; + + intr_reg &= ~egpio_intmask[chip_id]; + if (!intr_reg) return EOS_OK; if (intr_reg & egpio_switch[chip_id]) { + uint8_t def_reg; + rv = fxl6408_reg_read(chip_id, FXL6408_REG_I_DEFAULT, &def_reg); if (rv) return rv; @@ -157,64 +174,63 @@ static int handle_egpio_evt(uint8_t chip_id) { rv = handle_egpio_intr(chip_id, intr_reg); if (rv) return rv; - return 1; + return EOS_OK; } -static void handle_evt(unsigned char type, unsigned char *buffer, uint16_t len) { - type &= ~EOS_EVT_MASK; - - switch (type) { - case EGPIO_ETYPE_INT: { - int rv; +static void handle_evt(unsigned char type, EOSMessage *msg, uint16_t len) { + int rv; - rv = handle_egpio_evt(0); - if (rv < 0) goto handle_evt_fin; + switch (type & ~EOS_EVT_MASK) { + case EOS_EGPIO_ETYPE_INT: { + rv = handle_egpio_evt(EGPIO_CHIP_FXL0); + if (rv) goto handle_evt_fin; if (GPIO_REG(GPIO_INPUT_VAL) & (1 << EGPIO_PIN_INT)) goto handle_evt_fin; - rv = handle_egpio_evt(1); - if (rv < 0) goto handle_evt_fin; + rv = handle_egpio_evt(EGPIO_CHIP_FXL1); + if (rv) goto handle_evt_fin; if (GPIO_REG(GPIO_INPUT_VAL) & (1 << EGPIO_PIN_INT)) goto handle_evt_fin; if (egpio_ext_handler) rv = egpio_ext_handler(); handle_evt_fin: - clear_csr(mstatus, MSTATUS_MIE); GPIO_REG(GPIO_LOW_IP) = (1 << EGPIO_PIN_INT); + clear_csr(mstatus, MSTATUS_MIE); GPIO_REG(GPIO_LOW_IE) |= (1 << EGPIO_PIN_INT); set_csr(mstatus, MSTATUS_MIE); + if (rv) EOS_LOG(EOS_LOG_ERR, "EGPIO HANDLE INTR ERR:%d\n", rv); break; } - case EGPIO_ETYPE_INT_CTP: - case EGPIO_ETYPE_INT_EVE: { + case EOS_EGPIO_ETYPE_INT_CTP: { if (eos_egpio_get_val(EGPIO_PIN_CTP_SEL)) { - eos_ctp_handle_intr(); + rv = eos_ctp_handle_intr(); } else { - eos_eve_handle_intr(); + rv = eos_eve_handle_intr(); } -handle_evt_eve_fin: + GPIO_REG(GPIO_LOW_IP) = (1 << CTP_PIN_INT); clear_csr(mstatus, MSTATUS_MIE); - GPIO_REG(GPIO_LOW_IP) = (1 << EVE_PIN_INT); - GPIO_REG(GPIO_LOW_IE) |= (1 << EVE_PIN_INT); + GPIO_REG(GPIO_LOW_IE) |= (1 << CTP_PIN_INT); set_csr(mstatus, MSTATUS_MIE); + if (rv < 0) EOS_LOG(EOS_LOG_ERR, "CTP/EVE HANDLE INTR ERR:%d\n", rv); break; } + + default: + eos_evtq_bad_handler(type, msg, len); + break; + } } static void handle_intr(void) { GPIO_REG(GPIO_LOW_IE) &= ~(1 << EGPIO_PIN_INT); - eos_evtq_push_isr(EOS_EVT_EGPIO | EGPIO_ETYPE_INT, NULL, 0); + eos_evtq_push_isr(EOS_EVT_EGPIO | EOS_EGPIO_ETYPE_INT, NULL, 0); } -static void handle_intr_eve(void) { - GPIO_REG(GPIO_LOW_IE) &= ~(1 << EVE_PIN_INT); - if (egpio_pinval[EGPIO_CHIP_FXL0] & EGPIO_PIN2BIT(EGPIO0_PIN_CTP_SEL)) { - eos_evtq_push_isr(EOS_EVT_EGPIO | EGPIO_ETYPE_INT_CTP, NULL, 0); - } else { - eos_evtq_push_isr(EOS_EVT_EGPIO | EGPIO_ETYPE_INT_EVE, NULL, 0); - } +static void handle_intr_ctp(void) { + GPIO_REG(GPIO_LOW_IE) &= ~(1 << CTP_PIN_INT); + eos_evtq_push_isr(EOS_EVT_EGPIO | EOS_EGPIO_ETYPE_INT_CTP, NULL, 0); } int eos_egpio_init(void) { @@ -224,83 +240,98 @@ int eos_egpio_init(void) { wakeup_cause = eos_pwr_wakeup_cause(); rst = (wakeup_cause == EOS_PWR_WAKE_RST); if (rst) { - rv = fxl6408_reg_read(0, FXL6408_REG_ID_CTRL, &data); + rv = fxl6408_reg_read(EGPIO_CHIP_FXL0, FXL6408_REG_ID_CTRL, &data); + if (rv) return rv; + rv = fxl6408_reg_read(EGPIO_CHIP_FXL1, FXL6408_REG_ID_CTRL, &data); + if (rv) return rv; + + rv = egpio_fxl_set_mask(EGPIO_CHIP_FXL0, 0xff); if (rv) return rv; - rv = fxl6408_reg_read(1, FXL6408_REG_ID_CTRL, &data); + rv = egpio_fxl_set_mask(EGPIO_CHIP_FXL1, 0xff); if (rv) return rv; - rv = fxl6408_reg_write(0, FXL6408_REG_INT_MASK, 0xff); + /* clear interrupts */ + rv = fxl6408_reg_read(EGPIO_CHIP_FXL0, FXL6408_REG_INT_STATE, &data); if (rv) return rv; - rv = fxl6408_reg_write(1, FXL6408_REG_INT_MASK, 0xff); + rv = fxl6408_reg_read(EGPIO_CHIP_FXL1, FXL6408_REG_INT_STATE, &data); if (rv) return rv; /* 1st chip */ data = EGPIO_BIT_CTP_SEL | EGPIO_BIT_EXP_IO0 | EGPIO_BIT_EXP_IO1; - rv = fxl6408_reg_write(0, FXL6408_REG_IO_DIR, data); + rv = fxl6408_reg_write(EGPIO_CHIP_FXL0, FXL6408_REG_IO_DIR, data); if (rv) return rv; data = EGPIO_BIT_CTP_SEL; - rv = fxl6408_reg_write(0, FXL6408_REG_O_STATE, data); + rv = fxl6408_reg_write(EGPIO_CHIP_FXL0, FXL6408_REG_O_STATE, data); if (rv) return rv; data = EGPIO_BIT_EXP_IO0 | EGPIO_BIT_EXP_IO1; - rv = fxl6408_reg_write(0, FXL6408_REG_O_HIZ, data); + rv = fxl6408_reg_write(EGPIO_CHIP_FXL0, FXL6408_REG_O_HIZ, data); if (rv) return rv; - data = EGPIO_BIT_EVE_INT | EGPIO_BIT_SDCARD_DET | EGPIO_BIT_BTN_WAKE | EGPIO_BIT_BAT_INT | EGPIO_BIT_CTP_INT; - rv = fxl6408_reg_write(0, FXL6408_REG_PULL_ENA, data); + data = EGPIO_BIT_EVE_INT | EGPIO_BIT_SDCARD_NDET | EGPIO_BIT_BTN_WAKE | EGPIO_BIT_BAT_INT | EGPIO_BIT_CTP_INT; + rv = fxl6408_reg_write(EGPIO_CHIP_FXL0, FXL6408_REG_PULL_ENA, data); if (rv) return rv; - data = EGPIO_BIT_EVE_INT | EGPIO_BIT_SDCARD_DET | EGPIO_BIT_BTN_WAKE | EGPIO_BIT_BAT_INT | EGPIO_BIT_CTP_INT; - rv = fxl6408_reg_write(0, FXL6408_REG_PULL_DIR, data); + data = EGPIO_BIT_EVE_INT | EGPIO_BIT_SDCARD_NDET | EGPIO_BIT_BTN_WAKE | EGPIO_BIT_BAT_INT | EGPIO_BIT_CTP_INT; + rv = fxl6408_reg_write(EGPIO_CHIP_FXL0, FXL6408_REG_PULL_DIR, data); if (rv) return rv; /* 2nd chip */ data = EGPIO_BIT_HPAMP_CS | EGPIO_BIT_AUDIO_SEL | EGPIO_BIT_USR0 | EGPIO_BIT_USR1 | EGPIO_BIT_USR2 | EGPIO_BIT_USR3; - rv = fxl6408_reg_write(1, FXL6408_REG_IO_DIR, data); + rv = fxl6408_reg_write(EGPIO_CHIP_FXL1, FXL6408_REG_IO_DIR, data); if (rv) return rv; data = EGPIO_BIT_HPAMP_CS | EGPIO_BIT_AUDIO_SEL; - rv = fxl6408_reg_write(1, FXL6408_REG_O_STATE, data); + rv = fxl6408_reg_write(EGPIO_CHIP_FXL1, FXL6408_REG_O_STATE, data); if (rv) return rv; data = EGPIO_BIT_USR0 | EGPIO_BIT_USR1 | EGPIO_BIT_USR2 | EGPIO_BIT_USR3; - rv = fxl6408_reg_write(1, FXL6408_REG_O_HIZ, data); + rv = fxl6408_reg_write(EGPIO_CHIP_FXL1, FXL6408_REG_O_HIZ, data); if (rv) return rv; data = 0; - rv = fxl6408_reg_write(1, FXL6408_REG_PULL_ENA, data); + rv = fxl6408_reg_write(EGPIO_CHIP_FXL1, FXL6408_REG_PULL_ENA, data); if (rv) return rv; data = 0; - rv = fxl6408_reg_write(1, FXL6408_REG_PULL_DIR, data); + rv = fxl6408_reg_write(EGPIO_CHIP_FXL1, FXL6408_REG_PULL_DIR, data); if (rv) return rv; + } else { + /* read interrupt mask */ + rv = fxl6408_reg_read(EGPIO_CHIP_FXL0, FXL6408_REG_INT_MASK, &data); + if (rv) return rv; + egpio_intmask[EGPIO_CHIP_FXL0] = data; + + rv = fxl6408_reg_read(EGPIO_CHIP_FXL1, FXL6408_REG_INT_MASK, &data); + if (rv) return rv; + egpio_intmask[EGPIO_CHIP_FXL1] = data; } - rv = fxl6408_reg_read(0, FXL6408_REG_I_STATE, &data); + rv = fxl6408_reg_read(EGPIO_CHIP_FXL0, FXL6408_REG_I_STATE, &data); if (rv) return rv; - data &= egpio_switch[0]; + data &= egpio_switch[EGPIO_CHIP_FXL0]; egpio_pinval[EGPIO_CHIP_FXL0] = data; data |= EGPIO_BIT_EVE_INT | EGPIO_BIT_BAT_INT | EGPIO_BIT_CTP_INT; - rv = fxl6408_reg_write(0, FXL6408_REG_I_DEFAULT, data); + rv = fxl6408_reg_write(EGPIO_CHIP_FXL0, FXL6408_REG_I_DEFAULT, data); if (rv) return rv; - rv = fxl6408_reg_read(0, FXL6408_REG_IO_DIR, &data_dir); + rv = fxl6408_reg_read(EGPIO_CHIP_FXL0, FXL6408_REG_IO_DIR, &data_dir); if (rv) return rv; - rv = fxl6408_reg_read(0, FXL6408_REG_O_STATE, &data); + rv = fxl6408_reg_read(EGPIO_CHIP_FXL0, FXL6408_REG_O_STATE, &data); if (rv) return rv; egpio_pinval[EGPIO_CHIP_FXL0] |= (data & data_dir); - rv = fxl6408_reg_read(1, FXL6408_REG_I_STATE, &data); + rv = fxl6408_reg_read(EGPIO_CHIP_FXL1, FXL6408_REG_I_STATE, &data); if (rv) return rv; - data &= egpio_switch[1]; + data &= egpio_switch[EGPIO_CHIP_FXL1]; egpio_pinval[EGPIO_CHIP_FXL1] = data; - rv = fxl6408_reg_write(1, FXL6408_REG_I_DEFAULT, data); + rv = fxl6408_reg_write(EGPIO_CHIP_FXL1, FXL6408_REG_I_DEFAULT, data); if (rv) return rv; - rv = fxl6408_reg_read(1, FXL6408_REG_IO_DIR, &data_dir); + rv = fxl6408_reg_read(EGPIO_CHIP_FXL1, FXL6408_REG_IO_DIR, &data_dir); if (rv) return rv; - rv = fxl6408_reg_read(1, FXL6408_REG_O_STATE, &data); + rv = fxl6408_reg_read(EGPIO_CHIP_FXL1, FXL6408_REG_O_STATE, &data); if (rv) return rv; egpio_pinval[EGPIO_CHIP_FXL1] |= (data & data_dir); @@ -313,31 +344,31 @@ int eos_egpio_run(void) { eos_evtq_set_handler(EOS_EVT_EGPIO, handle_evt); - GPIO_REG(GPIO_INPUT_EN) |= (1 << EGPIO_PIN_INT); - clear_csr(mstatus, MSTATUS_MIE); - GPIO_REG(GPIO_LOW_IE) |= (1 << EGPIO_PIN_INT); - set_csr(mstatus, MSTATUS_MIE); - eos_intr_set(INT_GPIO_BASE + EGPIO_PIN_INT, IRQ_PRIORITY_EGPIO, handle_intr); - - /* EVE_PIN_INT will be set in intr_set() below */ - eos_intr_set(INT_GPIO_BASE + EVE_PIN_INT, IRQ_PRIORITY_EVE, handle_intr_eve); - wakeup_cause = eos_pwr_wakeup_cause(); rst = (wakeup_cause == EOS_PWR_WAKE_RST); if (rst) { - /* turn on interrupts when all is configured */ - data = ~(EGPIO_BIT_SDCARD_DET | EGPIO_BIT_BTN_WAKE | EGPIO_BIT_BAT_INT); - rv = fxl6408_reg_write(0, FXL6408_REG_INT_MASK, data); + /* enable interrupts when all is configured */ + data = ~(EGPIO_BIT_SDCARD_NDET | EGPIO_BIT_BTN_WAKE | EGPIO_BIT_BAT_INT); + rv = egpio_fxl_set_mask(EGPIO_CHIP_FXL0, data); if (rv) return rv; data = ~(EGPIO_BIT_MIC_MUTE | EGPIO_BIT_HP_NDET); - rv = fxl6408_reg_write(1, FXL6408_REG_INT_MASK, data); + rv = egpio_fxl_set_mask(EGPIO_CHIP_FXL1, data); if (rv) return rv; } rv = eos_egpio_intr_set(); if (rv) return rv; + /* CTP_PIN_INT is configured in intr_set() above */ + eos_intr_set(INT_GPIO_BASE + CTP_PIN_INT, IRQ_PRIORITY_CTP, handle_intr_ctp); + + GPIO_REG(GPIO_INPUT_EN) |= (1 << EGPIO_PIN_INT); + clear_csr(mstatus, MSTATUS_MIE); + GPIO_REG(GPIO_LOW_IE) |= (1 << EGPIO_PIN_INT); + set_csr(mstatus, MSTATUS_MIE); + eos_intr_set(INT_GPIO_BASE + EGPIO_PIN_INT, IRQ_PRIORITY_EGPIO, handle_intr); + return EOS_OK; } @@ -346,33 +377,32 @@ void eos_egpio_eve_set(uint16_t gpio_reg) { if (gpio_reg & (1 << EVE_GPIO_DISP)) egpio_pinval[EGPIO_CHIP_EVE] |= EGPIO_PIN2BIT(EGPIO_PIN_DISP_SEL); } -int _eos_egpio_intr_set(int i2s_running, int app_disp) { - uint8_t data; +static int egpio_intr_set(int i2s_running, int app_disp) { + uint8_t mask; int rv; - rv = fxl6408_reg_read(0, FXL6408_REG_INT_MASK, &data); - if (rv) return rv; + mask = egpio_intmask[EGPIO_CHIP_FXL0]; + mask |= EGPIO_BIT_EVE_INT | EGPIO_BIT_CTP_INT; - data &= ~(EGPIO_BIT_EVE_INT | EGPIO_BIT_CTP_INT); - if (app_disp) { - data |= (EGPIO_BIT_EVE_INT | EGPIO_BIT_CTP_INT); - } else if (!i2s_running) { - if (eos_egpio_get_val(EGPIO_PIN_CTP_SEL)) { - data |= EGPIO_BIT_CTP_INT; + if (!app_disp) { + if (i2s_running) { + mask &= ~(EGPIO_BIT_EVE_INT | EGPIO_BIT_CTP_INT); + } else if (eos_egpio_get_val(EGPIO_PIN_CTP_SEL)) { + mask &= ~EGPIO_BIT_EVE_INT; } else { - data |= EGPIO_BIT_EVE_INT; + mask &= ~EGPIO_BIT_CTP_INT; } } - rv = fxl6408_reg_write(0, FXL6408_REG_INT_MASK, data); + rv = egpio_fxl_set_mask(EGPIO_CHIP_FXL0, mask); if (rv) return rv; - GPIO_REG(GPIO_INPUT_EN) |= (1 << EVE_PIN_INT); + GPIO_REG(GPIO_INPUT_EN) |= (1 << CTP_PIN_INT); clear_csr(mstatus, MSTATUS_MIE); if (app_disp || i2s_running) { - GPIO_REG(GPIO_LOW_IE) &= ~(1 << EVE_PIN_INT); + GPIO_REG(GPIO_LOW_IE) &= ~(1 << CTP_PIN_INT); } else { - GPIO_REG(GPIO_LOW_IE) |= (1 << EVE_PIN_INT); + GPIO_REG(GPIO_LOW_IE) |= (1 << CTP_PIN_INT); } set_csr(mstatus, MSTATUS_MIE); @@ -380,25 +410,23 @@ int _eos_egpio_intr_set(int i2s_running, int app_disp) { } int eos_egpio_intr_set(void) { - return _eos_egpio_intr_set(eos_i2s_running(), !eos_egpio_get_val(EGPIO_PIN_DISP_SEL)); + return egpio_intr_set(eos_i2s_running(), !eos_egpio_get_val(EGPIO_PIN_DISP_SEL)); } int eos_egpio_intr_disable(void) { - uint8_t data; + uint8_t mask; int rv; - rv = fxl6408_reg_read(0, FXL6408_REG_INT_MASK, &data); - if (rv) return rv; - - data |= (EGPIO_BIT_EVE_INT | EGPIO_BIT_CTP_INT); + mask = egpio_intmask[EGPIO_CHIP_FXL0]; + mask |= (EGPIO_BIT_EVE_INT | EGPIO_BIT_CTP_INT); - rv = fxl6408_reg_write(0, FXL6408_REG_INT_MASK, data); + rv = egpio_fxl_set_mask(EGPIO_CHIP_FXL0, mask); if (rv) return rv; clear_csr(mstatus, MSTATUS_MIE); - GPIO_REG(GPIO_LOW_IE) &= ~(1 << EVE_PIN_INT); + GPIO_REG(GPIO_LOW_IE) &= ~(1 << CTP_PIN_INT); set_csr(mstatus, MSTATUS_MIE); - GPIO_REG(GPIO_INPUT_EN) &= ~(1 << EVE_PIN_INT); + GPIO_REG(GPIO_INPUT_EN) &= ~(1 << CTP_PIN_INT); return EOS_OK; } @@ -435,7 +463,17 @@ int eos_egpio_fxl_set_pin(uint8_t reg, uint8_t pin, uint8_t val) { return EOS_OK; } -int _eos_egpio_get_val(uint8_t pin) { +static int egpio_fxl_set_mask(uint8_t chip_id, uint8_t mask) { + int rv; + + rv = fxl6408_reg_write(chip_id, FXL6408_REG_INT_MASK, mask); + if (rv) return rv; + + egpio_intmask[chip_id] = mask; + return EOS_OK; +} + +static int egpio_get_val(uint8_t pin) { uint8_t chip_id; chip_id = EGPIO_PIN2CHIP(pin); @@ -443,7 +481,7 @@ int _eos_egpio_get_val(uint8_t pin) { return !!(egpio_pinval[chip_id] & EGPIO_PIN2BIT(pin)); } -int _eos_egpio_set_val(uint8_t pin, int val) { +static int egpio_set_val(uint8_t pin, int val) { uint8_t chip_id; int rv; @@ -485,7 +523,7 @@ int eos_egpio_get_val(uint8_t pin) { case EGPIO_PIN_EVEAUDIO_DIS: case EGPIO_PIN_LSGAIN_SEL: { - int lspk_on = (eos_i2s_running() || !_eos_egpio_get_val(EGPIO_PIN_AUDIO_SEL)) && eos_egpio_get_val(EGPIO_PIN_HP_NDET); + int lspk_on = (eos_i2s_running() || !egpio_get_val(EGPIO_PIN_AUDIO_SEL)) && eos_egpio_get_val(EGPIO_PIN_HP_NDET); if ((pin == EGPIO_PIN_EVEAUDIO_DIS) && lspk_on) { return !!(egpio_alt_pin & pin2alt_bit(pin)); @@ -498,7 +536,7 @@ int eos_egpio_get_val(uint8_t pin) { } } - return _eos_egpio_get_val(pin); + return egpio_get_val(pin); } int eos_egpio_set_val(uint8_t pin, int val) { @@ -520,7 +558,7 @@ int eos_egpio_set_val(uint8_t pin, int val) { return EOS_OK; } - if ((val != _eos_egpio_get_val(EGPIO_PIN_AUDIO_SEL)) && eos_egpio_get_val(EGPIO_PIN_HP_NDET)) { + if ((val != egpio_get_val(EGPIO_PIN_AUDIO_SEL)) && eos_egpio_get_val(EGPIO_PIN_HP_NDET)) { if (val) { /* store LSGAIN_SEL pin and set EVEAUDIO_DIS pin */ PINSWITCH(EGPIO_PIN_LSGAIN_SEL, EGPIO_PIN_EVEAUDIO_DIS); @@ -534,7 +572,7 @@ int eos_egpio_set_val(uint8_t pin, int val) { case EGPIO_PIN_EVEAUDIO_DIS: case EGPIO_PIN_LSGAIN_SEL: { - int lspk_on = (eos_i2s_running() || !_eos_egpio_get_val(EGPIO_PIN_AUDIO_SEL)) && eos_egpio_get_val(EGPIO_PIN_HP_NDET); + int lspk_on = (eos_i2s_running() || !egpio_get_val(EGPIO_PIN_AUDIO_SEL)) && eos_egpio_get_val(EGPIO_PIN_HP_NDET); if ((pin == EGPIO_PIN_EVEAUDIO_DIS) && lspk_on) { BITSET(egpio_alt_pin, pin2alt_bit(pin), val); @@ -549,7 +587,7 @@ int eos_egpio_set_val(uint8_t pin, int val) { } } - rv = _eos_egpio_set_val(pin, val); + rv = egpio_set_val(pin, val); if (rv) return rv; return EOS_OK; @@ -559,13 +597,13 @@ int eos_egpio_i2s_start(void) { uint8_t data; int rv, audio_sel; - rv = _eos_egpio_intr_set(1, !eos_egpio_get_val(EGPIO_PIN_DISP_SEL)); + rv = egpio_intr_set(1, !eos_egpio_get_val(EGPIO_PIN_DISP_SEL)); if (rv) return rv; - audio_sel = _eos_egpio_get_val(EGPIO_PIN_AUDIO_SEL); + audio_sel = egpio_get_val(EGPIO_PIN_AUDIO_SEL); BITSET(egpio_alt_pin, pin2alt_bit(EGPIO_PIN_AUDIO_SEL), audio_sel); - rv = _eos_egpio_set_val(EGPIO_PIN_AUDIO_SEL, 1); + rv = egpio_set_val(EGPIO_PIN_AUDIO_SEL, 1); if (rv) return rv; if (!audio_sel && eos_egpio_get_val(EGPIO_PIN_HP_NDET)) { @@ -579,7 +617,7 @@ int eos_egpio_i2s_start(void) { int eos_egpio_i2s_stop(void) { int rv, audio_sel; - rv = _eos_egpio_intr_set(0, !eos_egpio_get_val(EGPIO_PIN_DISP_SEL)); + rv = egpio_intr_set(0, !eos_egpio_get_val(EGPIO_PIN_DISP_SEL)); if (rv) return rv; audio_sel = (egpio_alt_pin & pin2alt_bit(EGPIO_PIN_AUDIO_SEL)); @@ -588,7 +626,7 @@ int eos_egpio_i2s_stop(void) { PINSWITCH(EGPIO_PIN_LSGAIN_SEL, EGPIO_PIN_EVEAUDIO_DIS); } - rv = _eos_egpio_set_val(EGPIO_PIN_AUDIO_SEL, audio_sel); + rv = egpio_set_val(EGPIO_PIN_AUDIO_SEL, audio_sel); if (rv) return rv; return EOS_OK; diff --git a/fw/fe310/eos/dev/egpio.h b/fw/fe310/eos/dev/egpio.h index 7d20443..a916ed5 100644 --- a/fw/fe310/eos/dev/egpio.h +++ b/fw/fe310/eos/dev/egpio.h @@ -1,93 +1,13 @@ #include <stdint.h> -#define EGPIO_ETYPE_INT 1 -#define EGPIO_ETYPE_INT_CTP 2 -#define EGPIO_ETYPE_INT_EVE 3 +#define EOS_EGPIO_ETYPE_INT 1 +#define EOS_EGPIO_ETYPE_INT_CTP 2 /* EGPIO_PIN_CTP_SEL is on: CTP int; EGPIO_PIN_CTP_SEL is off: EVE int */ -#define EGPIO_INT_TYPE_BAT 1 -#define EGPIO_INT_TYPE_WAKE 2 -#define EGPIO_INT_TYPE_SDCARD 3 -#define EGPIO_INT_TYPE_MUTE 4 -#define EGPIO_INT_TYPE_HP 5 - -#define EGPIO_CHIP_FXL0 0x00 -#define EGPIO_CHIP_FXL1 0x01 -#define EGPIO_CHIP_EVE 0x02 - -#define EGPIO_MAX_CHIP 3 - -#define EGPIO_PIN_MASK 0x07 -#define EGPIO_PIN_MASK_CHIP 0x30 - -#define EGPIO_PIN2BIT(X) (1 << ((X) & EGPIO_PIN_MASK)) -#define EGPIO_PIN2CHIP(X) (((X) & EGPIO_PIN_MASK_CHIP) >> 4) -#define EGPIO_PIN(C,P) (((C) << 4) | (P)) - -#define EGPIO0_PIN_EVE_INT 0x00 /* EVE interrrupt */ -#define EGPIO0_PIN_SDCARD_DET 0x01 /* SD Card detect */ -#define EGPIO0_PIN_EXP_IO0 0x02 /* expansion io 0 */ -#define EGPIO0_PIN_EXP_IO1 0x03 /* expansion io 1 */ -#define EGPIO0_PIN_BTN_WAKE 0x04 /* wake button */ -#define EGPIO0_PIN_BAT_INT 0x05 /* battery charger IC inetrrupt */ -#define EGPIO0_PIN_CTP_SEL 0x06 /* switch CTP connection: EVE_DISP:1 and CTP_SEL:0 - connected to EVE chip, EVE_DISP:X and CTP_SEL:1 - connected to fe310 chip, EVE_DISP:0 and CTP_SEL:0 - connected to app module */ -#define EGPIO0_PIN_CTP_INT 0x07 /* CTP interrupt */ - -#define EGPIO1_PIN_MIC_MUTE 0x00 /* microphone disable */ -#define EGPIO1_PIN_HPAMP_CS 0x01 /* SPI chip select for headphone amplifier (pcm1770) */ -#define EGPIO1_PIN_AUDIO_SEL 0x02 /* switch audio connection: 0 - connected to app module, 1 - connected to fe310 chip (only when i2s is off) */ -#define EGPIO1_PIN_HP_NDET 0x03 /* headphone detect: 0 - inserted, 1 - not inserted */ -#define EGPIO1_PIN_USR0 0x04 /* user IO */ -#define EGPIO1_PIN_USR1 0x05 -#define EGPIO1_PIN_USR2 0x06 -#define EGPIO1_PIN_USR3 0x07 - -#define EGPIOE_PIN_DISP 0x07 /* EVE DISP GPIO */ - -#define EGPIO_PIN_ALT 0x08 - -#define EGPIO_PIN_EVE_INT EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_EVE_INT) -#define EGPIO_PIN_SDCARD_DET EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_SDCARD_DET) -#define EGPIO_PIN_EXP_IO0 EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_EXP_IO0) -#define EGPIO_PIN_EXP_IO1 EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_EXP_IO1) -#define EGPIO_PIN_BTN_WAKE EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_BTN_WAKE) -#define EGPIO_PIN_BAT_INT EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_BAT_INT) -#define EGPIO_PIN_CTP_SEL EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_CTP_SEL) -#define EGPIO_PIN_CTP_INT EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_CTP_INT) - -#define EGPIO_PIN_MIC_MUTE EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_MIC_MUTE) -#define EGPIO_PIN_HPAMP_CS EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_HPAMP_CS) -#define EGPIO_PIN_AUDIO_SEL EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_AUDIO_SEL) -#define EGPIO_PIN_HP_NDET EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_HP_NDET) -#define EGPIO_PIN_USR0 EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_USR0) -#define EGPIO_PIN_USR1 EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_USR1) -#define EGPIO_PIN_USR2 EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_USR2) -#define EGPIO_PIN_USR3 EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_USR3) - -/* EVE pins defined in eve.h */ -#define EGPIO_PIN_USR4 EGPIO_PIN(EGPIO_CHIP_EVE, EVE_GPIO_USR) -#define EGPIO_PIN_EVEAUDIO_DIS EGPIO_PIN(EGPIO_CHIP_EVE, EVE_GPIO_EVEAUDIO_DIS) -#define EGPIO_PIN_LSGAIN_SEL EGPIO_PIN(EGPIO_CHIP_EVE, EVE_GPIO_LSGAIN_SEL | EGPIO_PIN_ALT) -#define EGPIO_PIN_LCD_EN EGPIO_PIN(EGPIO_CHIP_EVE, EVE_GPIO_LCD_EN) -#define EGPIO_PIN_CAM_EN EGPIO_PIN(EGPIO_CHIP_EVE, EVE_GPIO_CAM_EN) -#define EGPIO_PIN_DISP_SEL EGPIO_PIN(EGPIO_CHIP_EVE, EGPIOE_PIN_DISP) - -#define EGPIO_BIT_EVE_INT EGPIO_PIN2BIT(EGPIO0_PIN_EVE_INT) -#define EGPIO_BIT_SDCARD_DET EGPIO_PIN2BIT(EGPIO0_PIN_SDCARD_DET) -#define EGPIO_BIT_EXP_IO0 EGPIO_PIN2BIT(EGPIO0_PIN_EXP_IO0) -#define EGPIO_BIT_EXP_IO1 EGPIO_PIN2BIT(EGPIO0_PIN_EXP_IO1) -#define EGPIO_BIT_BTN_WAKE EGPIO_PIN2BIT(EGPIO0_PIN_BTN_WAKE) -#define EGPIO_BIT_BAT_INT EGPIO_PIN2BIT(EGPIO0_PIN_BAT_INT) -#define EGPIO_BIT_CTP_SEL EGPIO_PIN2BIT(EGPIO0_PIN_CTP_SEL) -#define EGPIO_BIT_CTP_INT EGPIO_PIN2BIT(EGPIO0_PIN_CTP_INT) - -#define EGPIO_BIT_MIC_MUTE EGPIO_PIN2BIT(EGPIO1_PIN_MIC_MUTE) -#define EGPIO_BIT_HPAMP_CS EGPIO_PIN2BIT(EGPIO1_PIN_HPAMP_CS) -#define EGPIO_BIT_AUDIO_SEL EGPIO_PIN2BIT(EGPIO1_PIN_AUDIO_SEL) -#define EGPIO_BIT_HP_NDET EGPIO_PIN2BIT(EGPIO1_PIN_HP_NDET) -#define EGPIO_BIT_USR0 EGPIO_PIN2BIT(EGPIO1_PIN_USR0) -#define EGPIO_BIT_USR1 EGPIO_PIN2BIT(EGPIO1_PIN_USR1) -#define EGPIO_BIT_USR2 EGPIO_PIN2BIT(EGPIO1_PIN_USR2) -#define EGPIO_BIT_USR3 EGPIO_PIN2BIT(EGPIO1_PIN_USR3) +#define EOS_EGPIO_INT_TYPE_BAT 1 +#define EOS_EGPIO_INT_TYPE_WAKE 2 +#define EOS_EGPIO_INT_TYPE_SDCARD 3 +#define EOS_EGPIO_INT_TYPE_MUTE 4 +#define EOS_EGPIO_INT_TYPE_HP 5 typedef void (*eos_egpio_intr_handler_t) (uint8_t type, int data0, int data1); typedef int (*eos_egpio_ext_handler_t) (void); @@ -95,7 +15,6 @@ typedef int (*eos_egpio_ext_handler_t) (void); int eos_egpio_init(void); int eos_egpio_run(void); void eos_egpio_eve_set(uint16_t gpio_reg); -int _eos_egpio_intr_set(int i2s_running, int app_running); int eos_egpio_intr_set(void); int eos_egpio_intr_enable(void); int eos_egpio_intr_disable(void); @@ -106,8 +25,6 @@ void eos_egpio_set_ext_handler(eos_egpio_ext_handler_t handler); int eos_egpio_fxl_get_pin(uint8_t reg, uint8_t pin, uint8_t *val); int eos_egpio_fxl_set_pin(uint8_t reg, uint8_t pin, uint8_t val); -int _eos_egpio_get_val(uint8_t pin); -int _eos_egpio_set_val(uint8_t pin, int val); int eos_egpio_get_val(uint8_t pin); int eos_egpio_set_val(uint8_t pin, int val); diff --git a/fw/fe310/eos/dev/egpio_priv.h b/fw/fe310/eos/dev/egpio_priv.h new file mode 100644 index 0000000..04fe271 --- /dev/null +++ b/fw/fe310/eos/dev/egpio_priv.h @@ -0,0 +1,81 @@ +#include "eve_priv.h" + +#define EGPIO_CHIP_FXL0 0 +#define EGPIO_CHIP_FXL1 1 +#define EGPIO_CHIP_EVE 2 + +#define EGPIO_MAX_CHIP 3 +#define EGPIO_MAX_FXL_CHIP 2 + +#define EGPIO_PIN_MASK 0x07 +#define EGPIO_PIN_MASK_CHIP 0x30 + +#define EGPIO_PIN2BIT(X) (1 << ((X) & EGPIO_PIN_MASK)) +#define EGPIO_PIN2CHIP(X) (((X) & EGPIO_PIN_MASK_CHIP) >> 4) +#define EGPIO_PIN(C,P) (((C) << 4) | (P)) + +#define EGPIO0_PIN_EVE_INT 0x00 /* EVE interrrupt */ +#define EGPIO0_PIN_SDCARD_NDET 0x01 /* SD Card detect: 0 - inserted, 1 - not inserted */ +#define EGPIO0_PIN_EXP_IO0 0x02 /* expansion io 0 */ +#define EGPIO0_PIN_EXP_IO1 0x03 /* expansion io 1 */ +#define EGPIO0_PIN_BTN_WAKE 0x04 /* wake button */ +#define EGPIO0_PIN_BAT_INT 0x05 /* battery charger IC inetrrupt */ +#define EGPIO0_PIN_CTP_SEL 0x06 /* switch CTP connection: EVE_DISP:1 and CTP_SEL:0 - connected to EVE chip, EVE_DISP:X and CTP_SEL:1 - connected to fe310 chip, EVE_DISP:0 and CTP_SEL:0 - connected to app module */ +#define EGPIO0_PIN_CTP_INT 0x07 /* CTP interrupt */ + +#define EGPIO1_PIN_MIC_MUTE 0x00 /* microphone disable */ +#define EGPIO1_PIN_HPAMP_CS 0x01 /* SPI chip select for headphone amplifier (pcm1770) */ +#define EGPIO1_PIN_AUDIO_SEL 0x02 /* switch audio connection: 0 - connected to app module, 1 - connected to fe310 chip (only when i2s is off) */ +#define EGPIO1_PIN_HP_NDET 0x03 /* headphone detect: 0 - inserted, 1 - not inserted */ +#define EGPIO1_PIN_USR0 0x04 /* user IO */ +#define EGPIO1_PIN_USR1 0x05 +#define EGPIO1_PIN_USR2 0x06 +#define EGPIO1_PIN_USR3 0x07 + +#define EGPIOE_PIN_DISP 0x07 /* EVE DISP GPIO */ + +#define EGPIO_PIN_ALT 0x08 + +#define EGPIO_BIT_EVE_INT EGPIO_PIN2BIT(EGPIO0_PIN_EVE_INT) +#define EGPIO_BIT_SDCARD_NDET EGPIO_PIN2BIT(EGPIO0_PIN_SDCARD_NDET) +#define EGPIO_BIT_EXP_IO0 EGPIO_PIN2BIT(EGPIO0_PIN_EXP_IO0) +#define EGPIO_BIT_EXP_IO1 EGPIO_PIN2BIT(EGPIO0_PIN_EXP_IO1) +#define EGPIO_BIT_BTN_WAKE EGPIO_PIN2BIT(EGPIO0_PIN_BTN_WAKE) +#define EGPIO_BIT_BAT_INT EGPIO_PIN2BIT(EGPIO0_PIN_BAT_INT) +#define EGPIO_BIT_CTP_SEL EGPIO_PIN2BIT(EGPIO0_PIN_CTP_SEL) +#define EGPIO_BIT_CTP_INT EGPIO_PIN2BIT(EGPIO0_PIN_CTP_INT) + +#define EGPIO_BIT_MIC_MUTE EGPIO_PIN2BIT(EGPIO1_PIN_MIC_MUTE) +#define EGPIO_BIT_HPAMP_CS EGPIO_PIN2BIT(EGPIO1_PIN_HPAMP_CS) +#define EGPIO_BIT_AUDIO_SEL EGPIO_PIN2BIT(EGPIO1_PIN_AUDIO_SEL) +#define EGPIO_BIT_HP_NDET EGPIO_PIN2BIT(EGPIO1_PIN_HP_NDET) +#define EGPIO_BIT_USR0 EGPIO_PIN2BIT(EGPIO1_PIN_USR0) +#define EGPIO_BIT_USR1 EGPIO_PIN2BIT(EGPIO1_PIN_USR1) +#define EGPIO_BIT_USR2 EGPIO_PIN2BIT(EGPIO1_PIN_USR2) +#define EGPIO_BIT_USR3 EGPIO_PIN2BIT(EGPIO1_PIN_USR3) + +#define EGPIO_PIN_EVE_INT EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_EVE_INT) +#define EGPIO_PIN_SDCARD_NDET EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_SDCARD_NDET) +#define EGPIO_PIN_EXP_IO0 EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_EXP_IO0) +#define EGPIO_PIN_EXP_IO1 EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_EXP_IO1) +#define EGPIO_PIN_BTN_WAKE EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_BTN_WAKE) +#define EGPIO_PIN_BAT_INT EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_BAT_INT) +#define EGPIO_PIN_CTP_SEL EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_CTP_SEL) +#define EGPIO_PIN_CTP_INT EGPIO_PIN(EGPIO_CHIP_FXL0, EGPIO0_PIN_CTP_INT) + +#define EGPIO_PIN_MIC_MUTE EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_MIC_MUTE) +#define EGPIO_PIN_HPAMP_CS EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_HPAMP_CS) +#define EGPIO_PIN_AUDIO_SEL EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_AUDIO_SEL) +#define EGPIO_PIN_HP_NDET EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_HP_NDET) +#define EGPIO_PIN_USR0 EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_USR0) +#define EGPIO_PIN_USR1 EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_USR1) +#define EGPIO_PIN_USR2 EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_USR2) +#define EGPIO_PIN_USR3 EGPIO_PIN(EGPIO_CHIP_FXL1, EGPIO1_PIN_USR3) + +/* EVE pins defined in eve.h */ +#define EGPIO_PIN_USR4 EGPIO_PIN(EGPIO_CHIP_EVE, EVE_GPIO_USR) +#define EGPIO_PIN_EVEAUDIO_DIS EGPIO_PIN(EGPIO_CHIP_EVE, EVE_GPIO_EVEAUDIO_DIS) +#define EGPIO_PIN_LSGAIN_SEL EGPIO_PIN(EGPIO_CHIP_EVE, EVE_GPIO_LSGAIN_SEL | EGPIO_PIN_ALT) +#define EGPIO_PIN_LCD_EN EGPIO_PIN(EGPIO_CHIP_EVE, EVE_GPIO_LCD_EN) +#define EGPIO_PIN_CAM_EN EGPIO_PIN(EGPIO_CHIP_EVE, EVE_GPIO_CAM_EN) +#define EGPIO_PIN_DISP_SEL EGPIO_PIN(EGPIO_CHIP_EVE, EGPIOE_PIN_DISP) diff --git a/fw/fe310/eos/dev/eve.c b/fw/fe310/eos/dev/eve.c index dad7dfe..873cd7a 100644 --- a/fw/fe310/eos/dev/eve.c +++ b/fw/fe310/eos/dev/eve.c @@ -2,6 +2,7 @@ #include <stdint.h> #include "eos.h" +#include "log.h" #include "event.h" #include "soc/pwr.h" @@ -11,15 +12,12 @@ #include "eve/eve_touch_engine.h" #include "egpio.h" +#include "egpio_priv.h" #include "spi.h" #include "aon.h" -#include "pwr.h" #include "eve.h" - -#ifdef EOS_DEBUG -#include <stdio.h> -#endif +#include "eve_priv.h" static void handle_time(unsigned char type) { int rv; @@ -36,13 +34,12 @@ int eos_eve_handle_intr(void) { int rv; rv = eve_select(); - if (rv) return 0; + if (rv) return rv; intr_flags = eve_handle_intr(); eve_deselect(); - if (intr_flags == 0) return 0; - return 1; + return intr_flags; } int eos_eve_init(void) { @@ -64,17 +61,9 @@ int eos_eve_init(void) { eve_touch_init_engine(eos_egpio_get_val(EGPIO_PIN_CTP_SEL) ? EVE_TOUCH_ENGINE_HOST : EVE_TOUCH_ENGINE_GOODIX); gpio_reg = EVE_GPIO_DEFAULT; } else { - uint8_t pwr_state; - - pwr_state = eos_aon_load4eve(); - eve_pwr_set_state(pwr_state); - eve_activate(); gpio_reg = eve_gpio_read(); eve_cmd_set_offset(); - if (gpio_reg & EVE_GPIO_DISP) { - eve_pwr_set_state(EVE_PSTATE_ACTIVE); - } eve_deactivate(); } @@ -92,49 +81,86 @@ eve_init_fin: } int eos_eve_run(void) { - int rv; + uint8_t wakeup_cause; + int rst, rv; + + wakeup_cause = eos_pwr_wakeup_cause(); + rst = (wakeup_cause == EOS_PWR_WAKE_RST); - if (eve_pwr_state() != EVE_PSTATE_ACTIVE) return EOS_ERR_BUSY; + if (!rst) { + /* was active before sleep */ + if (eve_pwr_state() == EVE_PSTATE_ACTIVE) return EOS_OK; + + /* Display is attached to app module */ + if (!eos_egpio_get_val(EGPIO_PIN_DISP_SEL)) return EOS_ERR_BUSY; + } rv = eve_select(); if (rv) return rv; - eve_touch_intr_enable(); - eve_touch_start(); - eve_intr_enable(); - eve_clk_start(); + if (!rst) eve_pwr_wake(); + _eos_eve_wake(); + if (rst) eve_set_brightness(0x40); eve_deselect(); return EOS_OK; } +void _eos_eve_sleep(void) { + eos_aon_save4eve_pwm(eve_get_brightness()); + eve_set_brightness(0); + eve_clk_stop(); + eve_intr_disable(); + eve_touch_stop(); + eve_touch_intr_disable(); +} + int eos_eve_sleep(void) { int rv; + if (eve_pwr_state() != EVE_PSTATE_ACTIVE) return EOS_ERR; + rv = eve_select(); if (rv) return rv; - eos_aon_save4eve(eve_pwr_state()); - eve_clk_stop(); - eve_intr_disable(); - eve_touch_stop(); - eve_touch_intr_disable(); + _eos_eve_sleep(); eve_pwr_sleep(); eve_deselect(); return EOS_OK; } +void _eos_eve_wake(void) { + eve_touch_intr_enable(); + eve_touch_start(); + eve_intr_enable(); + eve_clk_start(); + eve_set_brightness(eos_aon_load4eve_pwm()); +} + +int eos_eve_wake(void) { + int disp, rv; + + if (eve_pwr_state() == EVE_PSTATE_ACTIVE) return EOS_ERR; + if (!eos_egpio_get_val(EGPIO_PIN_DISP_SEL)) return EOS_ERR_BUSY; + + rv = eve_select(); + if (rv) return rv; + + eve_pwr_wake(); + _eos_eve_wake(); + + eve_deselect(); + + return rv; +} + void eve_calibrate(void) { int rv, d; -#ifdef EOS_DEBUG uint32_t matrix[6]; -#endif if (!eve_selected()) { -#ifdef EOS_DEBUG - printf("EVE CALIBRATE: NOT SELECTED\n"); -#endif + EOS_LOG(EOS_LOG_ERR, "EVE CALIBRATE: NOT SELECTED\n"); return; } @@ -155,25 +181,21 @@ void eve_calibrate(void) { eos_evtq_exec(); rv = eve_select(); if (rv) { -#ifdef EOS_DEBUG - printf("EVE CALIBRATE ERR:%d\n", rv); -#endif + EOS_LOG(EOS_LOG_ERR, "EVE CALIBRATE ERR:%d\n", rv); return; } } while (!d); eve_touch_set_extended(1); -#ifdef EOS_DEBUG if (rv) { - printf("EVE CALIBRATE ERR:%d\n", rv); + EOS_LOG(EOS_LOG_ERR, "EVE CALIBRATE ERR:%d\n", rv); return; } eve_touch_get_matrix(matrix); - printf("TOUCH MATRIX:\n"); - printf("uint32_t touch_matrix[6] = {0x%x,0x%x,0x%x,0x%x,0x%x,0x%x}\n", matrix[0], matrix[1], matrix[2], matrix[3], matrix[4], matrix[5]); -#endif + EOS_LOG(EOS_LOG_INFO, "TOUCH MATRIX:\n"); + EOS_LOG(EOS_LOG_INFO, "uint32_t touch_matrix[6] = {0x%x,0x%x,0x%x,0x%x,0x%x,0x%x}\n", matrix[0], matrix[1], matrix[2], matrix[3], matrix[4], matrix[5]); } int eve_select(void) { diff --git a/fw/fe310/eos/dev/eve.h b/fw/fe310/eos/dev/eve.h index 441cd5a..11d7cc9 100644 --- a/fw/fe310/eos/dev/eve.h +++ b/fw/fe310/eos/dev/eve.h @@ -1,21 +1,12 @@ #include <stdint.h> -#define EVE_GPIO_DIR 0x800f -#define EVE_GPIO_DEFAULT 0x2 /* EVEAUDIO_DIS */ -#define EVE_GPIO_MASK 0x800f - -#define EVE_GPIO_USR 0 -#define EVE_GPIO_EVEAUDIO_DIS 1 /* only when lspk is off */ -#define EVE_GPIO_LSGAIN_SEL 1 /* only when lspk is on */ -#define EVE_GPIO_LCD_EN 2 -#define EVE_GPIO_CAM_EN 3 -#define EVE_GPIO_DISP 15 - int eos_eve_handle_intr(void); int eos_eve_init(void); int eos_eve_run(void); +void _eos_eve_sleep(void); int eos_eve_sleep(void); +void _eos_eve_wake(void); int eos_eve_wake(void); void eve_calibrate(void); diff --git a/fw/fe310/eos/dev/eve_priv.h b/fw/fe310/eos/dev/eve_priv.h new file mode 100644 index 0000000..8baf6a4 --- /dev/null +++ b/fw/fe310/eos/dev/eve_priv.h @@ -0,0 +1,9 @@ +#define EVE_GPIO_DIR 0x800f +#define EVE_GPIO_DEFAULT 0x8002 /* DISP on, EVEAUDIO_DIS */ + +#define EVE_GPIO_USR 0 +#define EVE_GPIO_EVEAUDIO_DIS 1 /* only when lspk is off */ +#define EVE_GPIO_LSGAIN_SEL 1 /* only when lspk is on */ +#define EVE_GPIO_LCD_EN 2 +#define EVE_GPIO_CAM_EN 3 +#define EVE_GPIO_DISP 15 diff --git a/fw/fe310/eos/dev/flash.c b/fw/fe310/eos/dev/flash.c index c8f4c98..15811a2 100644 --- a/fw/fe310/eos/dev/flash.c +++ b/fw/fe310/eos/dev/flash.c @@ -9,6 +9,21 @@ #include "flash.h" +#define FLASH_RDSR 0x05 + +#define FLASH_NORD 0x03 +#define FLASH_FRD 0x0b + +#define FLASH_WREN 0x06 +#define FLASH_SER 0x20 +#define FLASH_PP 0x02 + +#define FLASH_QPIEN 0x35 +#define FLASH_QPIDI 0xF5 + +#define FLASH_WIP 0x01 +#define FLASH_WEL 0x02 + #define IDLE_TICKS 10 __attribute__ ((section (".itim.flash"))) @@ -42,7 +57,7 @@ void eos_flash_norm(void) { SPI0_REG(SPI_REG_SCKDIV) = 3; if (SPI0_REG(SPI_REG_FMT) & SPI_FMT_PROTO(SPI_PROTO_Q)) { - send(EOS_FLASH_QPIDI); + send(FLASH_QPIDI); while (!(SPI0_REG(SPI_REG_IP) & SPI_IP_TXWM)); } @@ -59,7 +74,7 @@ void eos_flash_norm(void) { SPI_INSN_CMD_PROTO(SPI_PROTO_S) | SPI_INSN_ADDR_PROTO(SPI_PROTO_S) | SPI_INSN_DATA_PROTO(SPI_PROTO_S) | - SPI_INSN_CMD_CODE(EOS_FLASH_NORD) | + SPI_INSN_CMD_CODE(FLASH_NORD) | SPI_INSN_PAD_CODE(0x00); mtime0 = *mtime; @@ -79,7 +94,7 @@ void eos_flash_fast(void) { SPI0_REG(SPI_REG_SCKDIV) = 2; if (!(SPI0_REG(SPI_REG_FMT) & SPI_FMT_PROTO(SPI_PROTO_Q))) { - send(EOS_FLASH_QPIEN); + send(FLASH_QPIEN); while (!(SPI0_REG(SPI_REG_IP) & SPI_IP_TXWM)); } @@ -96,7 +111,7 @@ void eos_flash_fast(void) { SPI_INSN_CMD_PROTO(SPI_PROTO_Q) | SPI_INSN_ADDR_PROTO(SPI_PROTO_Q) | SPI_INSN_DATA_PROTO(SPI_PROTO_Q) | - SPI_INSN_CMD_CODE(EOS_FLASH_FRD) | + SPI_INSN_CMD_CODE(FLASH_FRD) | SPI_INSN_PAD_CODE(0x00); mtime0 = *mtime; @@ -112,31 +127,31 @@ void eos_flash_wip(void) { do { SPI0_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD; - xfer(EOS_FLASH_RDSR); + xfer(FLASH_RDSR); status = xfer(0); SPI0_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO; - } while (status & EOS_FLASH_WIP); + } while (status & FLASH_WIP); } __attribute__ ((section (".itim.flash"))) void eos_flash_wren(void) { uint8_t status; - xfer(EOS_FLASH_WREN); + xfer(FLASH_WREN); #if 0 do { SPI0_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD; - xfer(EOS_FLASH_RDSR); + xfer(FLASH_RDSR); status = xfer(0); SPI0_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO; - } while (!(status & EOS_FLASH_WEL)); + } while (!(status & FLASH_WEL)); #endif } __attribute__ ((section (".itim.flash"))) void eos_flash_ser(uint32_t addr) { SPI0_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD; - xfer(EOS_FLASH_SER); + xfer(FLASH_SER); xfer(addr >> 16); xfer(addr >> 8); xfer(addr); @@ -149,7 +164,7 @@ void eos_flash_pp(uint32_t addr, uint8_t *buf) { SPI0_REG(SPI_REG_FMT) |= SPI_FMT_DIR(SPI_DIR_TX); SPI0_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD; - send(EOS_FLASH_PP); + send(FLASH_PP); send(addr >> 16); send(addr >> 8); send(addr); diff --git a/fw/fe310/eos/dev/flash.h b/fw/fe310/eos/dev/flash.h index 6f792cb..714e9bc 100644 --- a/fw/fe310/eos/dev/flash.h +++ b/fw/fe310/eos/dev/flash.h @@ -1,20 +1,5 @@ #include <stdint.h> -#define EOS_FLASH_RDSR 0x05 - -#define EOS_FLASH_NORD 0x03 -#define EOS_FLASH_FRD 0x0b - -#define EOS_FLASH_WREN 0x06 -#define EOS_FLASH_SER 0x20 -#define EOS_FLASH_PP 0x02 - -#define EOS_FLASH_QPIEN 0x35 -#define EOS_FLASH_QPIDI 0xF5 - -#define EOS_FLASH_WIP 0x01 -#define EOS_FLASH_WEL 0x02 - void eos_flash_init(void); void eos_flash_norm(void); void eos_flash_fast(void); diff --git a/fw/fe310/eos/dev/lcd.c b/fw/fe310/eos/dev/lcd.c index 6c005b9..9fb8767 100644 --- a/fw/fe310/eos/dev/lcd.c +++ b/fw/fe310/eos/dev/lcd.c @@ -13,9 +13,8 @@ #include "eve/eve.h" #include "egpio.h" +#include "egpio_priv.h" #include "spi.h" -#include "eve.h" -#include "pwr.h" #include "drv/ili9806e.h" #include "lcd.h" @@ -23,8 +22,6 @@ static int lcd_enable(void) { int rv; - if (eos_i2s_running() || !eos_egpio_get_val(EGPIO_PIN_DISP_SEL)) return EOS_ERR_BUSY; - rv = eos_egpio_set_val(EGPIO_PIN_LCD_EN, 1); return rv; } @@ -32,16 +29,18 @@ static int lcd_enable(void) { static int lcd_disable(void) { int rv; - if (eos_i2s_running() || !eos_egpio_get_val(EGPIO_PIN_DISP_SEL)) return EOS_ERR_BUSY; - rv = eos_egpio_set_val(EGPIO_PIN_LCD_EN, 0); return rv; } +static int lcd_enabled(void) { + return eos_egpio_get_val(EGPIO_PIN_LCD_EN); +} + static int lcd_select(void) { int rv; - if (eos_i2s_running() || !eos_egpio_get_val(EGPIO_PIN_DISP_SEL)) return EOS_ERR_BUSY; + if (eos_i2s_running()) return EOS_ERR_BUSY; GPIO_REG(GPIO_OUTPUT_XOR) |= (1 << SPI_CSPIN_LCD); GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << SPI_CSPIN_LCD); @@ -52,6 +51,7 @@ static int lcd_select(void) { GPIO_REG(GPIO_OUTPUT_EN) &= ~(1 << SPI_CSPIN_LCD); GPIO_REG(GPIO_OUTPUT_XOR) &= ~(1 << SPI_CSPIN_LCD); GPIO_REG(GPIO_OUTPUT_VAL) &= ~(1 << SPI_CSPIN_LCD); + return rv; } @@ -60,6 +60,7 @@ static int lcd_select(void) { static void lcd_deselect(void) { eos_spi_deselect(); + GPIO_REG(GPIO_OUTPUT_EN) &= ~(1 << SPI_CSPIN_LCD); GPIO_REG(GPIO_OUTPUT_XOR) &= ~(1 << SPI_CSPIN_LCD); GPIO_REG(GPIO_OUTPUT_VAL) &= ~(1 << SPI_CSPIN_LCD); @@ -80,13 +81,32 @@ static int lcd_init(void) { } rv = ili9806e_init(); - if (rv == EOS_ERR_NOTFOUND) eve_lcd_absent(); + if (rv == EOS_ERR_NOTFOUND) eve_lcd_set_absent(1); lcd_deselect(); if (rv) lcd_disable(); return rv; } +static int lcd_reset(void) { + int rv; + + if (!lcd_enabled()) return EOS_ERR; + + rv = lcd_disable(); + if (rv) return rv; + + eos_sleep(10); + + rv = lcd_init(); + if (rv) { + lcd_enable(); + return rv; + } + + return EOS_OK; +} + static int lcd_sleep(void) { int rv; @@ -104,6 +124,9 @@ int eos_lcd_init(void) { uint8_t wakeup_cause; int rv, rst; + if (!eos_egpio_get_val(EGPIO_PIN_DISP_SEL)) return EOS_ERR_BUSY; + if (lcd_enabled()) return EOS_ERR; + wakeup_cause = eos_pwr_wakeup_cause(); rst = (wakeup_cause == EOS_PWR_WAKE_RST); if (rst) { @@ -118,6 +141,8 @@ int eos_lcd_init(void) { int eos_lcd_sleep(void) { int rv; + if (!lcd_enabled()) return EOS_ERR; + rv = lcd_sleep(); return rv; } @@ -125,6 +150,16 @@ int eos_lcd_sleep(void) { int eos_lcd_wake(void) { int rv; + if (lcd_enabled()) return EOS_ERR; + rv = lcd_init(); return rv; } + +int eos_lcd_take(void) { + return lcd_reset(); +} + +int eos_lcd_give(void) { + return lcd_reset(); +} diff --git a/fw/fe310/eos/dev/lcd.h b/fw/fe310/eos/dev/lcd.h index fafe2b4..f52ee8a 100644 --- a/fw/fe310/eos/dev/lcd.h +++ b/fw/fe310/eos/dev/lcd.h @@ -3,3 +3,5 @@ int eos_lcd_init(void); int eos_lcd_sleep(void); int eos_lcd_wake(void); +int eos_lcd_take(void); +int eos_lcd_give(void); diff --git a/fw/fe310/eos/dev/net.c b/fw/fe310/eos/dev/net.c index c8b90f3..7ab4947 100644 --- a/fw/fe310/eos/dev/net.c +++ b/fw/fe310/eos/dev/net.c @@ -6,7 +6,7 @@ #include "board.h" #include "eos.h" -#include "msgq.h" +#include "log.h" #include "event.h" #include "soc/interrupt.h" @@ -16,72 +16,77 @@ #include "soc/spi_priv.h" #include "spi.h" +#include "aon.h" #include "net.h" -#define NET_SIZE_HDR 3 -#define NET_STATE_FLAG_RUN 0x01 -#define NET_STATE_FLAG_INIT 0x02 -#define NET_STATE_FLAG_XCHG 0x04 -#define NET_STATE_FLAG_ONEW 0x10 -#define NET_STATE_FLAG_SYNC 0x20 -#define NET_STATE_FLAG_RTS 0x40 -#define NET_STATE_FLAG_CTS 0x80 +#define NET_DETECT_TIMEOUT 1000 + +#define NET_SIZE_HDR 3 +#define NET_SIZE_BUFQ 2 + +#define NET_STATE_FLAG_RUN 0x0001 +#define NET_STATE_FLAG_RTS 0x0002 +#define NET_STATE_FLAG_CTS 0x0004 +#define NET_STATE_FLAG_INIT 0x0010 +#define NET_STATE_FLAG_XCHG 0x0020 +#define NET_STATE_FLAG_ONEW 0x0040 +#define NET_STATE_FLAG_SYNC 0x0080 +#define NET_STATE_FLAG_SLEEP 0x0100 +#define NET_STATE_FLAG_SLEEP_REQ 0x0200 +#define NET_STATE_FLAG_ABSENT 0x0400 +#define NET_STATE_FLAG_ERR_SIZE 0x0800 #define MIN(X, Y) (((X) < (Y)) ? (X) : (Y)) #define MAX(X, Y) (((X) > (Y)) ? (X) : (Y)) static EOSBufQ net_buf_q; -static unsigned char *net_bufq_array[EOS_NET_SIZE_BUFQ]; -static unsigned char net_bufq_buffer[EOS_NET_SIZE_BUFQ][EOS_NET_SIZE_BUF] __attribute__((section (".itim2"))); +static unsigned char *net_bufq_array[NET_SIZE_BUFQ]; +static unsigned char net_bufq_buffer[NET_SIZE_BUFQ][EOS_NET_MTU] __attribute__((section (".itim2"))); static EOSMsgQ net_send_q; -static EOSMsgItem net_sndq_array[EOS_NET_SIZE_BUFQ]; +static EOSMsgItem net_sndq_array[NET_SIZE_BUFQ]; -static volatile uint8_t net_state_flags = 0; +static volatile uint16_t net_state_flags = 0; static volatile unsigned char net_state_type = 0; static uint32_t net_state_len_tx = 0; static volatile uint32_t net_state_len_rx = 0; static unsigned char *net_state_buf = NULL; +static uint16_t net_state_buf_sz = 0; static volatile uint8_t net_state_next_cnt = 0; static unsigned char * volatile net_state_next_buf = NULL; static eos_evt_handler_t net_handler[EOS_NET_MAX_MTYPE]; -static uint16_t net_wrapper_acq[EOS_EVT_MAX_EVT]; -static uint16_t net_flags_acq[EOS_EVT_MAX_EVT]; +static uint16_t net_wrapper_acq; +static uint16_t net_flags_acq[EOS_EVT_MAX]; -static int net_xchg_sleep(void) { - int i; - int rv = EOS_OK; +static void net_xchg_reset(void) { volatile uint32_t x = 0; + net_state_flags &= ~NET_STATE_FLAG_CTS; SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD; - SPI1_REG(SPI_REG_TXFIFO) = 0xFF; + SPI1_REG(SPI_REG_TXFIFO) = 0; while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY); - if (x & 0xFF) rv = EOS_ERR_BUSY; - - for (i=0; i<7; i++) { - while (SPI1_REG(SPI_REG_TXFIFO) & SPI_TXFIFO_FULL); - SPI1_REG(SPI_REG_TXFIFO) = 0; - while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY); - } SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO; - - return rv; } -static void net_xchg_wake(void) { - int i; +static void net_xchg_sleep_req(void) { volatile uint32_t x = 0; + int i; + net_state_flags &= ~NET_STATE_FLAG_CTS; SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD; - for (i=0; i<8; i++) { + SPI1_REG(SPI_REG_TXFIFO) = EOS_NET_MTYPE_SLEEP | EOS_NET_MTYPE_FLAG_ONEW; + while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY); + + /* minimum 8 bytes for esp32 */ + for (i=0; i<7; i++) { while (SPI1_REG(SPI_REG_TXFIFO) & SPI_TXFIFO_FULL); SPI1_REG(SPI_REG_TXFIFO) = 0; while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY); @@ -90,20 +95,8 @@ static void net_xchg_wake(void) { SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO; } -static void net_xchg_reset(void) { - volatile uint32_t x = 0; - net_state_flags &= ~NET_STATE_FLAG_CTS; - - SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD; - - SPI1_REG(SPI_REG_TXFIFO) = 0; - while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY); - - SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO; -} - -static void net_xchg_start(unsigned char type, unsigned char *buffer, uint16_t len) { - net_state_flags &= ~NET_STATE_FLAG_CTS; +static void net_xchg_start(unsigned char type, EOSMessage *msg, uint16_t len) { + net_state_flags &= ~(NET_STATE_FLAG_CTS | NET_STATE_FLAG_ERR_SIZE); net_state_flags |= (NET_STATE_FLAG_INIT | NET_STATE_FLAG_XCHG); if (net_state_next_cnt && (net_state_next_buf == NULL)) type |= EOS_NET_MTYPE_FLAG_ONEW; @@ -112,7 +105,8 @@ static void net_xchg_start(unsigned char type, unsigned char *buffer, uint16_t l net_state_type = type; net_state_len_tx = len; net_state_len_rx = 0; - net_state_buf = buffer; + net_state_buf = msg->buffer; + net_state_buf_sz = msg->size; SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD; SPI1_REG(SPI_REG_TXFIFO) = type; @@ -122,26 +116,27 @@ static void net_xchg_start(unsigned char type, unsigned char *buffer, uint16_t l SPI1_REG(SPI_REG_IE) = SPI_IP_RXWM; } -static int net_xchg_next(unsigned char *_buffer) { +static int net_xchg_next(EOSMessage *_msg) { unsigned char type; - unsigned char *buffer = NULL; + EOSMessage msg; uint16_t len; - int ret = _buffer ? 1 : 0; + int do_release = _msg ? 1 : 0; - eos_msgq_pop(&net_send_q, &type, &buffer, &len); + eos_msgq_pop(&net_send_q, &type, &msg, &len); if (type) { - net_xchg_start(type, buffer, len); + net_xchg_start(type, &msg, len); } else if (net_state_flags & NET_STATE_FLAG_RTS) { - if (_buffer) { - buffer = _buffer; - ret = 0; + if (_msg) { + msg = *_msg; + do_release = 0; } else { - buffer = eos_bufq_pop(&net_buf_q); + msg.buffer = eos_bufq_pop(&net_buf_q); + msg.size = EOS_NET_MTU; } - if (buffer) net_xchg_start(0, buffer, 0); + if (msg.buffer) net_xchg_start(0, &msg, 0); } - return ret; + return do_release; } static void net_handle_xchg(void) { @@ -161,50 +156,69 @@ static void net_handle_xchg(void) { r3 = 0; } - net_state_type = (r1 & 0xFF); + net_state_type = r1; net_state_len_rx = (r2 & 0xFF) << 8; net_state_len_rx |= (r3 & 0xFF); len = MAX(net_state_len_tx, net_state_len_rx); - // esp32 dma workaraund + /* esp32 dma workaraund */ if (len < 8 - NET_SIZE_HDR) { len = 8 - NET_SIZE_HDR; } else if ((len + NET_SIZE_HDR) % 4 != 0) { len = ((len + NET_SIZE_HDR)/4 + 1) * 4 - NET_SIZE_HDR; } - if (len > EOS_NET_MTU) { + if (len > net_state_buf_sz) { + net_state_type = 0; + net_state_len_tx = 0; + net_state_len_rx = 0; + net_state_flags |= NET_STATE_FLAG_ERR_SIZE; net_state_flags &= ~NET_STATE_FLAG_XCHG; SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO; SPI1_REG(SPI_REG_IE) = 0x0; return; } - _eos_spi_xchg_init(net_state_buf, len, 0); + _eos_spi_xchg_init(net_state_buf, net_state_buf_sz, len, 0); SPI1_REG(SPI_REG_TXCTRL) = SPI_TXWM(SPI_SIZE_WM); SPI1_REG(SPI_REG_IE) = SPI_IP_TXWM; return; } eos_spi_handle_xchg(); - if (SPI1_REG(SPI_REG_CSMODE) == SPI_CSMODE_AUTO) { // exchange done + if (SPI1_REG(SPI_REG_CSMODE) == SPI_CSMODE_AUTO) { + /* exchange done */ if (!(net_state_flags & NET_STATE_FLAG_SYNC)) { if (net_state_type) { - int r = eos_evtq_push_isr(EOS_EVT_NET | (net_state_type & ~EOS_NET_MTYPE_FLAG_MASK), net_state_buf, net_state_len_rx); - if (r) eos_bufq_push(&net_buf_q, net_state_buf); + if (net_state_type == EOS_NET_MTYPE_SLEEP) { + net_state_flags |= NET_STATE_FLAG_SLEEP; + eos_bufq_push(&net_buf_q, net_state_buf); + } else { + EOSMessage msg; + int rv; + + msg.buffer = net_state_buf; + msg.size = net_state_buf_sz; + rv = eos_evtq_push_isr(EOS_EVT_NET | (net_state_type & EOS_NET_MTYPE_MASK), &msg, net_state_len_rx); + if (rv) { + EOS_LOG(EOS_LOG_ERR, "NET XCHG EVTQ PUSH ERR:%d\n", rv); + eos_bufq_push(&net_buf_q, net_state_buf); + } + } } else if (((net_state_flags & NET_STATE_FLAG_ONEW) || net_state_next_cnt) && (net_state_next_buf == NULL)) { net_state_next_buf = net_state_buf; } else { eos_bufq_push(&net_buf_q, net_state_buf); } } - net_state_flags &= ~(NET_STATE_FLAG_ONEW | NET_STATE_FLAG_XCHG); + net_state_flags &= ~(NET_STATE_FLAG_XCHG | NET_STATE_FLAG_ONEW); } } static void net_handle_cts(void) { - GPIO_REG(GPIO_RISE_IP) = (1 << NET_PIN_CTS); + GPIO_REG(GPIO_FALL_IP) = (1 << NET_PIN_CTS); net_state_flags |= NET_STATE_FLAG_CTS; + net_state_flags &= ~NET_STATE_FLAG_SLEEP; if (net_state_flags & NET_STATE_FLAG_RUN) { net_xchg_next(NULL); @@ -214,25 +228,33 @@ static void net_handle_cts(void) { static void net_handle_rts(void) { uint32_t rts_offset = (1 << NET_PIN_RTS); - if (GPIO_REG(GPIO_RISE_IP) & rts_offset) { - GPIO_REG(GPIO_RISE_IP) = rts_offset; + if (GPIO_REG(GPIO_FALL_IP) & rts_offset) { + GPIO_REG(GPIO_FALL_IP) = rts_offset; net_state_flags |= NET_STATE_FLAG_RTS; if ((net_state_flags & NET_STATE_FLAG_RUN) && (net_state_flags & NET_STATE_FLAG_CTS)) { net_xchg_reset(); } - } else if (GPIO_REG(GPIO_FALL_IP) & rts_offset) { - GPIO_REG(GPIO_FALL_IP) = rts_offset; + } + if (GPIO_REG(GPIO_RISE_IP) & rts_offset) { + GPIO_REG(GPIO_RISE_IP) = rts_offset; net_state_flags &= ~NET_STATE_FLAG_RTS; } } -static void net_handle_evt(unsigned char type, unsigned char *buffer, uint16_t len) { - unsigned char idx = (type & ~EOS_EVT_MASK) - 1; +static void net_handle_evt(unsigned char type, EOSMessage *msg, uint16_t len) { + unsigned char idx; - if (idx < EOS_NET_MAX_MTYPE) { - net_handler[idx](type, buffer, len); + idx = type & EOS_NET_MTYPE_FLAG_BRIDGE ? EOS_NET_MTYPE_BRIDGE : (type & ~EOS_EVT_MASK); + type &= ~EOS_EVT_MASK; + if (msg && (idx < EOS_NET_MAX_MTYPE)) { + net_handler[idx](type, msg, len); } else { - eos_net_bad_handler(type, buffer, len); + eos_net_bad_handler(type, msg, len); + } + if (msg && msg->buffer) { + eos_net_free(msg, 0); + } else { + eos_net_release(); } } @@ -262,34 +284,48 @@ static int net_acquire(unsigned char reserved) { return ret; } -static void evt_handler_wrapper(unsigned char type, unsigned char *buffer, uint16_t len, unsigned char idx, uint16_t flag) { - int ok; +static void evt_handler_wrapper(unsigned char type, EOSMessage *msg, uint16_t len, uint8_t idx) { + uint16_t flag = (uint16_t)1 << idx; + int rv; - ok = net_acquire(net_wrapper_acq[idx] & flag); - if (ok) { - eos_evtq_get_handler(type)(type, buffer, len); + rv = net_acquire(net_wrapper_acq & flag); + if (rv) { + eos_evtq_get_handler(type)(type, msg, len); eos_net_release(); - net_wrapper_acq[idx] &= ~flag; + net_wrapper_acq &= ~flag; } else { - net_wrapper_acq[idx] |= flag; - eos_evtq_push(type, buffer, len); + rv = eos_evtq_push_widx(type, msg, len, &idx); + if (rv) { + EOS_LOG(EOS_LOG_ERR, "NET WRAPPER EVTQ PUSH ERR:%d\n", rv); + return; + } + flag = (uint16_t)1 << idx; + net_wrapper_acq |= flag; } } -static void evt_handler(unsigned char type, unsigned char *buffer, uint16_t len) { +static void evt_handler(unsigned char type, EOSMessage *msg, uint16_t len, uint8_t _idx) { unsigned char idx = (type & EOS_EVT_MASK) >> 4; - if (idx && (idx <= EOS_EVT_MAX_EVT)) { + if (idx && (idx <= EOS_EVT_MAX)) { uint16_t flag = (uint16_t)1 << (type & ~EOS_EVT_MASK); idx--; if (flag & net_flags_acq[idx]) { - evt_handler_wrapper(type, buffer, len, idx, flag); + evt_handler_wrapper(type, msg, len, _idx); } else { - eos_evtq_get_handler(type)(type, buffer, len); + eos_evtq_get_handler(type)(type, msg, len); } } else { - eos_evtq_bad_handler(type, buffer, len); + eos_evtq_bad_handler(type, msg, len); + } +} + +static void net_flushq(void) { + while (eos_msgq_len(&net_send_q)) { + asm volatile ("wfi"); + set_csr(mstatus, MSTATUS_MIE); + clear_csr(mstatus, MSTATUS_MIE); } } @@ -309,12 +345,55 @@ static void net_wait4cts(void) { } } +static int net_wake(void) { + uint32_t start, timeout; + + start = eos_get_tick(); + timeout = NET_DETECT_TIMEOUT; + while (net_state_flags & NET_STATE_FLAG_SLEEP) { + if (timeout && (eos_tdelta_ms(start) > timeout)) return EOS_ERR_NOTFOUND; + net_xchg_reset(); + eos_sleep(10); + set_csr(mstatus, MSTATUS_MIE); + clear_csr(mstatus, MSTATUS_MIE); + } + + return EOS_OK; +} + +static int net_select(int *dsel) { + int rv; + + *dsel = 0; + if (net_state_flags & NET_STATE_FLAG_ABSENT) return EOS_ERR_NOTFOUND; + if (net_state_flags & NET_STATE_FLAG_SLEEP_REQ) return EOS_ERR_BUSY; + + rv = EOS_OK; + if (!(net_state_flags & NET_STATE_FLAG_RUN)) { + set_csr(mstatus, MSTATUS_MIE); + rv = eos_spi_select(EOS_SPI_DEV_NET); + clear_csr(mstatus, MSTATUS_MIE); + if (rv) return rv; + *dsel = 1; + } + /* wake up remote if sleeping */ + if (net_state_flags & NET_STATE_FLAG_SLEEP) rv = net_wake(); + + return rv; +} + +static void net_deselect(void) { + eos_spi_deselect(); +} + static void net_pause(void) { net_state_flags &= ~NET_STATE_FLAG_RUN; net_wait4xchg(); } static void net_resume(void) { + if (net_state_flags & NET_STATE_FLAG_ABSENT) return; + net_state_flags |= NET_STATE_FLAG_RUN; if (net_state_flags & NET_STATE_FLAG_CTS) { net_xchg_next(NULL); @@ -333,62 +412,87 @@ static void net_stop(void) { int eos_net_init(void) { int i; - eos_msgq_init(&net_send_q, net_sndq_array, EOS_NET_SIZE_BUFQ); - eos_bufq_init(&net_buf_q, net_bufq_array, EOS_NET_SIZE_BUFQ); - for (i=0; i<EOS_NET_SIZE_BUFQ; i++) { + eos_msgq_init(&net_send_q, net_sndq_array, NET_SIZE_BUFQ); + eos_bufq_init(&net_buf_q, net_bufq_array, NET_SIZE_BUFQ); + for (i=0; i<NET_SIZE_BUFQ; i++) { eos_bufq_push(&net_buf_q, net_bufq_buffer[i]); } for (i=0; i<EOS_NET_MAX_MTYPE; i++) { net_handler[i] = eos_net_bad_handler; } - eos_evtq_set_handler(0, evt_handler); + eos_evtq_set_handler_global(evt_handler); eos_evtq_set_handler(EOS_EVT_NET, net_handle_evt); + GPIO_REG(GPIO_PULLUP_EN) |= (1 << NET_PIN_CTS); GPIO_REG(GPIO_INPUT_EN) |= (1 << NET_PIN_CTS); - GPIO_REG(GPIO_RISE_IE) |= (1 << NET_PIN_CTS); + GPIO_REG(GPIO_FALL_IE) |= (1 << NET_PIN_CTS); eos_intr_set(INT_GPIO_BASE + NET_PIN_CTS, IRQ_PRIORITY_NET_CTS, net_handle_cts); + /* XXX: pull-up not needed for new board */ + GPIO_REG(GPIO_PULLUP_EN) |= (1 << NET_PIN_RTS); GPIO_REG(GPIO_INPUT_EN) |= (1 << NET_PIN_RTS); GPIO_REG(GPIO_RISE_IE) |= (1 << NET_PIN_RTS); GPIO_REG(GPIO_FALL_IE) |= (1 << NET_PIN_RTS); eos_intr_set(INT_GPIO_BASE + NET_PIN_RTS, IRQ_PRIORITY_NET_RTS, net_handle_rts); - /* set initial state */ - clear_csr(mstatus, MSTATUS_MIE); - if (GPIO_REG(GPIO_INPUT_VAL) & (1 << NET_PIN_CTS)) net_state_flags |= NET_STATE_FLAG_CTS; - if (GPIO_REG(GPIO_INPUT_VAL) & (1 << NET_PIN_RTS)) net_state_flags |= NET_STATE_FLAG_RTS; - set_csr(mstatus, MSTATUS_MIE); - return EOS_OK; } int eos_net_run(void) { uint8_t wakeup_cause; + int rv, rst; + rv = EOS_OK; net_start(); wakeup_cause = eos_pwr_wakeup_cause(); + rst = (wakeup_cause == EOS_PWR_WAKE_RST); + clear_csr(mstatus, MSTATUS_MIE); - if (wakeup_cause != EOS_PWR_WAKE_RST) { - if (wakeup_cause != EOS_PWR_WAKE_PIN) { - net_xchg_wake(); - } - if (!(net_state_flags & NET_STATE_FLAG_CTS)) { - while (!(GPIO_REG(GPIO_RISE_IP) & (1 << NET_PIN_CTS))) { - asm volatile ("wfi"); + if (rst) { + uint32_t start, timeout; + + start = eos_get_tick(); + timeout = NET_DETECT_TIMEOUT; + while (GPIO_REG(GPIO_INPUT_VAL) & (1 << NET_PIN_CTS)) { + if (timeout && (eos_tdelta_ms(start) > timeout)) { + rv = EOS_ERR_NOTFOUND; + break; } - GPIO_REG(GPIO_RISE_IP) = (1 << NET_PIN_CTS); } - net_xchg_reset(); + } else { + if (eos_aon_load4net()) { + /* device previously declared as absent */ + rv = EOS_ERR_NOTFOUND; + } else { + net_state_flags |= NET_STATE_FLAG_SLEEP; + } + } + if (!rv) { + /* set initial state */ + if (!(GPIO_REG(GPIO_INPUT_VAL) & (1 << NET_PIN_CTS))) net_state_flags |= NET_STATE_FLAG_CTS; + if (!(GPIO_REG(GPIO_INPUT_VAL) & (1 << NET_PIN_RTS))) net_state_flags |= NET_STATE_FLAG_RTS; + GPIO_REG(GPIO_PULLUP_EN) &= ~(1 << NET_PIN_CTS); + /* wake up remote */ + if (!rst) rv = net_wake(); + if (!rv) net_resume(); + } else { + net_state_flags |= NET_STATE_FLAG_ABSENT; + EOS_LOG(EOS_LOG_ERR, "NET DEVICE ABSENT\n"); } - net_resume(); set_csr(mstatus, MSTATUS_MIE); - return EOS_OK; + /* save absent state */ + if (rst) eos_aon_save4net(!!rv); + + if (rv) net_stop(); + return rv; } void eos_net_start(void) { + if (net_state_flags & NET_STATE_FLAG_ABSENT) return; + net_start(); clear_csr(mstatus, MSTATUS_MIE); @@ -397,6 +501,8 @@ void eos_net_start(void) { } void eos_net_stop(void) { + if (net_state_flags & NET_STATE_FLAG_ABSENT) return; + clear_csr(mstatus, MSTATUS_MIE); net_pause(); set_csr(mstatus, MSTATUS_MIE); @@ -404,64 +510,58 @@ void eos_net_stop(void) { net_stop(); } -int eos_net_sleep(uint32_t timeout) { - uint32_t start; - uint8_t done = 0; - int rv = EOS_OK; +int eos_net_sleep(void) { + int dsel = 0; + int rv; clear_csr(mstatus, MSTATUS_MIE); - if (!(net_state_flags & NET_STATE_FLAG_RUN)) rv = EOS_ERR; + rv = net_select(&dsel); + if (rv) { + set_csr(mstatus, MSTATUS_MIE); + return rv; + } + net_state_flags |= NET_STATE_FLAG_SLEEP_REQ; + net_flushq(); + net_pause(); + net_wait4cts(); + net_xchg_sleep_req(); + net_resume(); set_csr(mstatus, MSTATUS_MIE); + if (dsel) net_deselect(); - if (rv) return rv; - - start = eos_get_tick(); - do { - if (eos_tdelta_ms(start) > timeout) return EOS_ERR_TIMEOUT; - clear_csr(mstatus, MSTATUS_MIE); - eos_evtq_flush_isr(); - done = (eos_msgq_len(&net_send_q) == 0); - done = done && (!(net_state_flags & NET_STATE_FLAG_RTS) && (net_state_flags & NET_STATE_FLAG_CTS)); - if (done) done = (net_xchg_sleep() == EOS_OK); - if (!done) { - asm volatile ("wfi"); - set_csr(mstatus, MSTATUS_MIE); - } - } while (!done); - - while (!(GPIO_REG(GPIO_RISE_IP) & (1 << NET_PIN_CTS))) { - if (eos_tdelta_ms(start) > timeout) { - rv = EOS_ERR_TIMEOUT; - break; - } - asm volatile ("wfi"); - } + return EOS_OK; +} - if (!rv) { - GPIO_REG(GPIO_RISE_IP) = (1 << NET_PIN_CTS); - net_state_flags &= ~NET_STATE_FLAG_RUN; - } +int eos_net_sleep_rdy(void) { + int rv; + clear_csr(mstatus, MSTATUS_MIE); + rv = !!(net_state_flags & NET_STATE_FLAG_SLEEP); set_csr(mstatus, MSTATUS_MIE); return rv; } -void eos_net_bad_handler(unsigned char type, unsigned char *buffer, uint16_t len) { - eos_evtq_bad_handler(type, buffer, len); - if (buffer) eos_net_free(buffer, 0); +void eos_net_wake(void) { + clear_csr(mstatus, MSTATUS_MIE); + net_state_flags &= ~NET_STATE_FLAG_SLEEP_REQ; + set_csr(mstatus, MSTATUS_MIE); +} + +void eos_net_bad_handler(unsigned char type, EOSMessage *msg, uint16_t len) { + eos_evtq_bad_handler(type, msg, len); } void eos_net_set_handler(unsigned char mtype, eos_evt_handler_t handler) { if (handler == NULL) handler = eos_net_bad_handler; - if (mtype && (mtype <= EOS_NET_MAX_MTYPE)) net_handler[mtype - 1] = handler; + if (mtype < EOS_NET_MAX_MTYPE) net_handler[mtype] = handler; } -void eos_net_acquire_for_evt(unsigned char type, char acq) { +void eos_net_acquire_for_evt(unsigned char type, int acq) { unsigned char idx = (type & EOS_EVT_MASK) >> 4; uint16_t flag = type & ~EOS_EVT_MASK ? (uint16_t)1 << (type & ~EOS_EVT_MASK) : 0xFFFF; - if (idx && (idx <= EOS_EVT_MAX_EVT)) { + if (idx && (idx <= EOS_EVT_MAX)) { idx--; net_flags_acq[idx] &= ~flag; if (acq) net_flags_acq[idx] |= flag; @@ -469,7 +569,9 @@ void eos_net_acquire_for_evt(unsigned char type, char acq) { } void eos_net_acquire(void) { - unsigned char acq = net_acquire(0); + int acq; + + acq = net_acquire(0); if (!acq) net_acquire(1); } @@ -482,116 +584,118 @@ void eos_net_release(void) { set_csr(mstatus, MSTATUS_MIE); } -unsigned char *eos_net_alloc(void) { - unsigned char *ret = NULL; +void eos_net_alloc(EOSMessage *msg) { + msg->buffer = NULL; + msg->size = 0; - while (ret == NULL) { + while (msg->buffer == NULL) { clear_csr(mstatus, MSTATUS_MIE); if (net_state_next_buf) { - ret = net_state_next_buf; + msg->buffer = net_state_next_buf; + msg->size = EOS_NET_MTU; net_state_next_buf = NULL; } else { asm volatile ("wfi"); } set_csr(mstatus, MSTATUS_MIE); } - - return ret; } -void eos_net_free(unsigned char *buffer, unsigned char more) { - uint8_t do_release = 1; - +void eos_net_free(EOSMessage *msg, int more) { clear_csr(mstatus, MSTATUS_MIE); if ((more || net_state_next_cnt) && (net_state_next_buf == NULL)) { - net_state_next_buf = buffer; + net_state_next_buf = msg->buffer; } else { + int do_release = 1; + if ((net_state_flags & NET_STATE_FLAG_RUN) && (net_state_flags & NET_STATE_FLAG_CTS)) { - do_release = net_xchg_next(buffer); + do_release = net_xchg_next(msg); } if (do_release) { - eos_bufq_push(&net_buf_q, buffer); + eos_bufq_push(&net_buf_q, msg->buffer); } } + msg->buffer = NULL; + msg->size = 0; set_csr(mstatus, MSTATUS_MIE); } -static int net_xchg(unsigned char *type, unsigned char *buffer, uint16_t *len, unsigned char flags) { +static int net_xchg(unsigned char *type, EOSMessage *msg, uint16_t *len, unsigned char flags) { int rv = EOS_OK; int sync = 0, dsel = 0; - unsigned char _type = *type; + unsigned char _type = *type & EOS_NET_MTYPE_MASK; uint16_t _len = *len; - if (flags & EOS_NET_FLAG_ONEW) _type |= EOS_NET_MTYPE_FLAG_ONEW; + if ((flags & EOS_NET_FLAG_REPL) && (_type & EOS_NET_MTYPE_FLAG_BRIDGE)) return EOS_ERR; + + if (flags & EOS_NET_FLAG_REPL) flags |= EOS_NET_FLAG_SYNC; + + if (flags & EOS_NET_FLAG_MORE) _type |= EOS_NET_MTYPE_FLAG_ONEW; if (flags & EOS_NET_FLAG_REPL) _type |= EOS_NET_MTYPE_FLAG_REPL; if (flags & EOS_NET_FLAG_SYNC) sync = 1; clear_csr(mstatus, MSTATUS_MIE); - if ((flags & EOS_NET_FLAG_ONEW) && !(net_state_flags & NET_STATE_FLAG_RUN)) sync = 1; - - if (sync && !(net_state_flags & NET_STATE_FLAG_RUN)) { - set_csr(mstatus, MSTATUS_MIE); - - rv = eos_spi_select(EOS_SPI_DEV_NET); - if (rv) return rv; - - dsel = 1; - clear_csr(mstatus, MSTATUS_MIE); - } + rv = net_select(&dsel); + if (rv) goto net_xchg_fin; + if (dsel) sync = 1; if (sync) { + _type |= EOS_NET_MTYPE_FLAG_ONEW; net_pause(); net_wait4cts(); - if (flags & EOS_NET_FLAG_SYNC) { - net_state_flags |= NET_STATE_FLAG_SYNC; + net_state_flags |= NET_STATE_FLAG_SYNC; + net_xchg_start(_type, msg, _len); + if (flags & EOS_NET_FLAG_REPL) { + net_wait4cts(); + net_xchg_start(0, msg, 0); } - net_xchg_start(_type, buffer, _len); - if (flags & EOS_NET_FLAG_SYNC) { - if (flags & EOS_NET_FLAG_REPL) { - net_wait4cts(); - net_xchg_start(0, buffer, 0); + net_wait4xchg(); + net_state_flags &= ~NET_STATE_FLAG_SYNC; + if (flags & EOS_NET_FLAG_REPL) { + *type = 0; + *len = 0; + rv = (net_state_flags & NET_STATE_FLAG_ERR_SIZE) ? EOS_ERR_SIZE : EOS_OK; + if (!rv) { + *type = net_state_type & EOS_NET_MTYPE_MASK; + *len = net_state_len_rx; } - net_wait4xchg(); - net_state_flags &= ~NET_STATE_FLAG_SYNC; - *type = (net_state_type & ~EOS_NET_MTYPE_FLAG_MASK); - *len = net_state_len_rx; } net_resume(); } else { if ((net_state_flags & NET_STATE_FLAG_RUN) && (net_state_flags & NET_STATE_FLAG_CTS)) { - net_xchg_start(_type, buffer, _len); + net_xchg_start(_type, msg, _len); } else { - rv = eos_msgq_push(&net_send_q, _type, buffer, _len); - if (rv) eos_bufq_push(&net_buf_q, buffer); + rv = eos_msgq_push(&net_send_q, _type, msg, _len); } } +net_xchg_fin: set_csr(mstatus, MSTATUS_MIE); - if (dsel) eos_spi_deselect(); + if (!(flags & EOS_NET_FLAG_SYNC)) { + if (sync || rv) { + eos_net_free(msg, !!(flags & EOS_NET_FLAG_MORE)); + } else { + msg->buffer = NULL; + msg->size = 0; + } + } + if (dsel) net_deselect(); return rv; } -int eos_net_xchg(unsigned char *type, unsigned char *buffer, uint16_t *len) { - return net_xchg(type, buffer, len, (EOS_NET_FLAG_ONEW | EOS_NET_FLAG_SYNC | EOS_NET_FLAG_REPL)); +int eos_net_send(unsigned char type, EOSMessage *msg, uint16_t len, int more) { + return net_xchg(&type, msg, &len, more ? EOS_NET_FLAG_MORE : 0); } -int eos_net_send(unsigned char type, unsigned char *buffer, uint16_t len) { - return net_xchg(&type, buffer, &len, (EOS_NET_FLAG_ONEW | EOS_NET_FLAG_SYNC)); +int eos_net_send_sync(unsigned char type, EOSMessage *msg, uint16_t len) { + return net_xchg(&type, msg, &len, EOS_NET_FLAG_SYNC); } -int eos_net_send_async(unsigned char type, unsigned char *buffer, uint16_t len, unsigned char more) { - int rv; - - rv = net_xchg(&type, buffer, &len, more ? EOS_NET_FLAG_ONEW : 0); - if (rv) eos_net_free(buffer, more); - return rv; +int eos_net_xchg(unsigned char *type, EOSMessage *msg, uint16_t *len) { + return net_xchg(type, msg, len, EOS_NET_FLAG_REPL); } -int _eos_net_send(unsigned char type, unsigned char *buffer, uint16_t len, unsigned char async, unsigned char more) { - if (async) { - return eos_net_send_async(type, buffer, len, more); - } else { - return eos_net_send(type, buffer, len); - } +int _eos_net_send(unsigned char type, EOSMessage *msg, uint16_t len, unsigned char flags) { + return net_xchg(&type, msg, &len, flags); } diff --git a/fw/fe310/eos/dev/net.h b/fw/fe310/eos/dev/net.h index ead88b6..ad544a3 100644 --- a/fw/fe310/eos/dev/net.h +++ b/fw/fe310/eos/dev/net.h @@ -2,47 +2,45 @@ #include "../event.h" -/* common */ #define EOS_NET_MTU 1500 -#define EOS_NET_SIZE_BUF EOS_NET_MTU -#define EOS_NET_MTYPE_SOCK 1 -#define EOS_NET_MTYPE_RNG 3 -#define EOS_NET_MTYPE_POWER 4 +#define EOS_NET_MTYPE_BRIDGE 0 /* handler only */ +#define EOS_NET_MTYPE_WIFI 1 +#define EOS_NET_MTYPE_CELL 2 +#define EOS_NET_MTYPE_SOCK 3 +#define EOS_NET_MTYPE_RNG 4 -#define EOS_NET_MTYPE_WIFI 5 -#define EOS_NET_MTYPE_CELL 6 -#define EOS_NET_MTYPE_SIP 7 -#define EOS_NET_MTYPE_APP 8 +#define EOS_NET_MAX_MTYPE 5 -#define EOS_NET_MAX_MTYPE 8 +#define EOS_NET_MTYPE_SLEEP 0x20 /* does not have net handler */ -#define EOS_NET_MTYPE_FLAG_ONEW 0x40 -#define EOS_NET_MTYPE_FLAG_REPL 0x80 -#define EOS_NET_MTYPE_FLAG_MASK 0xc0 +#define EOS_NET_MTYPE_FLAG_ONEW 0x80 +#define EOS_NET_MTYPE_FLAG_REPL 0x40 +#define EOS_NET_MTYPE_FLAG_BRIDGE 0x08 -/* fe310 specific */ -#define EOS_NET_SIZE_BUFQ 2 +#define EOS_NET_MTYPE_MASK 0x0F /* must be the same as ~EOS_EVT_MASK */ -#define EOS_NET_FLAG_ONEW 0x1 -#define EOS_NET_FLAG_SYNC 0x2 -#define EOS_NET_FLAG_REPL 0x4 +#define EOS_NET_FLAG_MORE 0x01 +#define EOS_NET_FLAG_SYNC 0x02 +#define EOS_NET_FLAG_REPL 0x04 int eos_net_init(void); int eos_net_run(void); void eos_net_start(void); void eos_net_stop(void); -int eos_net_sleep(uint32_t timeout); +int eos_net_sleep(void); +int eos_net_sleep_rdy(void); +void eos_net_wake(void); -void eos_net_bad_handler(unsigned char type, unsigned char *buffer, uint16_t len); +void eos_net_bad_handler(unsigned char type, EOSMessage *msg, uint16_t len); void eos_net_set_handler(unsigned char type, eos_evt_handler_t handler); -void eos_net_acquire_for_evt(unsigned char type, char acq); +void eos_net_acquire_for_evt(unsigned char type, int acq); void eos_net_acquire(void); void eos_net_release(void); -unsigned char *eos_net_alloc(void); -void eos_net_free(unsigned char *buffer, unsigned char more); -int eos_net_xchg(unsigned char *type, unsigned char *buffer, uint16_t *len); -int eos_net_send(unsigned char type, unsigned char *buffer, uint16_t len); -int eos_net_send_async(unsigned char type, unsigned char *buffer, uint16_t len, unsigned char more); -int _eos_net_send(unsigned char type, unsigned char *buffer, uint16_t len, unsigned char async, unsigned char more); +void eos_net_alloc(EOSMessage *msg); +void eos_net_free(EOSMessage *msg, int more); +int eos_net_send(unsigned char type, EOSMessage *msg, uint16_t len, int more); +int eos_net_send_sync(unsigned char type, EOSMessage *msg, uint16_t len); +int eos_net_xchg(unsigned char *type, EOSMessage *msg, uint16_t *len); +int _eos_net_send(unsigned char type, EOSMessage *msg, uint16_t len, unsigned char flags);
\ No newline at end of file diff --git a/fw/fe310/eos/dev/pwr.c b/fw/fe310/eos/dev/pwr.c index c6537cb..b60e35c 100644 --- a/fw/fe310/eos/dev/pwr.c +++ b/fw/fe310/eos/dev/pwr.c @@ -2,6 +2,8 @@ #include <stdint.h> #include "eos.h" +#include "log.h" +#include "event.h" #include "soc/pwr.h" #include "eve/eve.h" #include "eve/eve_touch_engine.h" @@ -15,34 +17,31 @@ #include "pwr.h" +static void pwr_sleep_rdy(void) { + if ((eos_evtq_len() == 0) && eos_net_sleep_rdy()) { + eos_flash_norm(); #ifdef EOS_DEBUG -#include <stdio.h> + EOS_LOG(EOS_LOG_INFO, "PWR SLEEP\n"); + eos_sleep(100); #endif + eos_pwr_sleep(); + } +} void eos_pwr_sys_sleep(void) { int rv; rv = eos_lcd_sleep(); -#ifdef EOS_DEBUG - if (rv) printf("PWR SLEEP: LCD SLEEP ERR:%d\n", rv); -#endif + if (rv) EOS_LOG(EOS_LOG_ERR, "PWR SLEEP: LCD SLEEP ERR:%d\n", rv); rv = eos_ctp_sleep(); -#ifdef EOS_DEBUG - if (rv) printf("PWR SLEEP: CTP SLEEP ERR:%d\n", rv); -#endif + if (rv) EOS_LOG(EOS_LOG_ERR, "PWR SLEEP: CTP SLEEP ERR:%d\n", rv); rv = eos_eve_sleep(); -#ifdef EOS_DEBUG - if (rv) printf("PWR SLEEP: EVE SLEEP ERR:%d\n", rv); -#endif - - rv = eos_net_sleep(1000); -#ifdef EOS_DEBUG - if (rv) printf("PWR SLEEP: NET SLEEP ERR:%d\n", rv); -#endif + if (rv) EOS_LOG(EOS_LOG_ERR, "PWR SLEEP: EVE SLEEP ERR:%d\n", rv); - eos_flash_norm(); + eos_evtq_set_loopf(pwr_sleep_rdy); - eos_pwr_sleep(); + rv = eos_net_sleep(); + if (rv) EOS_LOG(EOS_LOG_ERR, "PWR SLEEP: NET SLEEP REQ ERR:%d\n", rv); } diff --git a/fw/fe310/eos/dev/sdcard.c b/fw/fe310/eos/dev/sdcard.c index 1edad96..ebdc883 100644 --- a/fw/fe310/eos/dev/sdcard.c +++ b/fw/fe310/eos/dev/sdcard.c @@ -1,38 +1,48 @@ #include <stdlib.h> #include <stdint.h> +#include "encoding.h" +#include "platform.h" +#include "board.h" + #include "eos.h" -#include "board.h" #include "spi.h" #include "drv/sdcard.h" #include "sdcard.h" -#ifdef EOS_DEBUG -#include <stdio.h> -#endif +#define SDC_DETECT_TIMEOUT 1000 -void eos_sdc_insert(int sdc_det) { - int rv; +int eos_sdc_init(void) { + clear_csr(mstatus, MSTATUS_MIE); + GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << SPI_CSPIN_SDC); + set_csr(mstatus, MSTATUS_MIE); + GPIO_REG(GPIO_OUTPUT_EN) |= (1 << SPI_CSPIN_SDC); - rv = EOS_OK; + return EOS_OK; +} + +int eos_sdc_insert(int sdc_det, uint32_t timeout) { + if (timeout == 0) timeout = SDC_DETECT_TIMEOUT; if (sdc_det) { + int rv; + eos_spi_set_div(EOS_SPI_DEV_SDC, 1024); // 100 - 400 kHz rv = eos_spi_select(EOS_SPI_DEV_SDC); if (rv) goto sdc_insert_fin; - rv = sdc_init(1000); + rv = sdc_init(timeout); + if (rv) rv = EOS_ERR_NOTFOUND; eos_spi_deselect(); sdc_insert_fin: eos_spi_set_div(EOS_SPI_DEV_SDC, SPI_DIV_SDC); + if (rv) return rv; } else { sdc_clear(); } -#ifdef EOS_DEBUG - if (rv) printf("SDC INSERT ERR:%d\n", rv); -#endif + return EOS_OK; } diff --git a/fw/fe310/eos/dev/sdcard.h b/fw/fe310/eos/dev/sdcard.h index cefc304..4b338ea 100644 --- a/fw/fe310/eos/dev/sdcard.h +++ b/fw/fe310/eos/dev/sdcard.h @@ -1,3 +1,4 @@ #include <stdint.h> -void eos_sdc_insert(int sdc_det); +int eos_sdc_init(void); +int eos_sdc_insert(int sdc_det, uint32_t timeout); diff --git a/fw/fe310/eos/dev/spi.c b/fw/fe310/eos/dev/spi.c index fef00e1..ea6d74a 100644 --- a/fw/fe310/eos/dev/spi.c +++ b/fw/fe310/eos/dev/spi.c @@ -5,7 +5,7 @@ #include "platform.h" #include "eos.h" -#include "msgq.h" +#include "log.h" #include "event.h" #include "board.h" @@ -13,33 +13,36 @@ #include "soc/interrupt.h" #include "soc/spi.h" #include "soc/spi_priv.h" +#include "soc/spi9bit.h" #include "net.h" #include "egpio.h" +#include "egpio_priv.h" #include "spi.h" #include "spi_cfg.h" -#ifdef EOS_DEBUG -#include <stdio.h> -#endif - static unsigned char spi_dstack[EOS_SPI_MAX_DSTACK]; static unsigned char spi_dstack_len; -static uint16_t spi_div[EOS_SPI_MAX_DEV]; +static uint16_t spi_div[SPI_MAX_DEV]; static uint8_t spi_dev(void) { return spi_dstack_len ? spi_dstack[spi_dstack_len - 1] : EOS_SPI_DEV_NET; } -static void spi_stop(unsigned char dev) { +static int spi_stop(unsigned char dev) { if (dev == EOS_SPI_DEV_NET) { eos_net_stop(); - } else if (spi_cfg[dev].flags & SPI_DEV_FLAG_9BIT) { - eos_spi_enable(); } else { - eos_spi_stop(); + if (eos_spi_get_cs()) return EOS_ERR_BUSY; + if (spi_cfg[dev].flags & SPI_DEV_FLAG_9BIT) { + eos_spi9bit_stop(); + eos_spi_enable(); + } else { + eos_spi_stop(); + } } + return EOS_OK; } static void spi_start(unsigned char dev) { @@ -48,6 +51,7 @@ static void spi_start(unsigned char dev) { } else if (spi_cfg[dev].flags & SPI_DEV_FLAG_9BIT) { eos_spi_configure(spi_div[dev], spi_cfg[dev].csid, spi_cfg[dev].cspin, spi_cfg[dev].evt); eos_spi_disable(); + eos_spi9bit_start(); } else { eos_spi_start(spi_div[dev], spi_cfg[dev].csid, spi_cfg[dev].cspin, spi_cfg[dev].evt); } @@ -56,7 +60,8 @@ static void spi_start(unsigned char dev) { int eos_spi_dev_init(void) { int i; - for (i=0; i<EOS_SPI_MAX_DEV; i++) { + /* dev modules are responsibile for configuring cs gpio */ + for (i=0; i<SPI_MAX_DEV; i++) { spi_div[i] = spi_cfg[i].div; } @@ -71,14 +76,10 @@ int eos_spi_select(unsigned char dev) { int rv; int dsel; - if (eos_spi_cs_get()) rv = EOS_ERR_BUSY; - if (!rv && (spi_dstack_len == EOS_SPI_MAX_DSTACK)) rv = EOS_ERR_FULL; - - if (rv) { -#ifdef EOS_DEBUG - printf("SPI SELECT DEV:%d ERR:%d\n", dev, rv); -#endif - return rv; + rv = EOS_OK; + if (spi_dstack_len == EOS_SPI_MAX_DSTACK) { + rv = EOS_ERR_FULL; + goto spi_select_fin; } dsel = 1; @@ -87,13 +88,21 @@ int eos_spi_select(unsigned char dev) { dsel = 0; } - if (dsel) spi_stop(spi_dev()); + if (dsel) { + rv = spi_stop(spi_dev()); + if (rv) goto spi_select_fin; + } spi_dstack[spi_dstack_len] = dev; spi_dstack_len++; if (dsel) spi_start(dev); +spi_select_fin: + if (rv) { + EOS_LOG(EOS_LOG_ERR, "SPI SELECT DEV:%d ERR:%d\n", dev, rv); + return rv; + } return EOS_OK; } @@ -101,23 +110,25 @@ void eos_spi_deselect(void) { int rv; int dsel; - if (eos_spi_cs_get()) rv = EOS_ERR_BUSY; - if (!rv && (spi_dstack_len == 0)) rv = EOS_ERR_EMPTY; - - if (rv) { -#ifdef EOS_DEBUG - printf("SPI DESELECT ERR:%d\n", rv); -#endif - return; + rv = EOS_OK; + if (spi_dstack_len == 0) { + rv = EOS_ERR_EMPTY; + goto spi_deselect_fin; } dsel = !(spi_dev() & EOS_SPI_DEV_FLAG_NDSEL); - if (dsel) spi_stop(spi_dev()); + if (dsel) { + rv = spi_stop(spi_dev()); + if (rv) goto spi_deselect_fin; + } spi_dstack_len--; spi_dstack[spi_dstack_len] = 0xff; if (dsel) spi_start(spi_dev()); + +spi_deselect_fin: + if (rv) EOS_LOG(EOS_LOG_ERR, "SPI DESELECT ERR:%d\n", rv); } void eos_spi_dev_configure(unsigned char dev) { diff --git a/fw/fe310/eos/dev/spi_cfg.h b/fw/fe310/eos/dev/spi_cfg.h index 6ef92aa..906de24 100644 --- a/fw/fe310/eos/dev/spi_cfg.h +++ b/fw/fe310/eos/dev/spi_cfg.h @@ -10,9 +10,9 @@ typedef struct { #define SPI_DEV_FLAG_9BIT 0x01 -#define EOS_SPI_MAX_DEV 6 +#define SPI_MAX_DEV 6 -static const SPIConfig spi_cfg[EOS_SPI_MAX_DEV] = { +static const SPIConfig spi_cfg[SPI_MAX_DEV] = { { // DEV_NET .div = SPI_DIV_NET, .csid = SPI_CSID_NET, @@ -32,14 +32,14 @@ static const SPIConfig spi_cfg[EOS_SPI_MAX_DEV] = { .csid = SPI_CSID_SDC, .cspin = SPI_CSPIN_SDC, .flags = 0, - .evt = EOS_SPI_EVT_SDC, + .evt = EOS_SPI_ETYPE_SDC, }, { // DEV_CAM .div = SPI_DIV_CAM, .csid = SPI_CSID_CAM, .cspin = SPI_CSPIN_CAM, .flags = 0, - .evt = EOS_SPI_EVT_CAM, + .evt = EOS_SPI_ETYPE_CAM, }, { // DEV_HPAMP .div = SPI_DIV_HPAMP, |