1 files changed, 30 insertions, 18 deletions

diff --git a/fw/fe310/eos/soc/spi.c b/fw/fe310/eos/soc/spi.c
index 05c9448..2c36109 100644
--- a/fw/fe310/eos/soc/spi.c
+++ b/fw/fe310/eos/soc/spi.c
@@ -21,6 +21,8 @@
 
 #define SPI_FLAG_XCHG           0x10
 
+#define SPI_CSID_NONE           1
+
 #define MIN(X, Y)               (((X) < (Y)) ? (X) : (Y))
 #define MAX(X, Y)               (((X) > (Y)) ? (X) : (Y))
 
@@ -52,19 +54,7 @@ int eos_spi_init(uint8_t wakeup_cause) {
         evt_handler[i] = eos_evtq_bad_handler;
     }
     eos_evtq_set_handler(EOS_EVT_SPI, spi_handle_evt);
-    eos_intr_set(INT_SPI1_BASE, IRQ_PRIORITY_SPI_XCHG, NULL);
-
-    GPIO_REG(GPIO_OUTPUT_VAL)   &= ~(1 << IOF_SPI1_SCK);
-    GPIO_REG(GPIO_OUTPUT_VAL)   |=  (1 << IOF_SPI1_MOSI);
-
-    GPIO_REG(GPIO_INPUT_EN)     &= ~(1 << IOF_SPI1_SCK);
-    GPIO_REG(GPIO_OUTPUT_EN)    |=  (1 << IOF_SPI1_SCK);
-
-    GPIO_REG(GPIO_INPUT_EN)     &= ~(1 << IOF_SPI1_MOSI);
-    GPIO_REG(GPIO_OUTPUT_EN)    |=  (1 << IOF_SPI1_MOSI);
-
-    GPIO_REG(GPIO_INPUT_EN)     |=  (1 << IOF_SPI1_MISO);
-    GPIO_REG(GPIO_OUTPUT_EN)    &= ~(1 << IOF_SPI1_MISO);
+    eos_intr_set_priority(INT_SPI1_BASE, IRQ_PRIORITY_SPI_XCHG);
 
     SPI1_REG(SPI_REG_SCKMODE) = SPI_MODE0;
     SPI1_REG(SPI_REG_FMT) = SPI_FMT_PROTO(SPI_PROTO_S) |
@@ -72,25 +62,34 @@ int eos_spi_init(uint8_t wakeup_cause) {
       SPI_FMT_DIR(SPI_DIR_RX) |
       SPI_FMT_LEN(8);
 
-    GPIO_REG(GPIO_IOF_SEL)      &= ~SPI_IOF_MASK;
-    GPIO_REG(GPIO_IOF_EN)       |=  SPI_IOF_MASK;
+    /* for spi 9bit protocol */
+    GPIO_REG(GPIO_OUTPUT_EN)    |=  (1 << IOF_SPI1_SCK);
+    GPIO_REG(GPIO_OUTPUT_EN)    |=  (1 << IOF_SPI1_MOSI);
+    GPIO_REG(GPIO_INPUT_EN)     |=  (1 << IOF_SPI1_MISO);
+
+    eos_spi_enable();
 
     // There is no way here to change the CS polarity.
     // SPI1_REG(SPI_REG_CSDEF) = 0xFFFF;
     return EOS_OK;
 }
 
-void eos_spi_start(uint16_t div, uint8_t csid, uint8_t cspin, unsigned char evt) {
+void eos_spi_configure(uint16_t div, int8_t csid, int8_t cspin, unsigned char evt) {
     spi_state_flags = 0;
     spi_evt = evt;
     SPI1_REG(SPI_REG_SCKDIV) = div;
-    SPI1_REG(SPI_REG_CSID) = csid;
-    if (csid != SPI_CSID_NONE) {
+    if (csid != -1) {
+        SPI1_REG(SPI_REG_CSID) = csid;
         SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
     } else {
         spi_cspin = cspin;
+        SPI1_REG(SPI_REG_CSID) = SPI_CSID_NONE;
         SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_OFF;
     }
+}
+
+void eos_spi_start(uint16_t div, int8_t csid, int8_t cspin, unsigned char evt) {
+    eos_spi_configure(div, csid, cspin, evt);
     eos_intr_set_handler(INT_SPI1_BASE, eos_spi_handle_xchg);
 }
 
@@ -100,6 +99,19 @@ void eos_spi_stop(void) {
     spi_evt = 0;
 }
 
+void eos_spi_enable(void) {
+    eos_intr_enable(INT_SPI1_BASE);
+
+    GPIO_REG(GPIO_IOF_SEL)      &= ~SPI_IOF_MASK;
+    GPIO_REG(GPIO_IOF_EN)       |=  SPI_IOF_MASK;
+}
+
+void eos_spi_disable(void) {
+    GPIO_REG(GPIO_IOF_EN)       &= ~SPI_IOF_MASK;
+
+    eos_intr_disable(INT_SPI1_BASE);
+}
+
 void eos_spi_set_handler(unsigned char evt, eos_evt_handler_t handler) {
     if (handler == NULL) handler = eos_evtq_bad_handler;
     if (evt && (evt <= EOS_SPI_MAX_EVT)) evt_handler[evt - 1] = handler;