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path: root/fw/fe310/eos/soc/trap_entry.S
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Diffstat (limited to 'fw/fe310/eos/soc/trap_entry.S')
-rw-r--r--fw/fe310/eos/soc/trap_entry.S205
1 files changed, 50 insertions, 155 deletions
diff --git a/fw/fe310/eos/soc/trap_entry.S b/fw/fe310/eos/soc/trap_entry.S
index 98f9267..19f4502 100644
--- a/fw/fe310/eos/soc/trap_entry.S
+++ b/fw/fe310/eos/soc/trap_entry.S
@@ -28,12 +28,10 @@
#define INT_PWM1_BASE 44
#define INT_PWM2_BASE 48
-#define I2S_FMT (0*4)
-#define I2S_MODE (1*4)
-#define I2S_MIC_WM (2*4)
-#define I2S_SPK_WM (3*4)
-#define I2S_MIC_EVT (4*4)
-#define I2S_SPK_EVT (5*4)
+#define I2S_MIC_WM (0*4)
+#define I2S_SPK_WM (1*4)
+#define I2S_MIC_EVT (2*4)
+#define I2S_SPK_EVT (3*4)
#include "board.h"
#include "irq_def.h"
@@ -57,8 +55,8 @@ eos_trap_vector:
STORE x22, 6*REGBYTES(sp)
STORE x23, 7*REGBYTES(sp)
STORE x24, 8*REGBYTES(sp)
- STORE x25, 9*REGBYTES(sp) # channel: 0 - left; 1 - right
- STORE x26, 10*REGBYTES(sp) # format: 0 - PCM16; 1 - ALAW
+ STORE x25, 9*REGBYTES(sp)
+ STORE x26, 10*REGBYTES(sp) # unused
STORE x27, 11*REGBYTES(sp) # _eos_i2s_drvr addr
csrr x8, mcause
@@ -66,7 +64,7 @@ eos_trap_vector:
bne x8, x18, handle_intr
li x18, PLIC_CLAIM
lw x9, 0(x18)
- li x18, I2S_IRQ_SD_ID
+ li x18, I2S_IRQ_ID
beq x9, x18, i2s_handle_sd
j handle_intr
@@ -82,30 +80,22 @@ evtq_push:
addi x20, x20, -1
and x20, x20, x19
+
+ addi x19, x19, 1
+ sb x19, MSGQ_OFF_IDXW(x9)
+
li x18, MSGQ_ITEM_SIZE
mul x20, x20, x18
lw x21, MSGQ_OFF_ARRAY(x9)
add x21, x21, x20
-
- addi x19, x19, 1
- sb x19, MSGQ_OFF_IDXW(x9)
jalr x0, x22
0:
- mv x20, x0
- jalr x0, x21
+ mv x21, x0
+ jalr x0, x22
i2s_handle_sd:
- # store channel bit to x25
- li x18, I2S_CTRL_ADDR_WS
- lw x18, PWM_CFG(x18)
- # 29th - pwmcmp1ip bit
- li x19, (1 << 29)
- and x25, x18, x19
- srli x25, x25, 29
-
la x27, _eos_i2s_drvr
- lw x26, I2S_FMT(x27)
i2s_abuf_pop:
# pop from spk buf -> x8
@@ -115,107 +105,55 @@ i2s_abuf_pop:
lhu x20, I2S_ABUF_OFF_SIZE(x9)
beqz x20, i2s_sd_xchg
- beq x18, x19, 2f
+ beq x18, x19, 0f
addi x20, x20, -1
and x20, x20, x18
- lw x21, I2S_ABUF_OFF_ARRAY(x9)
- add x21, x21, x20
- beqz x26, 0f
- mv x22, x18
- lbu x8, 0(x21)
+
addi x18, x18, 1
- j 1f
-0:
- srli x22, x18, 1
- lb x8, 0(x21)
- lbu x20, 1(x21)
- slli x8, x8, 8
- or x8, x8, x20
- addi x18, x18, 2
-1:
sh x18, I2S_ABUF_OFF_IDXR(x9)
- # check if buf data is for correct channel if mode is stereo
- lw x21, I2S_MODE(x27)
- bnez x21, 2f
- andi x22, x22, 1
- xor x22, x22, x25
- beqz x22, i2s_abuf_pop
+ # uint16_t array
+ slli x20, x20, 1
+ lw x21, I2S_ABUF_OFF_ARRAY(x9)
+ add x21, x21, x20
+ lh x8, 0(x21)
-2:
+0:
li x21, 0xffff
sub x18, x19, x18
and x18, x18, x21
# check for push to event queue
lw x9, I2S_SPK_WM(x27)
- bgtu x18, x9, i2s_decode
+ bgtu x18, x9, i2s_sd_xchg
lw x9, I2S_SPK_EVT(x27)
- beqz x9, i2s_decode
+ beqz x9, i2s_sd_xchg
sw x0, I2S_SPK_EVT(x27)
# push to event queue
jal x22, evtq_push
- beqz x21, i2s_decode
+ beqz x21, i2s_sd_xchg
li x18, (EOS_EVT_I2S | EOS_I2S_ETYPE_SPK)
sb x18, MSGQ_ITEM_OFF_TYPE(x21)
-i2s_decode:
- beqz x26, 3f
- # aLaw decode -> x8
- xori x8, x8, 0x55
- andi x9, x8, 0x80
- beqz x9, 0f
- li x9, (1 << 7)
- not x9, x9
- and x8, x8, x9
- li x9, -1
-0:
- andi x18, x8, 0xf0
- srli x18, x18, 4
- addi x18, x18, 4
-
- li x19, 4
- beq x18, x19, 1f
-
- andi x8, x8, 0x0f
- addi x19, x18, -4
- sll x8, x8, x19
-
- li x19, 1
- sll x19, x19, x18
- or x8, x8, x19
-
- li x19, 1
- addi x18, x18, -5
- sll x19, x19, x18
- or x8, x8, x19
- j 2f
-1:
- slli x8, x8, 1
- ori x8, x8, 1
-2:
- beqz x9, 3f
- mul x8, x8, x9
-3:
-
i2s_sd_xchg:
# read/write shift reg: x8 -> sr -> x8
+ # values of GPIO_OUTPUT_EN, GPIO_INPUT_EN, GPIO_OUTPUT_VAL registers are NOT changed (no need for clear_csr / set_csr guards outside of interrupt)
li x18, GPIO_CTRL_ADDR
li x19, (1 << I2S_PIN_SD_IN)
li x20, (1 << I2S_PIN_SD_OUT)
li x21, (1 << I2S_PIN_SR_CK)
lw x22, GPIO_OUTPUT_VAL(x18)
- # disable intpu, enable output for I2S_PIN_SD_OUT (pin is low)
- lw x9, GPIO_OUTPUT_EN(x18)
- or x9, x9, x20
+ # disable intput, enable output for I2S_PIN_SD_OUT (pin is low)
+ lw x24, GPIO_OUTPUT_EN(x18)
+ or x9, x24, x20
sw x9, GPIO_OUTPUT_EN(x18)
not x20, x20
- lw x9, GPIO_INPUT_EN(x18)
- and x9, x9, x20
+ lw x25, GPIO_INPUT_EN(x18)
+ and x9, x25, x20
sw x9, GPIO_INPUT_EN(x18)
# I2S_PIN_SR_CK bit low (was high)
@@ -268,58 +206,19 @@ i2s_sd_xchg:
addi x23, x23, -1
bnez x23, 0b
- # I2S_PIN_SD_OUT pin low (has pull-dn)
+ # I2S_PIN_SD_OUT pin low (was low)
and x22, x22, x20
# I2S_PIN_SR_CK pin high (74HC595 ck low)
xor x22, x22, x21
sw x22, GPIO_OUTPUT_VAL(x18)
- # disable output, enable input for I2S_PIN_SD_OUT
- lw x9, GPIO_OUTPUT_EN(x18)
- xor x9, x9, x20
- sw x9, GPIO_OUTPUT_EN(x18)
- lw x9, GPIO_INPUT_EN(x18)
- xor x9, x9, x20
- sw x9, GPIO_INPUT_EN(x18)
+ # restore input/output for I2S_PIN_SD_OUT
+ sw x24, GPIO_OUTPUT_EN(x18)
+ sw x25, GPIO_INPUT_EN(x18)
slli x8, x8, 16
srai x8, x8, 16
- # skip right mic channel
- bnez x25, i2s_sd_complete
-
-i2s_encode:
- beqz x26, i2s_abuf_push
- # aLaw encode -> x8
- li x18, 0x800
- li x19, 7
- bgez x8, 0f
- neg x8, x8
- lui x9, 0x80000
- or x8, x8, x9
-0:
- and x9, x8, x18
- beq x9, x18, 1f
- beqz x19, 1f
- srli x18, x18, 1
- addi x19, x19, -1
- j 0b
-1:
- mv x9, x19
- bnez x9, 2f
- addi x9, x9, 1
-2:
- sra x8, x8, x9
- li x9, 0x8000000f
- and x8, x8, x9
- slli x19, x19, 4
- or x8, x8, x19
- bgez x8, 3f
- ori x8, x8, 0x80
-3:
- xori x8, x8, 0x55
- andi x8, x8, 0xff
-
i2s_abuf_push:
# push to mic buf
la x9, _eos_i2s_mic_buf
@@ -331,27 +230,22 @@ i2s_abuf_push:
sub x18, x19, x18
and x18, x18, x21
- beq x18, x20, 2f
+ beq x18, x20, 0f
addi x20, x20, -1
and x20, x20, x19
+
+ addi x19, x19, 1
+ sh x19, I2S_ABUF_OFF_IDXW(x9)
+
+ # uint16_t array
+ slli x20, x20, 1
lw x21, I2S_ABUF_OFF_ARRAY(x9)
add x21, x21, x20
- beqz x26, 0f
- sb x8, 0(x21)
- addi x19, x19, 1
+ sh x8, 0(x21)
addi x18, x18, 1
- j 1f
-0:
- sb x8, 1(x21)
- srli x8, x8, 8
- sb x8, 0(x21)
- addi x19, x19, 2
- addi x18, x18, 2
-1:
- sh x19, I2S_ABUF_OFF_IDXW(x9)
-2:
+0:
# check for push to event queue
lw x9, I2S_MIC_WM(x27)
bltu x18, x9, i2s_sd_complete
@@ -371,7 +265,7 @@ i2s_sd_complete:
li x19, (1 << I2S_PIN_INT)
sw x19, GPIO_FALL_IP(x18)
- li x18, I2S_IRQ_SD_ID
+ li x18, I2S_IRQ_ID
li x19, PLIC_CLAIM
sw x18, 0(x19)
@@ -393,7 +287,8 @@ _eos_i2s_start_pwm:
li x18, I2S_CTRL_ADDR_CK
li x19, I2S_CTRL_ADDR_WS
li x20, I2S_CTRL_ADDR_SR_SEL
- li x21, PWM_CFG_ENALWAYS | PWM_CFG_ZEROCMP | I2S_PWM_SCALE_CK
+ li x21, PWM_CFG_ENALWAYS | PWM_CFG_ZEROCMP
+ or x21, x21, a0
li x22, PWM_CFG_ENALWAYS | PWM_CFG_ZEROCMP | PWM_CFG_CMP2GANG
li x23, PWM_CFG_ENALWAYS | PWM_CFG_ZEROCMP | PWM_CFG_CMP1GANG
sw x21, PWM_CFG(x18)
@@ -414,8 +309,8 @@ _eos_i2s_start_pwm:
trap_exit_data:
# Remain in M-mode after mret
- li x18, MSTATUS_MPP
- csrs mstatus, x18
+ # li x18, MSTATUS_MPP
+ # csrs mstatus, x18
LOAD x8, 0*REGBYTES(sp)
LOAD x9, 1*REGBYTES(sp)
@@ -483,8 +378,8 @@ handle_ext:
trap_exit_text:
# Remain in M-mode after mret
- li t0, MSTATUS_MPP
- csrs mstatus, t0
+ # li t0, MSTATUS_MPP
+ # csrs mstatus, t0
LOAD x1, 0*REGBYTES(sp)
LOAD x2, 1*REGBYTES(sp)
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-31 22:06:10 +0000