diff options
Diffstat (limited to 'recipes-bsp/u-boot/rvphone/cl-imx8/board')
9 files changed, 4017 insertions, 0 deletions
diff --git a/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/Kconfig b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/Kconfig new file mode 100644 index 0000000..4daaf23 --- /dev/null +++ b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/Kconfig @@ -0,0 +1,30 @@ +if TARGET_RVPHONE_CL_IMX8 + +config SYS_BOARD + default "cl-imx8" + +config SYS_VENDOR + default "rvphone" + +config SYS_CONFIG_NAME + default "cl-imx8" + +choice + prompt "RAM Volume select" + default RAM_2G + help + This option configures 2G RAM only + +config RAM_1G + bool "RAM_1G" + help + This option configures 1G RAM only + +config RAM_2G + bool "RAM_2G" + help + This option configures 2G RAM only + +endchoice + +endif diff --git a/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/Makefile b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/Makefile new file mode 100644 index 0000000..30eb144 --- /dev/null +++ b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2017 CompuLab LTD. +# +# SPDX-License-Identifier: GPL-2.0+ +# +ccflags-y += -I../../freescale + +obj-y += common.o +obj-y += ../../freescale/common/mmc.o +obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += ../../freescale/common/pfuze.o +obj-$(CONFIG_POWER_PFUZE100) += ../../freescale/common/pfuze.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o ddr/lpddr4_timing_1g.o ddr/lpddr4_timing_2g.o +else +obj-y += cl-imx8.o +endif diff --git a/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/cl-imx8.c b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/cl-imx8.c new file mode 100644 index 0000000..b728bc7 --- /dev/null +++ b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/cl-imx8.c @@ -0,0 +1,145 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <asm/io.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm-generic/gpio.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/arch/clock.h> +#include <asm/mach-imx/video.h> +#include <asm/arch/video_common.h> +#include <spl.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include "../../freescale/common/pfuze.h" + +#include "common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init(void) +{ + /* TODO */ + return 0; +} +#endif + +static phys_size_t imx8_ddr_size(void) +{ + unsigned long mem = 0x3d400000; + unsigned long value = readl(mem+0x200); + phys_size_t dram_size = 0x40000000;; + + switch (value) { + case 0x1f: + dram_size = 0x40000000; + break; + case 0x16: + dram_size = 0x80000000; + break; + case 0x17: + /* dram_size = 0x100000000;*/ + /* reports 3G only, if reports above then gets crashed */ + dram_size = 0xc0000000; + break; + default: + break; + }; + return dram_size; +} + +int dram_init(void) +{ + gd->ram_size = imx8_ddr_size(); + return 0; +} + +void _dram_init_banksize(void) + +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = imx8_ddr_size(); +} + +phys_size_t get_effective_memsize(void) +{ + phys_size_t dram_size = imx8_ddr_size(); + if (dram_size > 0x80000000) + return 0x80000000; + + return dram_size; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +static iomux_v3_cfg_t const usbmux_pads[] = { + IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_usbmux(void) +{ + imx_iomux_v3_setup_multiple_pads(usbmux_pads, ARRAY_SIZE(usbmux_pads)); + + gpio_request(IMX_GPIO_NR(1, 4), "usb_mux"); + gpio_direction_output(IMX_GPIO_NR(1, 4), 0); +} + +static void setup_usbmux(void) +{ + setup_iomux_usbmux(); +} + +int board_init(void) +{ + setup_usbmux(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + const char *s = env_get("atp"); + if (s != NULL) { + printf("ATP Mode: Save environmet on eMMC\n"); + return CONFIG_SYS_MMC_ENV_DEV; + } + return devno; +} + +int board_late_init(void) +{ + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/common.c b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/common.c new file mode 100644 index 0000000..d3a8f3f --- /dev/null +++ b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/common.c @@ -0,0 +1,33 @@ +#include "common.h" +#include <asm/arch/clock.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm-generic/gpio.h> +#include <asm/mach-imx/gpio.h> + +void set_wdog_reset(struct wdog_regs *wdog); + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} diff --git a/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/common.h b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/common.h new file mode 100644 index 0000000..d70f78c --- /dev/null +++ b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/common.h @@ -0,0 +1,11 @@ +#ifndef __CL_IMX8_COMMON_H__ +#define __CL_IMX8_COMMON_H__ + +#include <asm/mach-imx/iomux-v3.h> + +int board_early_init_f(void); + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +#endif /* __CL_IMX8_COMMON_H__ */ diff --git a/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/ddr/ddr.h b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/ddr/ddr.h new file mode 100644 index 0000000..f52c93e --- /dev/null +++ b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/ddr/ddr.h @@ -0,0 +1,14 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +extern struct dram_timing_info dram_timing_2g; +extern struct dram_timing_info dram_timing_1g; +void ddr_init(struct dram_timing_info *dram_timing); + +#endif diff --git a/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/ddr/lpddr4_timing_1g.c b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/ddr/lpddr4_timing_1g.c new file mode 100644 index 0000000..4b2cd0f --- /dev/null +++ b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/ddr/lpddr4_timing_1g.c @@ -0,0 +1,1733 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include <linux/kernel.h> +#include <asm/arch/imx8m_ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304,0x1}, + {0x3d400030,0x1}, + {0x3d400000,0xa1080020}, + {0x3d400028,0x0}, + {0x3d400020,0x203}, + {0x3d400024,0x3e800}, + {0x3d400064,0x610090}, + {0x3d4000d0,0xc003061c}, + {0x3d4000d4,0x9e0000}, + {0x3d4000dc,0xd4002d}, + {0x3d4000e0,0x310008}, + {0x3d4000e8,0x66004a}, + {0x3d4000ec,0x16004a}, + {0x3d400100,0x1a201b22}, + {0x3d400104,0x60633}, + {0x3d40010c,0xc0c000}, + {0x3d400110,0xf04080f}, + {0x3d400114,0x2040c0c}, + {0x3d400118,0x1010007}, + {0x3d40011c,0x401}, + {0x3d400130,0x20600}, + {0x3d400134,0xc100002}, + {0x3d400138,0x96}, + {0x3d400144,0xa00050}, + {0x3d400180,0xc3200018}, + {0x3d400184,0x28061a8}, + {0x3d400188,0x0}, + {0x3d400190,0x497820a}, + {0x3d400194,0x80303}, + {0x3d4001a0,0xe0400018}, + {0x3d4001a4,0xdf00e4}, + {0x3d4001a8,0x80000000}, + {0x3d4001b0,0x11}, + {0x3d4001b4,0x170a}, + {0x3d4001c0,0x1}, + {0x3d4001c4,0x1}, + {0x3d4000f4,0x639}, + {0x3d400108,0x70e1617}, + {0x3d400200,0x1f}, + {0x3d40020c,0x0}, + {0x3d400210,0x1f1f}, + {0x3d400204,0x80808}, + {0x3d400214,0x7070707}, + {0x3d400218,0xf070707}, + {0x3d402020,0x1}, + {0x3d402024,0xd0c0}, + {0x3d402050,0x20d040}, + {0x3d402064,0x14001f}, + {0x3d4020dc,0x940009}, + {0x3d4020e0,0x310000}, + {0x3d4020e8,0x66004a}, + {0x3d4020ec,0x16004a}, + {0x3d402100,0xb070508}, + {0x3d402104,0x3040b}, + {0x3d402108,0x305090c}, + {0x3d40210c,0x505000}, + {0x3d402110,0x4040204}, + {0x3d402114,0x2030303}, + {0x3d402118,0x1010004}, + {0x3d40211c,0x301}, + {0x3d402130,0x20300}, + {0x3d402134,0xa100002}, + {0x3d402138,0x20}, + {0x3d402144,0x220011}, + {0x3d402180,0xc0a70006}, + {0x3d402190,0x3858202}, + {0x3d402194,0x80303}, + {0x3d4021b4,0x502}, + {0x3d400244,0x0}, + {0x3d400250,0x29001505}, + {0x3d400254,0x2c}, + {0x3d40025c,0x5900575b}, + {0x3d400264,0x90000096}, + {0x3d40026c,0x1000012c}, + {0x3d400300,0x16}, + {0x3d400304,0x0}, + {0x3d40030c,0x0}, + {0x3d400320,0x1}, + {0x3d40036c,0x11}, + {0x3d400400,0x111}, + {0x3d400404,0x10f3}, + {0x3d400408,0x72ff}, + {0x3d400490,0x1}, + {0x3d400494,0xe00}, + {0x3d400498,0x62ffff}, + {0x3d40049c,0xe00}, + {0x3d4004a0,0xffff}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0,0x0}, + {0x100a1,0x1}, + {0x100a2,0x2}, + {0x100a3,0x3}, + {0x100a4,0x4}, + {0x100a5,0x5}, + {0x100a6,0x6}, + {0x100a7,0x7}, + {0x110a0,0x2}, + {0x110a1,0x6}, + {0x110a2,0x4}, + {0x110a3,0x7}, + {0x110a4,0x5}, + {0x110a5,0x3}, + {0x110a6,0x0}, + {0x110a7,0x1}, + {0x120a0,0x0}, + {0x120a1,0x1}, + {0x120a2,0x2}, + {0x120a3,0x3}, + {0x120a4,0x4}, + {0x120a5,0x5}, + {0x120a6,0x6}, + {0x120a7,0x7}, + {0x130a0,0x1}, + {0x130a1,0x3}, + {0x130a2,0x4}, + {0x130a3,0x7}, + {0x130a4,0x6}, + {0x130a5,0x5}, + {0x130a6,0x0}, + {0x130a7,0x2}, + {0x20110,0x2}, + {0x20111,0x3}, + {0x20112,0x4}, + {0x20113,0x5}, + {0x20114,0x0}, + {0x20115,0x1}, + {0x1005f,0x1ff}, + {0x1015f,0x1ff}, + {0x1105f,0x1ff}, + {0x1115f,0x1ff}, + {0x1205f,0x1ff}, + {0x1215f,0x1ff}, + {0x1305f,0x1ff}, + {0x1315f,0x1ff}, + {0x11005f,0x1ff}, + {0x11015f,0x1ff}, + {0x11105f,0x1ff}, + {0x11115f,0x1ff}, + {0x11205f,0x1ff}, + {0x11215f,0x1ff}, + {0x11305f,0x1ff}, + {0x11315f,0x1ff}, + {0x55,0x1ff}, + {0x1055,0x1ff}, + {0x2055,0x1ff}, + {0x3055,0x1ff}, + {0x4055,0x1ff}, + {0x5055,0x1ff}, + {0x6055,0x1ff}, + {0x7055,0x1ff}, + {0x8055,0x1ff}, + {0x9055,0x1ff}, + {0x200c5,0x19}, + {0x1200c5,0x7}, + {0x2002e,0x2}, + {0x12002e,0x1}, + {0x90204,0x0}, + {0x190204,0x0}, + {0x20024,0x1ab}, + {0x2003a,0x0}, + {0x120024,0x1ab}, + {0x2003a,0x0}, + {0x20056,0x3}, + {0x120056,0xa}, + {0x1004d,0xe00}, + {0x1014d,0xe00}, + {0x1104d,0xe00}, + {0x1114d,0xe00}, + {0x1204d,0xe00}, + {0x1214d,0xe00}, + {0x1304d,0xe00}, + {0x1314d,0xe00}, + {0x11004d,0xe00}, + {0x11014d,0xe00}, + {0x11104d,0xe00}, + {0x11114d,0xe00}, + {0x11204d,0xe00}, + {0x11214d,0xe00}, + {0x11304d,0xe00}, + {0x11314d,0xe00}, + {0x10049,0xeba}, + {0x10149,0xeba}, + {0x11049,0xeba}, + {0x11149,0xeba}, + {0x12049,0xeba}, + {0x12149,0xeba}, + {0x13049,0xeba}, + {0x13149,0xeba}, + {0x110049,0xeba}, + {0x110149,0xeba}, + {0x111049,0xeba}, + {0x111149,0xeba}, + {0x112049,0xeba}, + {0x112149,0xeba}, + {0x113049,0xeba}, + {0x113149,0xeba}, + {0x43,0x63}, + {0x1043,0x63}, + {0x2043,0x63}, + {0x3043,0x63}, + {0x4043,0x63}, + {0x5043,0x63}, + {0x6043,0x63}, + {0x7043,0x63}, + {0x8043,0x63}, + {0x9043,0x63}, + {0x20018,0x3}, + {0x20075,0x4}, + {0x20050,0x0}, + {0x20008,0x320}, + {0x120008,0xa7}, + {0x20088,0x9}, + {0x200b2,0xdc}, + {0x10043,0x5a1}, + {0x10143,0x5a1}, + {0x11043,0x5a1}, + {0x11143,0x5a1}, + {0x12043,0x5a1}, + {0x12143,0x5a1}, + {0x13043,0x5a1}, + {0x13143,0x5a1}, + {0x1200b2,0xdc}, + {0x110043,0x5a1}, + {0x110143,0x5a1}, + {0x111043,0x5a1}, + {0x111143,0x5a1}, + {0x112043,0x5a1}, + {0x112143,0x5a1}, + {0x113043,0x5a1}, + {0x113143,0x5a1}, + {0x200fa,0x1}, + {0x1200fa,0x1}, + {0x20019,0x1}, + {0x120019,0x1}, + {0x200f0,0x0}, + {0x200f1,0x0}, + {0x200f2,0x4444}, + {0x200f3,0x8888}, + {0x200f4,0x5555}, + {0x200f5,0x0}, + {0x200f6,0x0}, + {0x200f7,0xf000}, + {0x20025,0x0}, + {0x2002d,0x0}, + {0x12002d,0x0}, + {0x200c7,0x80}, + {0x1200c7,0x80}, + {0x200ca,0x106}, + {0x1200ca,0x106}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + 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0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xc80}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x131f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4a66}, + {0x5401c,0x4a08}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4a66}, + {0x54022,0x4a08}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x84a}, + {0x54036,0x4a}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x84a}, + {0x5403c,0x4a}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x1}, + {0x54003,0x29c}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x994}, + {0x5401a,0x31}, + {0x5401b,0x4a66}, + {0x5401c,0x4a08}, + {0x5401e,0x16}, + {0x5401f,0x994}, + {0x54020,0x31}, + {0x54021,0x4a66}, + {0x54022,0x4a08}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0x9400}, + {0x54033,0x3109}, + {0x54034,0x6600}, + {0x54035,0x84a}, + {0x54036,0x4a}, + {0x54037,0x1600}, + {0x54038,0x9400}, + {0x54039,0x3109}, + {0x5403a,0x6600}, + {0x5403b,0x84a}, + {0x5403c,0x4a}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xc80}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x61}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400f,0x100}, + {0x54010,0x1f7f}, + {0x54012,0x110}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4a66}, + {0x5401c,0x4a08}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4a66}, + {0x54022,0x4a08}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x84a}, + {0x54036,0x4a}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x84a}, + {0x5403c,0x4a}, + {0x5403d,0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000,0x10}, + {0x90001,0x400}, + {0x90002,0x10e}, + {0x90003,0x0}, + {0x90004,0x0}, + {0x90005,0x8}, + {0x90029,0xb}, + {0x9002a,0x480}, + {0x9002b,0x109}, + {0x9002c,0x8}, + {0x9002d,0x448}, + {0x9002e,0x139}, + {0x9002f,0x8}, + {0x90030,0x478}, + {0x90031,0x109}, + {0x90032,0x0}, + {0x90033,0xe8}, + {0x90034,0x109}, + {0x90035,0x2}, + {0x90036,0x10}, + {0x90037,0x139}, + {0x90038,0xf}, + {0x90039,0x7c0}, + {0x9003a,0x139}, + {0x9003b,0x44}, + {0x9003c,0x630}, + {0x9003d,0x159}, + {0x9003e,0x14f}, + {0x9003f,0x630}, + {0x90040,0x159}, + {0x90041,0x47}, + {0x90042,0x630}, + {0x90043,0x149}, + {0x90044,0x4f}, + {0x90045,0x630}, + {0x90046,0x179}, + {0x90047,0x8}, + {0x90048,0xe0}, + {0x90049,0x109}, + {0x9004a,0x0}, + {0x9004b,0x7c8}, + {0x9004c,0x109}, + {0x9004d,0x0}, + {0x9004e,0x1}, + {0x9004f,0x8}, + {0x90050,0x0}, + {0x90051,0x45a}, + {0x90052,0x9}, + {0x90053,0x0}, + {0x90054,0x448}, + {0x90055,0x109}, + {0x90056,0x40}, + {0x90057,0x630}, + {0x90058,0x179}, + {0x90059,0x1}, + {0x9005a,0x618}, + {0x9005b,0x109}, + {0x9005c,0x40c0}, + {0x9005d,0x630}, + {0x9005e,0x149}, + {0x9005f,0x8}, + {0x90060,0x4}, + {0x90061,0x48}, + {0x90062,0x4040}, + {0x90063,0x630}, + {0x90064,0x149}, + {0x90065,0x0}, + {0x90066,0x4}, + {0x90067,0x48}, + {0x90068,0x40}, + {0x90069,0x630}, + {0x9006a,0x149}, + {0x9006b,0x10}, + {0x9006c,0x4}, + {0x9006d,0x18}, + {0x9006e,0x0}, + {0x9006f,0x4}, + {0x90070,0x78}, + {0x90071,0x549}, + {0x90072,0x630}, + {0x90073,0x159}, + {0x90074,0xd49}, + {0x90075,0x630}, + {0x90076,0x159}, + {0x90077,0x94a}, + {0x90078,0x630}, + {0x90079,0x159}, + {0x9007a,0x441}, + {0x9007b,0x630}, + {0x9007c,0x149}, + {0x9007d,0x42}, + {0x9007e,0x630}, + {0x9007f,0x149}, + {0x90080,0x1}, + {0x90081,0x630}, + {0x90082,0x149}, + {0x90083,0x0}, + {0x90084,0xe0}, + {0x90085,0x109}, + {0x90086,0xa}, + {0x90087,0x10}, + {0x90088,0x109}, + {0x90089,0x9}, + {0x9008a,0x3c0}, + {0x9008b,0x149}, + {0x9008c,0x9}, + {0x9008d,0x3c0}, + {0x9008e,0x159}, + {0x9008f,0x18}, + {0x90090,0x10}, + {0x90091,0x109}, + {0x90092,0x0}, + {0x90093,0x3c0}, + {0x90094,0x109}, + {0x90095,0x18}, + {0x90096,0x4}, + {0x90097,0x48}, + {0x90098,0x18}, + {0x90099,0x4}, + {0x9009a,0x58}, + {0x9009b,0xa}, + {0x9009c,0x10}, + {0x9009d,0x109}, + {0x9009e,0x2}, + {0x9009f,0x10}, + {0x900a0,0x109}, + {0x900a1,0x5}, + {0x900a2,0x7c0}, + {0x900a3,0x109}, + {0x900a4,0x10}, + {0x900a5,0x10}, + {0x900a6,0x109}, + {0x40000,0x811}, + {0x40020,0x880}, + {0x40040,0x0}, + {0x40060,0x0}, + {0x40001,0x4008}, + {0x40021,0x83}, + {0x40041,0x4f}, + {0x40061,0x0}, + {0x40002,0x4040}, + {0x40022,0x83}, + {0x40042,0x51}, + {0x40062,0x0}, + {0x40003,0x811}, + {0x40023,0x880}, + {0x40043,0x0}, + {0x40063,0x0}, + {0x40004,0x720}, + {0x40024,0xf}, + {0x40044,0x1740}, + {0x40064,0x0}, + {0x40005,0x16}, + {0x40025,0x83}, + {0x40045,0x4b}, + {0x40065,0x0}, + {0x40006,0x716}, + {0x40026,0xf}, + {0x40046,0x2001}, + {0x40066,0x0}, + {0x40007,0x716}, + {0x40027,0xf}, + {0x40047,0x2800}, + {0x40067,0x0}, + {0x40008,0x716}, + {0x40028,0xf}, + {0x40048,0xf00}, + {0x40068,0x0}, + {0x40009,0x720}, + {0x40029,0xf}, + {0x40049,0x1400}, + {0x40069,0x0}, + {0x4000a,0xe08}, + {0x4002a,0xc15}, + {0x4004a,0x0}, + {0x4006a,0x0}, + {0x4000b,0x623}, + {0x4002b,0x15}, + {0x4004b,0x0}, + {0x4006b,0x0}, + {0x4000c,0x4028}, + {0x4002c,0x80}, + {0x4004c,0x0}, + {0x4006c,0x0}, + {0x4000d,0xe08}, + {0x4002d,0xc1a}, + {0x4004d,0x0}, + {0x4006d,0x0}, + {0x4000e,0x623}, + {0x4002e,0x1a}, + {0x4004e,0x0}, + {0x4006e,0x0}, + {0x4000f,0x4040}, + {0x4002f,0x80}, + {0x4004f,0x0}, + {0x4006f,0x0}, + {0x40010,0x2604}, + {0x40030,0x15}, + {0x40050,0x0}, + {0x40070,0x0}, + {0x40011,0x708}, + {0x40031,0x5}, + {0x40051,0x0}, + {0x40071,0x2002}, + {0x40012,0x8}, + {0x40032,0x80}, + {0x40052,0x0}, + {0x40072,0x0}, + {0x40013,0x2604}, + {0x40033,0x1a}, + {0x40053,0x0}, + {0x40073,0x0}, + {0x40014,0x708}, + {0x40034,0xa}, + {0x40054,0x0}, + {0x40074,0x2002}, + {0x40015,0x4040}, + {0x40035,0x80}, + {0x40055,0x0}, + {0x40075,0x0}, + {0x40016,0x60a}, + {0x40036,0x15}, + {0x40056,0x1200}, + {0x40076,0x0}, + {0x40017,0x61a}, + {0x40037,0x15}, + {0x40057,0x1300}, + {0x40077,0x0}, + {0x40018,0x60a}, + {0x40038,0x1a}, + {0x40058,0x1200}, + {0x40078,0x0}, + {0x40019,0x642}, + {0x40039,0x1a}, + {0x40059,0x1300}, + {0x40079,0x0}, + {0x4001a,0x4808}, + {0x4003a,0x880}, + {0x4005a,0x0}, + {0x4007a,0x0}, + {0x900a7,0x0}, + {0x900a8,0x790}, + {0x900a9,0x11a}, + {0x900aa,0x8}, + {0x900ab,0x7aa}, + {0x900ac,0x2a}, + {0x900ad,0x10}, + {0x900ae,0x7b2}, + {0x900af,0x2a}, + {0x900b0,0x0}, + {0x900b1,0x7c8}, + {0x900b2,0x109}, + {0x900b3,0x10}, + {0x900b4,0x2a8}, + {0x900b5,0x129}, + {0x900b6,0x8}, + {0x900b7,0x370}, + {0x900b8,0x129}, + {0x900b9,0xa}, + {0x900ba,0x3c8}, + {0x900bb,0x1a9}, + {0x900bc,0xc}, + {0x900bd,0x408}, + {0x900be,0x199}, + {0x900bf,0x14}, + {0x900c0,0x790}, + {0x900c1,0x11a}, + {0x900c2,0x8}, + {0x900c3,0x4}, + {0x900c4,0x18}, + {0x900c5,0xe}, + {0x900c6,0x408}, + {0x900c7,0x199}, + {0x900c8,0x8}, + {0x900c9,0x8568}, + {0x900ca,0x108}, + {0x900cb,0x18}, + {0x900cc,0x790}, + {0x900cd,0x16a}, + {0x900ce,0x8}, + {0x900cf,0x1d8}, + {0x900d0,0x169}, + {0x900d1,0x10}, + {0x900d2,0x8558}, + {0x900d3,0x168}, + {0x900d4,0x70}, + {0x900d5,0x788}, + {0x900d6,0x16a}, + {0x900d7,0x1ff8}, + {0x900d8,0x85a8}, + {0x900d9,0x1e8}, + {0x900da,0x50}, + {0x900db,0x798}, + {0x900dc,0x16a}, + {0x900dd,0x60}, + {0x900de,0x7a0}, + {0x900df,0x16a}, + {0x900e0,0x8}, + {0x900e1,0x8310}, + {0x900e2,0x168}, + {0x900e3,0x8}, + {0x900e4,0xa310}, + {0x900e5,0x168}, + {0x900e6,0xa}, + {0x900e7,0x408}, + {0x900e8,0x169}, + {0x900e9,0x6e}, + {0x900ea,0x0}, + {0x900eb,0x68}, + {0x900ec,0x0}, + {0x900ed,0x408}, + {0x900ee,0x169}, + {0x900ef,0x0}, + {0x900f0,0x8310}, + {0x900f1,0x168}, + {0x900f2,0x0}, + {0x900f3,0xa310}, + {0x900f4,0x168}, + {0x900f5,0x1ff8}, + {0x900f6,0x85a8}, + {0x900f7,0x1e8}, + {0x900f8,0x68}, + {0x900f9,0x798}, + {0x900fa,0x16a}, + {0x900fb,0x78}, + {0x900fc,0x7a0}, + {0x900fd,0x16a}, + {0x900fe,0x68}, + {0x900ff,0x790}, + {0x90100,0x16a}, + {0x90101,0x8}, + {0x90102,0x8b10}, + {0x90103,0x168}, + {0x90104,0x8}, + {0x90105,0xab10}, + {0x90106,0x168}, + {0x90107,0xa}, + {0x90108,0x408}, + {0x90109,0x169}, + {0x9010a,0x58}, + {0x9010b,0x0}, + {0x9010c,0x68}, + {0x9010d,0x0}, + {0x9010e,0x408}, + {0x9010f,0x169}, + {0x90110,0x0}, + {0x90111,0x8b10}, + {0x90112,0x168}, + {0x90113,0x0}, + {0x90114,0xab10}, + {0x90115,0x168}, + {0x90116,0x0}, + {0x90117,0x1d8}, + {0x90118,0x169}, + {0x90119,0x80}, + {0x9011a,0x790}, + {0x9011b,0x16a}, + {0x9011c,0x18}, + {0x9011d,0x7aa}, + {0x9011e,0x6a}, + {0x9011f,0xa}, + {0x90120,0x0}, + {0x90121,0x1e9}, + {0x90122,0x8}, + {0x90123,0x8080}, + {0x90124,0x108}, + {0x90125,0xf}, + {0x90126,0x408}, + {0x90127,0x169}, + {0x90128,0xc}, + {0x90129,0x0}, + {0x9012a,0x68}, + {0x9012b,0x9}, + {0x9012c,0x0}, + {0x9012d,0x1a9}, + {0x9012e,0x0}, + {0x9012f,0x408}, + {0x90130,0x169}, + {0x90131,0x0}, + {0x90132,0x8080}, + {0x90133,0x108}, + {0x90134,0x8}, + {0x90135,0x7aa}, + {0x90136,0x6a}, + {0x90137,0x0}, + {0x90138,0x8568}, + {0x90139,0x108}, + {0x9013a,0xb7}, + {0x9013b,0x790}, + {0x9013c,0x16a}, + {0x9013d,0x1f}, + {0x9013e,0x0}, + {0x9013f,0x68}, + {0x90140,0x8}, + {0x90141,0x8558}, + {0x90142,0x168}, + {0x90143,0xf}, + {0x90144,0x408}, + {0x90145,0x169}, + {0x90146,0xc}, + {0x90147,0x0}, + {0x90148,0x68}, + {0x90149,0x0}, + {0x9014a,0x408}, + {0x9014b,0x169}, + {0x9014c,0x0}, + {0x9014d,0x8558}, + {0x9014e,0x168}, + {0x9014f,0x8}, + {0x90150,0x3c8}, + {0x90151,0x1a9}, + {0x90152,0x3}, + {0x90153,0x370}, + {0x90154,0x129}, + {0x90155,0x20}, + {0x90156,0x2aa}, + {0x90157,0x9}, + {0x90158,0x0}, + {0x90159,0x400}, + {0x9015a,0x10e}, + {0x9015b,0x8}, + {0x9015c,0xe8}, + {0x9015d,0x109}, + {0x9015e,0x0}, + {0x9015f,0x8140}, + {0x90160,0x10c}, + {0x90161,0x10}, + {0x90162,0x8138}, + {0x90163,0x10c}, + {0x90164,0x8}, + {0x90165,0x7c8}, + {0x90166,0x101}, + {0x90167,0x8}, + {0x90168,0x0}, + {0x90169,0x8}, + {0x9016a,0x8}, + {0x9016b,0x448}, + {0x9016c,0x109}, + {0x9016d,0xf}, + {0x9016e,0x7c0}, + {0x9016f,0x109}, + {0x90170,0x0}, + {0x90171,0xe8}, + {0x90172,0x109}, + {0x90173,0x47}, + {0x90174,0x630}, + {0x90175,0x109}, + {0x90176,0x8}, + {0x90177,0x618}, + {0x90178,0x109}, + {0x90179,0x8}, + {0x9017a,0xe0}, + {0x9017b,0x109}, + {0x9017c,0x0}, + {0x9017d,0x7c8}, + {0x9017e,0x109}, + {0x9017f,0x8}, + {0x90180,0x8140}, + {0x90181,0x10c}, + {0x90182,0x0}, + {0x90183,0x1}, + {0x90184,0x8}, + {0x90185,0x8}, + {0x90186,0x4}, + {0x90187,0x8}, + {0x90188,0x8}, + {0x90189,0x7c8}, + {0x9018a,0x101}, + {0x90006,0x0}, + {0x90007,0x0}, + {0x90008,0x8}, + {0x90009,0x0}, + {0x9000a,0x0}, + {0x9000b,0x0}, + {0xd00e7,0x400}, + {0x90017,0x0}, + {0x9001f,0x2a}, + {0x90026,0x6a}, + {0x400d0,0x0}, + {0x400d1,0x101}, + {0x400d2,0x105}, + {0x400d3,0x107}, + {0x400d4,0x10f}, + {0x400d5,0x202}, + {0x400d6,0x20a}, + {0x400d7,0x20b}, + {0x2003a,0x2}, + {0x2000b,0x64}, + {0x2000c,0xc8}, + {0x2000d,0x7d0}, + {0x2000e,0x2c}, + {0x12000b,0x14}, + {0x12000c,0x29}, + {0x12000d,0x1a1}, + {0x12000e,0x10}, + {0x9000c,0x0}, + {0x9000d,0x173}, + {0x9000e,0x60}, + {0x9000f,0x6110}, + {0x90010,0x2152}, + {0x90011,0xdfbd}, + {0x90012,0x60}, + {0x90013,0x6152}, + {0x20010,0x5a}, + {0x20011,0x3}, + {0x120010,0x5a}, + {0x120011,0x3}, + {0x40080,0xe0}, + {0x40081,0x12}, + {0x40082,0xe0}, + {0x40083,0x12}, + {0x40084,0xe0}, + {0x40085,0x12}, + {0x140080,0xe0}, + {0x140081,0x12}, + {0x140082,0xe0}, + {0x140083,0x12}, + {0x140084,0xe0}, + {0x140085,0x12}, + {0x400fd,0xf}, + {0x10011,0x1}, + {0x10012,0x1}, + {0x10013,0x180}, + {0x10018,0x1}, + {0x10002,0x6209}, + {0x100b2,0x1}, + {0x101b4,0x1}, + {0x102b4,0x1}, + {0x103b4,0x1}, + {0x104b4,0x1}, + {0x105b4,0x1}, + {0x106b4,0x1}, + {0x107b4,0x1}, + {0x108b4,0x1}, + {0x11011,0x1}, + {0x11012,0x1}, + {0x11013,0x180}, + {0x11018,0x1}, + {0x11002,0x6209}, + {0x110b2,0x1}, + {0x111b4,0x1}, + {0x112b4,0x1}, + {0x113b4,0x1}, + {0x114b4,0x1}, + {0x115b4,0x1}, + {0x116b4,0x1}, + {0x117b4,0x1}, + {0x118b4,0x1}, + {0x12011,0x1}, + {0x12012,0x1}, + {0x12013,0x180}, + {0x12018,0x1}, + {0x12002,0x6209}, + {0x120b2,0x1}, + {0x121b4,0x1}, + {0x122b4,0x1}, + {0x123b4,0x1}, + {0x124b4,0x1}, + {0x125b4,0x1}, + {0x126b4,0x1}, + {0x127b4,0x1}, + {0x128b4,0x1}, + {0x13011,0x1}, + {0x13012,0x1}, + {0x13013,0x180}, + {0x13018,0x1}, + {0x13002,0x6209}, + {0x130b2,0x1}, + {0x131b4,0x1}, + {0x132b4,0x1}, + {0x133b4,0x1}, + {0x134b4,0x1}, + {0x135b4,0x1}, + {0x136b4,0x1}, + {0x137b4,0x1}, + {0x138b4,0x1}, + {0x2003a,0x2}, + {0xc0080,0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1g = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 667, }, +}; diff --git a/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/ddr/lpddr4_timing_2g.c b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/ddr/lpddr4_timing_2g.c new file mode 100644 index 0000000..9173c57 --- /dev/null +++ b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/ddr/lpddr4_timing_2g.c @@ -0,0 +1,1733 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include <linux/kernel.h> +#include <asm/arch/imx8m_ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304,0x1}, + {0x3d400030,0x1}, + {0x3d400000,0xa3080020}, + {0x3d400028,0x0}, + {0x3d400020,0x203}, + {0x3d400024,0x3e800}, + {0x3d400064,0x6100e0}, + {0x3d4000d0,0xc003061c}, + {0x3d4000d4,0x9e0000}, + {0x3d4000dc,0xd4002d}, + {0x3d4000e0,0x310008}, + {0x3d4000e8,0x66004a}, + {0x3d4000ec,0x16004a}, + {0x3d400100,0x1a201b22}, + {0x3d400104,0x60633}, + {0x3d40010c,0xc0c000}, + {0x3d400110,0xf04080f}, + {0x3d400114,0x2040c0c}, + {0x3d400118,0x1010007}, + {0x3d40011c,0x401}, + {0x3d400130,0x20600}, + {0x3d400134,0xc100002}, + {0x3d400138,0xe6}, + {0x3d400144,0xa00050}, + {0x3d400180,0xc3200018}, + {0x3d400184,0x28061a8}, + {0x3d400188,0x0}, + {0x3d400190,0x497820a}, + {0x3d400194,0x80303}, + {0x3d4001a0,0xe0400018}, + {0x3d4001a4,0xdf00e4}, + {0x3d4001a8,0x80000000}, + {0x3d4001b0,0x11}, + {0x3d4001b4,0x170a}, + {0x3d4001c0,0x1}, + {0x3d4001c4,0x1}, + {0x3d4000f4,0x639}, + {0x3d400108,0x70e1617}, + {0x3d400200,0x16}, + {0x3d40020c,0x0}, + {0x3d400210,0x1f1f}, + {0x3d400204,0x80808}, + {0x3d400214,0x7070707}, + {0x3d400218,0xf070707}, + {0x3d402020,0x1}, + {0x3d402024,0xd0c0}, + {0x3d402050,0x20d040}, + {0x3d402064,0x14002f}, + {0x3d4020dc,0x940009}, + {0x3d4020e0,0x310000}, + {0x3d4020e8,0x66004a}, + {0x3d4020ec,0x16004a}, + {0x3d402100,0xb070508}, + {0x3d402104,0x3040b}, + {0x3d402108,0x305090c}, + {0x3d40210c,0x505000}, + {0x3d402110,0x4040204}, + {0x3d402114,0x2030303}, + {0x3d402118,0x1010004}, + {0x3d40211c,0x301}, + {0x3d402130,0x20300}, + {0x3d402134,0xa100002}, + {0x3d402138,0x31}, + {0x3d402144,0x220011}, + {0x3d402180,0xc0a70006}, + {0x3d402190,0x3858202}, + {0x3d402194,0x80303}, + {0x3d4021b4,0x502}, + {0x3d400244,0x0}, + {0x3d400250,0x29001505}, + {0x3d400254,0x2c}, + {0x3d40025c,0x5900575b}, + {0x3d400264,0x90000096}, + {0x3d40026c,0x1000012c}, + {0x3d400300,0x16}, + {0x3d400304,0x0}, + {0x3d40030c,0x0}, + {0x3d400320,0x1}, + {0x3d40036c,0x11}, + {0x3d400400,0x111}, + {0x3d400404,0x10f3}, + {0x3d400408,0x72ff}, + {0x3d400490,0x1}, + {0x3d400494,0xe00}, + {0x3d400498,0x62ffff}, + {0x3d40049c,0xe00}, + {0x3d4004a0,0xffff}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0,0x0}, + {0x100a1,0x1}, + {0x100a2,0x2}, + {0x100a3,0x3}, + {0x100a4,0x4}, + {0x100a5,0x5}, + {0x100a6,0x6}, + {0x100a7,0x7}, + {0x110a0,0x2}, + {0x110a1,0x6}, + {0x110a2,0x4}, + {0x110a3,0x7}, + {0x110a4,0x5}, + {0x110a5,0x3}, + {0x110a6,0x0}, + {0x110a7,0x1}, + {0x120a0,0x0}, + {0x120a1,0x1}, + {0x120a2,0x2}, + {0x120a3,0x3}, + {0x120a4,0x4}, + {0x120a5,0x5}, + {0x120a6,0x6}, + {0x120a7,0x7}, + {0x130a0,0x1}, + {0x130a1,0x3}, + {0x130a2,0x4}, + {0x130a3,0x7}, + {0x130a4,0x6}, + {0x130a5,0x5}, + {0x130a6,0x0}, + {0x130a7,0x2}, + {0x20110,0x2}, + {0x20111,0x3}, + {0x20112,0x4}, + {0x20113,0x5}, + {0x20114,0x0}, + {0x20115,0x1}, + {0x1005f,0x1ff}, + {0x1015f,0x1ff}, + {0x1105f,0x1ff}, + {0x1115f,0x1ff}, + {0x1205f,0x1ff}, + {0x1215f,0x1ff}, + {0x1305f,0x1ff}, + {0x1315f,0x1ff}, + {0x11005f,0x1ff}, + {0x11015f,0x1ff}, + {0x11105f,0x1ff}, + {0x11115f,0x1ff}, + {0x11205f,0x1ff}, + {0x11215f,0x1ff}, + {0x11305f,0x1ff}, + {0x11315f,0x1ff}, + {0x55,0x1ff}, + {0x1055,0x1ff}, + {0x2055,0x1ff}, + {0x3055,0x1ff}, + {0x4055,0x1ff}, + {0x5055,0x1ff}, + {0x6055,0x1ff}, + {0x7055,0x1ff}, + {0x8055,0x1ff}, + {0x9055,0x1ff}, + {0x200c5,0x19}, + {0x1200c5,0x7}, + {0x2002e,0x2}, + {0x12002e,0x1}, + {0x90204,0x0}, + {0x190204,0x0}, + {0x20024,0x1ab}, + {0x2003a,0x0}, + {0x120024,0x1ab}, + {0x2003a,0x0}, + {0x20056,0x3}, + {0x120056,0xa}, + {0x1004d,0xe00}, + {0x1014d,0xe00}, + {0x1104d,0xe00}, + {0x1114d,0xe00}, + {0x1204d,0xe00}, + {0x1214d,0xe00}, + {0x1304d,0xe00}, + {0x1314d,0xe00}, + {0x11004d,0xe00}, + {0x11014d,0xe00}, + {0x11104d,0xe00}, + {0x11114d,0xe00}, + {0x11204d,0xe00}, + {0x11214d,0xe00}, + {0x11304d,0xe00}, + {0x11314d,0xe00}, + {0x10049,0xeba}, + {0x10149,0xeba}, + {0x11049,0xeba}, + {0x11149,0xeba}, + {0x12049,0xeba}, + {0x12149,0xeba}, + {0x13049,0xeba}, + {0x13149,0xeba}, + {0x110049,0xeba}, + {0x110149,0xeba}, + {0x111049,0xeba}, + {0x111149,0xeba}, + {0x112049,0xeba}, + {0x112149,0xeba}, + {0x113049,0xeba}, + {0x113149,0xeba}, + {0x43,0x63}, + {0x1043,0x63}, + {0x2043,0x63}, + {0x3043,0x63}, + {0x4043,0x63}, + {0x5043,0x63}, + {0x6043,0x63}, + {0x7043,0x63}, + {0x8043,0x63}, + {0x9043,0x63}, + {0x20018,0x3}, + {0x20075,0x4}, + {0x20050,0x0}, + {0x20008,0x320}, + {0x120008,0xa7}, + {0x20088,0x9}, + {0x200b2,0xdc}, + {0x10043,0x5a1}, + {0x10143,0x5a1}, + {0x11043,0x5a1}, + {0x11143,0x5a1}, + {0x12043,0x5a1}, + {0x12143,0x5a1}, + {0x13043,0x5a1}, + {0x13143,0x5a1}, + {0x1200b2,0xdc}, + {0x110043,0x5a1}, + {0x110143,0x5a1}, + {0x111043,0x5a1}, + {0x111143,0x5a1}, + {0x112043,0x5a1}, + {0x112143,0x5a1}, + {0x113043,0x5a1}, + {0x113143,0x5a1}, + {0x200fa,0x1}, + {0x1200fa,0x1}, + {0x20019,0x1}, + {0x120019,0x1}, + {0x200f0,0x0}, + {0x200f1,0x0}, + {0x200f2,0x4444}, + {0x200f3,0x8888}, + {0x200f4,0x5555}, + {0x200f5,0x0}, + {0x200f6,0x0}, + {0x200f7,0xf000}, + {0x20025,0x0}, + {0x2002d,0x0}, + {0x12002d,0x0}, + {0x200c7,0x80}, + {0x1200c7,0x80}, + {0x200ca,0x106}, + {0x1200ca,0x106}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xc80}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x131f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x310}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4a66}, + {0x5401c,0x4a08}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4a66}, + {0x54022,0x4a08}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x84a}, + {0x54036,0x4a}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x84a}, + {0x5403c,0x4a}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x1}, + {0x54003,0x29c}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x310}, + {0x54019,0x994}, + {0x5401a,0x31}, + {0x5401b,0x4a66}, + {0x5401c,0x4a08}, + {0x5401e,0x16}, + {0x5401f,0x994}, + {0x54020,0x31}, + {0x54021,0x4a66}, + {0x54022,0x4a08}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0x9400}, + {0x54033,0x3109}, + {0x54034,0x6600}, + {0x54035,0x84a}, + {0x54036,0x4a}, + {0x54037,0x1600}, + {0x54038,0x9400}, + {0x54039,0x3109}, + {0x5403a,0x6600}, + {0x5403b,0x84a}, + {0x5403c,0x4a}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xc80}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x61}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400f,0x100}, + {0x54010,0x1f7f}, + {0x54012,0x310}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4a66}, + {0x5401c,0x4a08}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4a66}, + {0x54022,0x4a08}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x84a}, + {0x54036,0x4a}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x84a}, + {0x5403c,0x4a}, + {0x5403d,0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000,0x10}, + {0x90001,0x400}, + {0x90002,0x10e}, + {0x90003,0x0}, + {0x90004,0x0}, + {0x90005,0x8}, + {0x90029,0xb}, + {0x9002a,0x480}, + {0x9002b,0x109}, + {0x9002c,0x8}, + {0x9002d,0x448}, + {0x9002e,0x139}, + {0x9002f,0x8}, + {0x90030,0x478}, + {0x90031,0x109}, + {0x90032,0x0}, + {0x90033,0xe8}, + {0x90034,0x109}, + {0x90035,0x2}, + {0x90036,0x10}, + {0x90037,0x139}, + {0x90038,0xf}, + {0x90039,0x7c0}, + {0x9003a,0x139}, + {0x9003b,0x44}, + {0x9003c,0x630}, + {0x9003d,0x159}, + {0x9003e,0x14f}, + {0x9003f,0x630}, + {0x90040,0x159}, + {0x90041,0x47}, + {0x90042,0x630}, + {0x90043,0x149}, + {0x90044,0x4f}, + {0x90045,0x630}, + {0x90046,0x179}, + {0x90047,0x8}, + {0x90048,0xe0}, + {0x90049,0x109}, + {0x9004a,0x0}, + {0x9004b,0x7c8}, + {0x9004c,0x109}, + {0x9004d,0x0}, + {0x9004e,0x1}, + {0x9004f,0x8}, + {0x90050,0x0}, + {0x90051,0x45a}, + {0x90052,0x9}, + {0x90053,0x0}, + {0x90054,0x448}, + {0x90055,0x109}, + {0x90056,0x40}, + {0x90057,0x630}, + {0x90058,0x179}, + {0x90059,0x1}, + {0x9005a,0x618}, + {0x9005b,0x109}, + {0x9005c,0x40c0}, + {0x9005d,0x630}, + {0x9005e,0x149}, + {0x9005f,0x8}, + {0x90060,0x4}, + {0x90061,0x48}, + {0x90062,0x4040}, + {0x90063,0x630}, + {0x90064,0x149}, + {0x90065,0x0}, + {0x90066,0x4}, + {0x90067,0x48}, + {0x90068,0x40}, + {0x90069,0x630}, + {0x9006a,0x149}, + {0x9006b,0x10}, + {0x9006c,0x4}, + {0x9006d,0x18}, + {0x9006e,0x0}, + {0x9006f,0x4}, + {0x90070,0x78}, + {0x90071,0x549}, + {0x90072,0x630}, + {0x90073,0x159}, + {0x90074,0xd49}, + {0x90075,0x630}, + {0x90076,0x159}, + {0x90077,0x94a}, + {0x90078,0x630}, + {0x90079,0x159}, + {0x9007a,0x441}, + {0x9007b,0x630}, + {0x9007c,0x149}, + {0x9007d,0x42}, + {0x9007e,0x630}, + {0x9007f,0x149}, + {0x90080,0x1}, + {0x90081,0x630}, + {0x90082,0x149}, + {0x90083,0x0}, + {0x90084,0xe0}, + {0x90085,0x109}, + {0x90086,0xa}, + {0x90087,0x10}, + {0x90088,0x109}, + {0x90089,0x9}, + {0x9008a,0x3c0}, + {0x9008b,0x149}, + {0x9008c,0x9}, + {0x9008d,0x3c0}, + {0x9008e,0x159}, + {0x9008f,0x18}, + {0x90090,0x10}, + {0x90091,0x109}, + {0x90092,0x0}, + {0x90093,0x3c0}, + {0x90094,0x109}, + {0x90095,0x18}, + {0x90096,0x4}, + {0x90097,0x48}, + {0x90098,0x18}, + {0x90099,0x4}, + {0x9009a,0x58}, + {0x9009b,0xa}, + {0x9009c,0x10}, + {0x9009d,0x109}, + {0x9009e,0x2}, + {0x9009f,0x10}, + {0x900a0,0x109}, + {0x900a1,0x5}, + {0x900a2,0x7c0}, + {0x900a3,0x109}, + {0x900a4,0x10}, + {0x900a5,0x10}, + {0x900a6,0x109}, + {0x40000,0x811}, + {0x40020,0x880}, + {0x40040,0x0}, + {0x40060,0x0}, + {0x40001,0x4008}, + {0x40021,0x83}, + {0x40041,0x4f}, + {0x40061,0x0}, + {0x40002,0x4040}, + {0x40022,0x83}, + {0x40042,0x51}, + {0x40062,0x0}, + {0x40003,0x811}, + {0x40023,0x880}, + {0x40043,0x0}, + {0x40063,0x0}, + {0x40004,0x720}, + {0x40024,0xf}, + {0x40044,0x1740}, + {0x40064,0x0}, + {0x40005,0x16}, + {0x40025,0x83}, + {0x40045,0x4b}, + {0x40065,0x0}, + {0x40006,0x716}, + {0x40026,0xf}, + {0x40046,0x2001}, + {0x40066,0x0}, + {0x40007,0x716}, + {0x40027,0xf}, + {0x40047,0x2800}, + {0x40067,0x0}, + {0x40008,0x716}, + {0x40028,0xf}, + {0x40048,0xf00}, + {0x40068,0x0}, + {0x40009,0x720}, + {0x40029,0xf}, + {0x40049,0x1400}, + {0x40069,0x0}, + {0x4000a,0xe08}, + {0x4002a,0xc15}, + {0x4004a,0x0}, + {0x4006a,0x0}, + {0x4000b,0x623}, + {0x4002b,0x15}, + {0x4004b,0x0}, + {0x4006b,0x0}, + {0x4000c,0x4028}, + {0x4002c,0x80}, + {0x4004c,0x0}, + {0x4006c,0x0}, + {0x4000d,0xe08}, + {0x4002d,0xc1a}, + {0x4004d,0x0}, + {0x4006d,0x0}, + {0x4000e,0x623}, + {0x4002e,0x1a}, + {0x4004e,0x0}, + {0x4006e,0x0}, + {0x4000f,0x4040}, + {0x4002f,0x80}, + {0x4004f,0x0}, + {0x4006f,0x0}, + {0x40010,0x2604}, + {0x40030,0x15}, + {0x40050,0x0}, + {0x40070,0x0}, + {0x40011,0x708}, + {0x40031,0x5}, + {0x40051,0x0}, + {0x40071,0x2002}, + {0x40012,0x8}, + {0x40032,0x80}, + {0x40052,0x0}, + {0x40072,0x0}, + {0x40013,0x2604}, + {0x40033,0x1a}, + {0x40053,0x0}, + {0x40073,0x0}, + {0x40014,0x708}, + {0x40034,0xa}, + {0x40054,0x0}, + {0x40074,0x2002}, + {0x40015,0x4040}, + {0x40035,0x80}, + {0x40055,0x0}, + {0x40075,0x0}, + {0x40016,0x60a}, + {0x40036,0x15}, + {0x40056,0x1200}, + {0x40076,0x0}, + {0x40017,0x61a}, + {0x40037,0x15}, + {0x40057,0x1300}, + {0x40077,0x0}, + {0x40018,0x60a}, + {0x40038,0x1a}, + {0x40058,0x1200}, + {0x40078,0x0}, + {0x40019,0x642}, + {0x40039,0x1a}, + {0x40059,0x1300}, + {0x40079,0x0}, + {0x4001a,0x4808}, + {0x4003a,0x880}, + {0x4005a,0x0}, + {0x4007a,0x0}, + {0x900a7,0x0}, + {0x900a8,0x790}, + {0x900a9,0x11a}, + {0x900aa,0x8}, + {0x900ab,0x7aa}, + {0x900ac,0x2a}, + {0x900ad,0x10}, + {0x900ae,0x7b2}, + {0x900af,0x2a}, + {0x900b0,0x0}, + {0x900b1,0x7c8}, + {0x900b2,0x109}, + {0x900b3,0x10}, + {0x900b4,0x2a8}, + {0x900b5,0x129}, + {0x900b6,0x8}, + {0x900b7,0x370}, + {0x900b8,0x129}, + {0x900b9,0xa}, + {0x900ba,0x3c8}, + {0x900bb,0x1a9}, + {0x900bc,0xc}, + {0x900bd,0x408}, + {0x900be,0x199}, + {0x900bf,0x14}, + {0x900c0,0x790}, + {0x900c1,0x11a}, + {0x900c2,0x8}, + {0x900c3,0x4}, + {0x900c4,0x18}, + {0x900c5,0xe}, + {0x900c6,0x408}, + {0x900c7,0x199}, + {0x900c8,0x8}, + {0x900c9,0x8568}, + {0x900ca,0x108}, + {0x900cb,0x18}, + {0x900cc,0x790}, + {0x900cd,0x16a}, + {0x900ce,0x8}, + {0x900cf,0x1d8}, + {0x900d0,0x169}, + {0x900d1,0x10}, + {0x900d2,0x8558}, + {0x900d3,0x168}, + {0x900d4,0x70}, + {0x900d5,0x788}, + {0x900d6,0x16a}, + {0x900d7,0x1ff8}, + {0x900d8,0x85a8}, + {0x900d9,0x1e8}, + {0x900da,0x50}, + {0x900db,0x798}, + {0x900dc,0x16a}, + {0x900dd,0x60}, + {0x900de,0x7a0}, + {0x900df,0x16a}, + {0x900e0,0x8}, + {0x900e1,0x8310}, + {0x900e2,0x168}, + {0x900e3,0x8}, + {0x900e4,0xa310}, + {0x900e5,0x168}, + {0x900e6,0xa}, + {0x900e7,0x408}, + {0x900e8,0x169}, + {0x900e9,0x6e}, + {0x900ea,0x0}, + {0x900eb,0x68}, + {0x900ec,0x0}, + {0x900ed,0x408}, + {0x900ee,0x169}, + {0x900ef,0x0}, + {0x900f0,0x8310}, + {0x900f1,0x168}, + {0x900f2,0x0}, + {0x900f3,0xa310}, + {0x900f4,0x168}, + {0x900f5,0x1ff8}, + {0x900f6,0x85a8}, + {0x900f7,0x1e8}, + {0x900f8,0x68}, + {0x900f9,0x798}, + {0x900fa,0x16a}, + {0x900fb,0x78}, + {0x900fc,0x7a0}, + {0x900fd,0x16a}, + {0x900fe,0x68}, + {0x900ff,0x790}, + {0x90100,0x16a}, + {0x90101,0x8}, + {0x90102,0x8b10}, + {0x90103,0x168}, + {0x90104,0x8}, + {0x90105,0xab10}, + {0x90106,0x168}, + {0x90107,0xa}, + {0x90108,0x408}, + {0x90109,0x169}, + {0x9010a,0x58}, + {0x9010b,0x0}, + {0x9010c,0x68}, + {0x9010d,0x0}, + {0x9010e,0x408}, + {0x9010f,0x169}, + {0x90110,0x0}, + {0x90111,0x8b10}, + {0x90112,0x168}, + {0x90113,0x0}, + {0x90114,0xab10}, + {0x90115,0x168}, + {0x90116,0x0}, + {0x90117,0x1d8}, + {0x90118,0x169}, + {0x90119,0x80}, + {0x9011a,0x790}, + {0x9011b,0x16a}, + {0x9011c,0x18}, + {0x9011d,0x7aa}, + {0x9011e,0x6a}, + {0x9011f,0xa}, + {0x90120,0x0}, + {0x90121,0x1e9}, + {0x90122,0x8}, + {0x90123,0x8080}, + {0x90124,0x108}, + {0x90125,0xf}, + {0x90126,0x408}, + {0x90127,0x169}, + {0x90128,0xc}, + {0x90129,0x0}, + {0x9012a,0x68}, + {0x9012b,0x9}, + {0x9012c,0x0}, + {0x9012d,0x1a9}, + {0x9012e,0x0}, + {0x9012f,0x408}, + {0x90130,0x169}, + {0x90131,0x0}, + {0x90132,0x8080}, + {0x90133,0x108}, + {0x90134,0x8}, + {0x90135,0x7aa}, + {0x90136,0x6a}, + {0x90137,0x0}, + {0x90138,0x8568}, + {0x90139,0x108}, + {0x9013a,0xb7}, + {0x9013b,0x790}, + {0x9013c,0x16a}, + {0x9013d,0x1f}, + {0x9013e,0x0}, + {0x9013f,0x68}, + {0x90140,0x8}, + {0x90141,0x8558}, + {0x90142,0x168}, + {0x90143,0xf}, + {0x90144,0x408}, + {0x90145,0x169}, + {0x90146,0xc}, + {0x90147,0x0}, + {0x90148,0x68}, + {0x90149,0x0}, + {0x9014a,0x408}, + {0x9014b,0x169}, + {0x9014c,0x0}, + {0x9014d,0x8558}, + {0x9014e,0x168}, + {0x9014f,0x8}, + {0x90150,0x3c8}, + {0x90151,0x1a9}, + {0x90152,0x3}, + {0x90153,0x370}, + {0x90154,0x129}, + {0x90155,0x20}, + {0x90156,0x2aa}, + {0x90157,0x9}, + {0x90158,0x0}, + {0x90159,0x400}, + {0x9015a,0x10e}, + {0x9015b,0x8}, + {0x9015c,0xe8}, + {0x9015d,0x109}, + {0x9015e,0x0}, + {0x9015f,0x8140}, + {0x90160,0x10c}, + {0x90161,0x10}, + {0x90162,0x8138}, + {0x90163,0x10c}, + {0x90164,0x8}, + {0x90165,0x7c8}, + {0x90166,0x101}, + {0x90167,0x8}, + {0x90168,0x0}, + {0x90169,0x8}, + {0x9016a,0x8}, + {0x9016b,0x448}, + {0x9016c,0x109}, + {0x9016d,0xf}, + {0x9016e,0x7c0}, + {0x9016f,0x109}, + {0x90170,0x0}, + {0x90171,0xe8}, + {0x90172,0x109}, + {0x90173,0x47}, + {0x90174,0x630}, + {0x90175,0x109}, + {0x90176,0x8}, + {0x90177,0x618}, + {0x90178,0x109}, + {0x90179,0x8}, + {0x9017a,0xe0}, + {0x9017b,0x109}, + {0x9017c,0x0}, + {0x9017d,0x7c8}, + {0x9017e,0x109}, + {0x9017f,0x8}, + {0x90180,0x8140}, + {0x90181,0x10c}, + {0x90182,0x0}, + {0x90183,0x1}, + {0x90184,0x8}, + {0x90185,0x8}, + {0x90186,0x4}, + {0x90187,0x8}, + {0x90188,0x8}, + {0x90189,0x7c8}, + {0x9018a,0x101}, + {0x90006,0x0}, + {0x90007,0x0}, + {0x90008,0x8}, + {0x90009,0x0}, + {0x9000a,0x0}, + {0x9000b,0x0}, + {0xd00e7,0x400}, + {0x90017,0x0}, + {0x9001f,0x2a}, + {0x90026,0x6a}, + {0x400d0,0x0}, + {0x400d1,0x101}, + {0x400d2,0x105}, + {0x400d3,0x107}, + {0x400d4,0x10f}, + {0x400d5,0x202}, + {0x400d6,0x20a}, + {0x400d7,0x20b}, + {0x2003a,0x2}, + {0x2000b,0x64}, + {0x2000c,0xc8}, + {0x2000d,0x7d0}, + {0x2000e,0x2c}, + {0x12000b,0x14}, + {0x12000c,0x29}, + {0x12000d,0x1a1}, + {0x12000e,0x10}, + {0x9000c,0x0}, + {0x9000d,0x173}, + {0x9000e,0x60}, + {0x9000f,0x6110}, + {0x90010,0x2152}, + {0x90011,0xdfbd}, + {0x90012,0x60}, + {0x90013,0x6152}, + {0x20010,0x5a}, + {0x20011,0x3}, + {0x120010,0x5a}, + {0x120011,0x3}, + {0x40080,0xe0}, + {0x40081,0x12}, + {0x40082,0xe0}, + {0x40083,0x12}, + {0x40084,0xe0}, + {0x40085,0x12}, + {0x140080,0xe0}, + {0x140081,0x12}, + {0x140082,0xe0}, + {0x140083,0x12}, + {0x140084,0xe0}, + {0x140085,0x12}, + {0x400fd,0xf}, + {0x10011,0x1}, + {0x10012,0x1}, + {0x10013,0x180}, + {0x10018,0x1}, + {0x10002,0x6209}, + {0x100b2,0x1}, + {0x101b4,0x1}, + {0x102b4,0x1}, + {0x103b4,0x1}, + {0x104b4,0x1}, + {0x105b4,0x1}, + {0x106b4,0x1}, + {0x107b4,0x1}, + {0x108b4,0x1}, + {0x11011,0x1}, + {0x11012,0x1}, + {0x11013,0x180}, + {0x11018,0x1}, + {0x11002,0x6209}, + {0x110b2,0x1}, + {0x111b4,0x1}, + {0x112b4,0x1}, + {0x113b4,0x1}, + {0x114b4,0x1}, + {0x115b4,0x1}, + {0x116b4,0x1}, + {0x117b4,0x1}, + {0x118b4,0x1}, + {0x12011,0x1}, + {0x12012,0x1}, + {0x12013,0x180}, + {0x12018,0x1}, + {0x12002,0x6209}, + {0x120b2,0x1}, + {0x121b4,0x1}, + {0x122b4,0x1}, + {0x123b4,0x1}, + {0x124b4,0x1}, + {0x125b4,0x1}, + {0x126b4,0x1}, + {0x127b4,0x1}, + {0x128b4,0x1}, + {0x13011,0x1}, + {0x13012,0x1}, + {0x13013,0x180}, + {0x13018,0x1}, + {0x13002,0x6209}, + {0x130b2,0x1}, + {0x131b4,0x1}, + {0x132b4,0x1}, + {0x133b4,0x1}, + {0x134b4,0x1}, + {0x135b4,0x1}, + {0x136b4,0x1}, + {0x137b4,0x1}, + {0x138b4,0x1}, + {0x2003a,0x2}, + {0xc0080,0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_2g = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 667, }, +}; diff --git a/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/spl.c b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/spl.c new file mode 100644 index 0000000..1524173 --- /dev/null +++ b/recipes-bsp/u-boot/rvphone/cl-imx8/board/rvphone/cl-imx8/spl.c @@ -0,0 +1,301 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch/ddr.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include "../../freescale/common/pfuze.h" +#include <asm/arch/clock.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <fsl_esdhc.h> +#include <mmc.h> + +#include "common.h" +#include "ddr/ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define CL_SOM_IMX8_1G 0x1 +#define CL_SOM_IMX8_2G 0x2 + +static int get_baseboard_id(void) +{ +#ifdef CONFIG_RAM_1G +#define BOARD_ID CL_SOM_IMX8_1G +#endif +#ifdef CONFIG_RAM_2G +#define BOARD_ID CL_SOM_IMX8_2G +#endif +#ifdef BOARD_ID + return BOARD_ID; +#else +#error "Invalid RAM configuration" +#endif +} + +#define TCM_BOARD_CFG 0x7e0000 +static void set_baseboard_tcm(int board_id) +{ + writel(board_id, TCM_BOARD_CFG); +} + +void spl_dram_init(void) +{ + /* ddr init */ + int board_id = get_baseboard_id(); + set_baseboard_tcm(board_id); + + /* ddr init */ + if ((board_id == CL_SOM_IMX8_2G)) + ddr_init(&dram_timing_2g); + else + ddr_init(&dram_timing_1g); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | PC, + .gp = IMX_GPIO_NR(5, 16), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | PC, + .gp = IMX_GPIO_NR(5, 17), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 1 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return -ENODEV; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return -ENODEV; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Increase the DRAM rail voltage up to 1V125 */ + pmic_reg_read(p, PFUZE100_SW2VOL, ®); + if ((reg & 0x3f) != 0x1E) { + reg &= ~0x3f; + reg |= 0x1E; + pmic_reg_write(p, PFUZE100_SW2VOL, reg); + } + + /* Increase the GPU rail voltage */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, ®); + if ((reg & 0x3f) != 0x1C) { + reg &= ~0x3f; + reg |= 0x1C; + pmic_reg_write(p, PFUZE100_SW1ABVOL, reg); + } + + pmic_reg_read(p, PFUZE100_SW3AVOL, ®); + if ((reg & 0x3f) != 0x18) { + reg &= ~0x3f; + reg |= 0x18; + pmic_reg_write(p, PFUZE100_SW3AVOL, reg); + } + + ret = pfuze_mode_init(p, APS_PFM); + if (ret < 0) + return ret; + + return 0; +} +#endif + +void spl_board_init(void) +{ + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + init_uart_clk(2); /* Init UART3 clock */ + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + /* Adjust pmic voltage to 1.0V for 800M */ + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = spl_boot_device(); + switch (spl_boot_list[0]) { + case BOOT_DEVICE_MMC1: + printf("SPL Boot Device: MMC1\n"); + spl_boot_list[1] = BOOT_DEVICE_MMC2; + break; + case BOOT_DEVICE_MMC2: + printf("SPL Boot Device: MMC2\n"); + spl_boot_list[1] = BOOT_DEVICE_MMC1; + break; + default: + printf("SPL Boot Device: # %d; no 2-nd boot device\n", spl_boot_list[0]); + break; + } +} |