diff options
| author | Uros Majstorovic <majstor@majstor.org> | 2019-07-26 16:40:10 +0200 |
|---|---|---|
| committer | Uros Majstorovic <majstor@majstor.org> | 2019-07-26 16:40:10 +0200 |
| commit | 0fdc7ebc120b99bef9338630e954e773acf15018 (patch) | |
| tree | d0de5d87c981d79d8f518d7730d58b7907442fb3 | |
| parent | df2ebc3201c5ecb25ce104528dc5d98e0ce5fcbb (diff) | |
fixed audio pins for phone board
| -rw-r--r-- | code/fe310/eos/eos.c | 2 | ||||
| -rw-r--r-- | code/fe310/eos/i2s.c | 2 | ||||
| -rw-r--r-- | code/fe310/eos/net.c | 2 | ||||
| -rw-r--r-- | code/fe310/eos/spi_def.h | 7 |
4 files changed, 7 insertions, 6 deletions
diff --git a/code/fe310/eos/eos.c b/code/fe310/eos/eos.c index 3ad3b68..163edfa 100644 --- a/code/fe310/eos/eos.c +++ b/code/fe310/eos/eos.c @@ -13,5 +13,5 @@ void eos_init(void) { } void eos_start(void) { - eos_net_start(15); + eos_net_start(9); }
\ No newline at end of file diff --git a/code/fe310/eos/i2s.c b/code/fe310/eos/i2s.c index 42e185b..7d8baf4 100644 --- a/code/fe310/eos/i2s.c +++ b/code/fe310/eos/i2s.c @@ -21,7 +21,7 @@ EOSABuf _eos_i2s_mic_buf; EOSABuf _eos_i2s_spk_buf; uint32_t _eos_i2s_ck_period = 0; uint32_t _eos_i2s_mic_volume = 0; -uint32_t _eos_i2s_spk_volume = 4; +uint32_t _eos_i2s_spk_volume = 0; static eos_evt_fptr_t evt_handler[I2S_MAX_HANDLER]; uint32_t _eos_i2s_evt_enable[I2S_MAX_HANDLER]; uint32_t _eos_i2s_wm[I2S_MAX_HANDLER]; diff --git a/code/fe310/eos/net.c b/code/fe310/eos/net.c index bcfa1f2..7ef1745 100644 --- a/code/fe310/eos/net.c +++ b/code/fe310/eos/net.c @@ -273,7 +273,7 @@ void eos_net_start(uint32_t sckdiv) { SPI_FMT_LEN(8); // enable CS pin for selected channel/pin - SPI1_REG(SPI_REG_CSID) = 2; + SPI1_REG(SPI_REG_CSID) = SPI_IDX_SS; // There is no way here to change the CS polarity. // SPI1_REG(SPI_REG_CSDEF) = 0xFFFF; diff --git a/code/fe310/eos/spi_def.h b/code/fe310/eos/spi_def.h index c49a73b..e73b5e3 100644 --- a/code/fe310/eos/spi_def.h +++ b/code/fe310/eos/spi_def.h @@ -10,9 +10,10 @@ #define SPI_SIZE_CHUNK 4 #define SPI_SIZE_WM 2 -#define SPI_PIN_RTS 0 -#define SPI_PIN_CTS 23 -#define SPI_PIN_CS IOF_SPI1_SS0 +#define SPI_PIN_RTS 21 +#define SPI_PIN_CTS 22 +#define SPI_PIN_CS 10 +#define SPI_IDX_SS 3 #define SPI_FLAG_RDY 0x01 #define SPI_FLAG_RST 0x02 |