added test app with voice, wifi/cellular data connectivity examples

6 files changed, 92 insertions, 46 deletions

diff --git a/fw/fe310/bsp/include/platform.h b/fw/fe310/bsp/include/platform.h
index 5178d86..46ce61c 100644
--- a/fw/fe310/bsp/include/platform.h
+++ b/fw/fe310/bsp/include/platform.h
@@ -18,6 +18,7 @@
 #include "sifive/devices/prci.h"
 #include "sifive/devices/pwm.h"
 #include "sifive/devices/spi.h"
+#include "sifive/devices/i2c.h"
 #include "sifive/devices/uart.h"
 
 /****************************************************************************
@@ -37,6 +38,7 @@
 #define UART0_CTRL_ADDR _AC(0x10013000,UL)
 #define SPI0_CTRL_ADDR _AC(0x10014000,UL)
 #define PWM0_CTRL_ADDR _AC(0x10015000,UL)
+#define I2C0_CTRL_ADDR _AC(0x10016000,UL)
 #define UART1_CTRL_ADDR _AC(0x10023000,UL)
 #define SPI1_CTRL_ADDR _AC(0x10024000,UL)
 #define PWM1_CTRL_ADDR _AC(0x10025000,UL)
@@ -47,43 +49,45 @@
 
 // IOF masks
 #define IOF0_SPI1_MASK          _AC(0x000007FC,UL)
-#define SPI11_NUM_SS     (4)
-#define IOF_SPI1_SS0          (2u)
-#define IOF_SPI1_SS1          (8u)
-#define IOF_SPI1_SS2          (9u)
-#define IOF_SPI1_SS3          (10u)
-#define IOF_SPI1_MOSI         (3u)
-#define IOF_SPI1_MISO         (4u)
-#define IOF_SPI1_SCK          (5u)
-#define IOF_SPI1_DQ0          (3u)
-#define IOF_SPI1_DQ1          (4u)
-#define IOF_SPI1_DQ2          (6u)
-#define IOF_SPI1_DQ3          (7u)
+#define SPI11_NUM_SS            (4)
+#define IOF_SPI1_SS0            (2u)
+#define IOF_SPI1_SS1            (8u)
+#define IOF_SPI1_SS2            (9u)
+#define IOF_SPI1_SS3            (10u)
+#define IOF_SPI1_MOSI           (3u)
+#define IOF_SPI1_MISO           (4u)
+#define IOF_SPI1_SCK            (5u)
+#define IOF_SPI1_DQ0            (3u)
+#define IOF_SPI1_DQ1            (4u)
+#define IOF_SPI1_DQ2            (6u)
+#define IOF_SPI1_DQ3            (7u)
 
 #define IOF0_SPI2_MASK          _AC(0xFC000000,UL)
-#define SPI2_NUM_SS       (1)
-#define IOF_SPI2_SS0          (26u)
-#define IOF_SPI2_MOSI         (27u)
-#define IOF_SPI2_MISO         (28u)
-#define IOF_SPI2_SCK          (29u)
-#define IOF_SPI2_DQ0          (27u)
-#define IOF_SPI2_DQ1          (28u)
-#define IOF_SPI2_DQ2          (30u)
-#define IOF_SPI2_DQ3          (31u)
-
-//#define IOF0_I2C_MASK          _AC(0x00003000,UL)
-
-#define IOF0_UART0_MASK         _AC(0x00030000, UL)
-#define IOF_UART0_RX   (16u)
-#define IOF_UART0_TX   (17u)
-
-#define IOF0_UART1_MASK         _AC(0x03000000, UL)
-#define IOF_UART1_RX (24u)
-#define IOF_UART1_TX (25u)
-
-#define IOF1_PWM0_MASK          _AC(0x0000000F, UL)
-#define IOF1_PWM1_MASK          _AC(0x00780000, UL)
-#define IOF1_PWM2_MASK          _AC(0x00003C00, UL)
+#define SPI2_NUM_SS             (1)
+#define IOF_SPI2_SS0            (26u)
+#define IOF_SPI2_MOSI           (27u)
+#define IOF_SPI2_MISO           (28u)
+#define IOF_SPI2_SCK            (29u)
+#define IOF_SPI2_DQ0            (27u)
+#define IOF_SPI2_DQ1            (28u)
+#define IOF_SPI2_DQ2            (30u)
+#define IOF_SPI2_DQ3            (31u)
+
+#define IOF0_I2C0_MASK          _AC(0x00003000,UL)
+#define IOF_I2C0_SCL            (13u)
+#define IOF_I2C0_SDA            (12u)
+
+#define IOF0_UART0_MASK         _AC(0x00030000,UL)
+#define IOF_UART0_RX            (16u)
+#define IOF_UART0_TX            (17u)
+
+#define IOF0_UART1_MASK         _AC(0x00840000,UL)
+#define IOF_UART1_RX            (23u)
+#define IOF_UART1_TX            (18u)
+
+#define IOF1_PWM0_MASK          _AC(0x0000000F,UL)
+#define IOF1_PWM1_MASK          _AC(0x00780000,UL)
+#define IOF1_PWM2_MASK          _AC(0x00003C00,UL)
 
 // Interrupt numbers
 #define INT_RESERVED 0
@@ -98,9 +102,14 @@
 #define INT_PWM0_BASE 40
 #define INT_PWM1_BASE 44
 #define INT_PWM2_BASE 48
+#define INT_I2C0_BASE 52
 
 // Helper functions
+#define _REG8(p, i) (*(volatile uint8_t *) ((p) + (i)))
+#define _REG16(p, i) (*(volatile uint16_t *) ((p) + (i)))
 #define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
+#define _REG8P(p, i) ((volatile uint8_t *) ((p) + (i)))
+#define _REG16P(p, i) ((volatile uint16_t *) ((p) + (i)))
 #define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
 #define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
 #define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
@@ -114,6 +123,8 @@
 #define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
 #define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
 #define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
+#define I2C0_REG(offset) _REG32(I2C0_CTRL_ADDR, offset)
+#define I2C0_REGB(offset) _REG8(I2C0_CTRL_ADDR, offset)
 #define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
 #define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
 
diff --git a/fw/fe310/bsp/include/sifive/devices/aon.h b/fw/fe310/bsp/include/sifive/devices/aon.h
index 63f1db3..4a3332c 100644
--- a/fw/fe310/bsp/include/sifive/devices/aon.h
+++ b/fw/fe310/bsp/include/sifive/devices/aon.h
@@ -57,6 +57,7 @@
 #define AON_PMUKEY      0x14C
 
 #define AON_LFROSC      0x070
+
 /* Constants */
 
 #define AON_WDOGKEY_VALUE  0x51F15E
diff --git a/fw/fe310/bsp/include/sifive/devices/clint.h b/fw/fe310/bsp/include/sifive/devices/clint.h
index cd3e0c7..617b657 100644
--- a/fw/fe310/bsp/include/sifive/devices/clint.h
+++ b/fw/fe310/bsp/include/sifive/devices/clint.h
@@ -4,11 +4,11 @@
 #define _SIFIVE_CLINT_H
 
 
-#define CLINT_MSIP 0x0000
-#define CLINT_MSIP_size   0x4
-#define CLINT_MTIMECMP 0x4000
+#define CLINT_MSIP          0x0000
+#define CLINT_MSIP_size     0x4
+#define CLINT_MTIMECMP      0x4000
 #define CLINT_MTIMECMP_size 0x8
-#define CLINT_MTIME 0xBFF8
-#define CLINT_MTIME_size 0x8
+#define CLINT_MTIME         0xBFF8
+#define CLINT_MTIME_size    0x8
 
-#endif /* _SIFIVE_CLINT_H */ 
+#endif /* _SIFIVE_CLINT_H */
diff --git a/fw/fe310/bsp/include/sifive/devices/gpio.h b/fw/fe310/bsp/include/sifive/devices/gpio.h
index f7f0acb..835ac83 100644
--- a/fw/fe310/bsp/include/sifive/devices/gpio.h
+++ b/fw/fe310/bsp/include/sifive/devices/gpio.h
@@ -19,6 +19,6 @@
 #define GPIO_LOW_IP     (0x34)
 #define GPIO_IOF_EN     (0x38)
 #define GPIO_IOF_SEL    (0x3C)
-#define GPIO_OUTPUT_XOR    (0x40)
+#define GPIO_OUTPUT_XOR (0x40)
 
 #endif /* _SIFIVE_GPIO_H */
diff --git a/fw/fe310/bsp/include/sifive/devices/i2c.h b/fw/fe310/bsp/include/sifive/devices/i2c.h
new file mode 100644
index 0000000..900e238
--- /dev/null
+++ b/fw/fe310/bsp/include/sifive/devices/i2c.h
@@ -0,0 +1,34 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_I2C_H
+#define _SIFIVE_I2C_H
+
+/* Register offsets */
+
+#define I2C_PRESCALE_LOW   0x00
+#define I2C_PRESCALE_HIGH  0x04
+#define I2C_CONTROL        0x08
+#define I2C_TRANSMIT       0x0c
+#define I2C_RECEIVE        0x0c
+#define I2C_COMMAND        0x10
+#define I2C_STATUS         0x10
+
+/* Constants */
+
+#define I2C_CONTROL_EN      (1UL << 7)
+#define I2C_CONTROL_IE      (1UL << 6)
+#define I2C_WRITE           (0UL << 0)
+#define I2C_READ            (1UL << 0)
+#define I2C_CMD_START       (1UL << 7)
+#define I2C_CMD_STOP        (1UL << 6)
+#define I2C_CMD_READ        (1UL << 5)
+#define I2C_CMD_WRITE       (1UL << 4)
+#define I2C_CMD_ACK         (1UL << 3)
+#define I2C_CMD_IACK        (1UL << 0)
+#define I2C_STATUS_RXACK    (1UL << 7)
+#define I2C_STATUS_BUSY     (1UL << 6)
+#define I2C_STATUS_AL       (1UL << 5)
+#define I2C_STATUS_TIP      (1UL << 1)
+#define I2C_STATUS_IP       (1UL << 0)
+
+#endif /* _SIFIVE_I2C_H */
diff --git a/fw/fe310/bsp/include/sifive/devices/prci.h b/fw/fe310/bsp/include/sifive/devices/prci.h
index 1a3de58..d46da08 100644
--- a/fw/fe310/bsp/include/sifive/devices/prci.h
+++ b/fw/fe310/bsp/include/sifive/devices/prci.h
@@ -12,13 +12,13 @@
 #define PRCI_PROCMONCFG  (0x00F0)
 
 /* Fields */
-#define ROSC_DIV(x)    (((x) & 0x2F) << 0 ) 
+#define ROSC_DIV(x)    (((x) & 0x2F) << 0 )
 #define ROSC_TRIM(x)   (((x) & 0x1F) << 16)
-#define ROSC_EN(x)     (((x) & 0x1 ) << 30) 
+#define ROSC_EN(x)     (((x) & 0x1 ) << 30)
 #define ROSC_RDY(x)    (((x) & 0x1 ) << 31)
 
-#define XOSC_EN(x)     (((x) & 0x1) << 30)
-#define XOSC_RDY(x)    (((x) & 0x1) << 31)
+#define XOSC_EN(x)     (((x) & 0x1)  << 30)
+#define XOSC_RDY(x)    (((x) & 0x1)  << 31)
 
 #define PLL_R(x)       (((x) & 0x7)  << 0)
 // single reserved bit for F LSB.