diff options
| author | Uros Majstorovic <majstor@majstor.org> | 2022-08-09 22:23:08 +0200 |
|---|---|---|
| committer | Uros Majstorovic <majstor@majstor.org> | 2022-08-09 22:23:08 +0200 |
| commit | 3f913efda03fd840cd526ef72e6f397c7da61bd7 (patch) | |
| tree | 08f62c93e0e0660fdb7beba32276ff1ceb7a8a3c /fw/fe310/eos/board.h | |
| parent | 810dde21ee65653c15606917b19566cfbaaf165e (diff) | |
code layout
Diffstat (limited to 'fw/fe310/eos/board.h')
| -rw-r--r-- | fw/fe310/eos/board.h | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/fw/fe310/eos/board.h b/fw/fe310/eos/board.h index 99832a7..3891c61 100644 --- a/fw/fe310/eos/board.h +++ b/fw/fe310/eos/board.h @@ -5,30 +5,33 @@ #define SPI_CSID_NET 0 #define SPI_CSID_EVE 3 -#define SPI_CSID_SDC SPI_CSID_NONE +#define SPI_CSID_SDC -1 #define SPI_CSID_CAM 2 -#define SPI_IOF_MASK ((1 << IOF_SPI1_SCK) | (1 << IOF_SPI1_MOSI) | (1 << IOF_SPI1_MISO) | (1 << IOF_SPI1_SS0) | (1 << IOF_SPI1_SS2) | (1 << IOF_SPI1_SS3)) - -#define SPI_CSPIN_NET 2 -#define SPI_CSPIN_EVE 10 +#define SPI_CSPIN_NET -1 +#define SPI_CSPIN_EVE -1 #define SPI_CSPIN_SDC 0 -#define SPI_CSPIN_CAM 9 +#define SPI_CSPIN_CAM -1 + +#define SPI_CSPIN_LCD 11 + +#define SPI_IOF_MASK ((1 << IOF_SPI1_SCK) | (1 << IOF_SPI1_MOSI) | (1 << IOF_SPI1_MISO) | (1 << IOF_SPI1_SS0) | (1 << IOF_SPI1_SS2) | (1 << IOF_SPI1_SS3)) #define NET_PIN_RTS 20 #define NET_PIN_CTS 22 -#define LCD_PIN_CS 11 - -#define EVE_PIN_INTR 23 +#define EVE_PIN_INTR 1 +//#define EVE_PIN_INTR 23 #define I2S_PIN_CK 1 /* PWM 0.1 */ #define I2S_PIN_CK_SW 21 /* PWM 1.2 */ #define I2S_PIN_CK_SR 18 #define I2S_PIN_WS_MIC 19 /* PWM 1.1 */ #define I2S_PIN_WS_SPK 11 /* PWM 2.1 */ -#define I2S_PIN_SD_IN 13 -#define I2S_PIN_SD_OUT 12 +#define I2S_PIN_SD_IN 17 +#define I2S_PIN_SD_OUT 16 +//#define I2S_PIN_SD_IN 13 +//#define I2S_PIN_SD_OUT 12 #define I2S_IRQ_WS_ID (INT_PWM2_BASE + 0) #define I2S_IRQ_SD_ID (INT_PWM2_BASE + 3) @@ -39,7 +42,8 @@ #define I2S_IDLE_CYCLES 1 -#define CTP_PIN_INT 1 +//#define CTP_PIN_INT 1 +#define CTP_PIN_INT 23 #define CTP_PIN_RST 19 #define EVE_GPIO_DIR 0xf |