i2s driver fixed; added uart programming;

6 files changed, 201 insertions, 26 deletions

diff --git a/fw/fe310/eos/dev/Makefile b/fw/fe310/eos/dev/Makefile
index a5d3f77..611b24f 100644
--- a/fw/fe310/eos/dev/Makefile
+++ b/fw/fe310/eos/dev/Makefile
@@ -1,7 +1,7 @@
 include ../../common.mk
 CFLAGS += -I$(bsp_dir)/include -I$(ext_dir)/crypto
 
-obj = spi.o net.o bq25895.o sdcard.o sdc_crypto.o lcd.o gt911.o ili9806e.o eve.o ov2640.o cam.o
+obj = flash.o spi.o net.o bq25895.o sdcard.o sdc_crypto.o lcd.o gt911.o ili9806e.o eve.o ov2640.o cam.o
 lib = ../../libeos-dev.a
 
 
diff --git a/fw/fe310/eos/dev/flash.c b/fw/fe310/eos/dev/flash.c
new file mode 100644
index 0000000..4f017b3
--- /dev/null
+++ b/fw/fe310/eos/dev/flash.c
@@ -0,0 +1,162 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "encoding.h"
+#include "platform.h"
+
+#include "eos.h"
+#include "soc/timer.h"
+
+#include "flash.h"
+
+#define IDLE_TICKS  10
+
+__attribute__ ((section (".itim.flash")))
+static void send(uint8_t data) {
+    while (SPI0_REG(SPI_REG_TXFIFO) & SPI_TXFIFO_FULL);
+    SPI0_REG(SPI_REG_TXFIFO) = data;
+}
+
+__attribute__ ((section (".itim.flash")))
+static uint8_t xfer(uint8_t data) {
+    volatile uint32_t x = 0;
+
+    send(data);
+    while ((x = SPI0_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY);
+    return x;
+}
+
+void eos_flash_init(void) {
+    SPI0_REG(SPI_REG_FMT) |= SPI_FMT_DIR(SPI_DIR_TX);
+    SPI0_REG(SPI_REG_TXCTRL) = SPI_TXWM(1);
+    eos_flash_norm();
+}
+
+__attribute__ ((section (".itim.flash")))
+void eos_flash_norm(void) {
+    volatile uint64_t *mtime = (uint64_t *) (CLINT_CTRL_ADDR + CLINT_MTIME);
+    uint32_t mtime0;
+
+    clear_csr(mstatus, MSTATUS_MIE);
+    SPI0_REG(SPI_REG_FCTRL) = 0;
+
+    SPI0_REG(SPI_REG_SCKDIV) = 3;
+    if (SPI0_REG(SPI_REG_FMT) & SPI_FMT_PROTO(SPI_PROTO_Q)) {
+        send(EOS_FLASH_QPIDI);
+        while (!(SPI0_REG(SPI_REG_IP) & SPI_IP_TXWM));
+    }
+
+    SPI0_REG(SPI_REG_FMT) = \
+        SPI_FMT_PROTO(SPI_PROTO_S)      |
+        SPI_FMT_ENDIAN(SPI_ENDIAN_MSB)  |
+        SPI_FMT_DIR(SPI_DIR_TX)         |
+        SPI_FMT_LEN(8);
+
+    SPI0_REG(SPI_REG_FFMT) =
+        SPI_INSN_CMD_EN         |
+        SPI_INSN_ADDR_LEN(3)    |
+	    SPI_INSN_PAD_CNT(0)     |
+	    SPI_INSN_CMD_PROTO(SPI_PROTO_S)     |
+	    SPI_INSN_ADDR_PROTO(SPI_PROTO_S)    |
+	    SPI_INSN_DATA_PROTO(SPI_PROTO_S)    |
+	    SPI_INSN_CMD_CODE(EOS_FLASH_NORD)   |
+	    SPI_INSN_PAD_CODE(0x00);
+
+    mtime0 = *mtime;
+    while ((*mtime - mtime0) < IDLE_TICKS);
+
+    SPI0_REG(SPI_REG_FCTRL) = SPI_FCTRL_EN;
+    set_csr(mstatus, MSTATUS_MIE);
+}
+
+__attribute__ ((section (".itim.flash")))
+void eos_flash_fast(void) {
+    volatile uint64_t *mtime = (uint64_t *) (CLINT_CTRL_ADDR + CLINT_MTIME);
+    uint32_t mtime0;
+
+    clear_csr(mstatus, MSTATUS_MIE);
+    SPI0_REG(SPI_REG_FCTRL) = 0;
+
+    SPI0_REG(SPI_REG_SCKDIV) = 2;
+    if (!(SPI0_REG(SPI_REG_FMT) & SPI_FMT_PROTO(SPI_PROTO_Q))) {
+        send(EOS_FLASH_QPIEN);
+        while (!(SPI0_REG(SPI_REG_IP) & SPI_IP_TXWM));
+    }
+
+    SPI0_REG(SPI_REG_FMT) = \
+        SPI_FMT_PROTO(SPI_PROTO_Q)      |
+        SPI_FMT_ENDIAN(SPI_ENDIAN_MSB)  |
+        SPI_FMT_DIR(SPI_DIR_TX)         |
+        SPI_FMT_LEN(8);
+
+    SPI0_REG(SPI_REG_FFMT) =
+        SPI_INSN_CMD_EN         |
+        SPI_INSN_ADDR_LEN(3)    |
+	    SPI_INSN_PAD_CNT(6)     |
+	    SPI_INSN_CMD_PROTO(SPI_PROTO_Q)     |
+	    SPI_INSN_ADDR_PROTO(SPI_PROTO_Q)    |
+	    SPI_INSN_DATA_PROTO(SPI_PROTO_Q)    |
+	    SPI_INSN_CMD_CODE(EOS_FLASH_FRD)    |
+	    SPI_INSN_PAD_CODE(0x00);
+
+    mtime0 = *mtime;
+    while ((*mtime - mtime0) < IDLE_TICKS);
+
+    SPI0_REG(SPI_REG_FCTRL) = SPI_FCTRL_EN;
+    set_csr(mstatus, MSTATUS_MIE);
+}
+
+__attribute__ ((section (".itim.flash")))
+void eos_flash_wip(void) {
+    uint8_t status;
+
+    do {
+        SPI0_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD;
+        xfer(EOS_FLASH_RDSR);
+        status = xfer(0);
+        SPI0_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
+    } while (status & EOS_FLASH_WIP);
+}
+
+__attribute__ ((section (".itim.flash")))
+void eos_flash_wren(void) {
+    uint8_t status;
+
+    xfer(EOS_FLASH_WREN);
+#if 0
+    do {
+        SPI0_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD;
+        xfer(EOS_FLASH_RDSR);
+        status = xfer(0);
+        SPI0_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
+    } while (!(status & EOS_FLASH_WEL));
+#endif
+}
+
+__attribute__ ((section (".itim.flash")))
+void eos_flash_ser(uint32_t addr) {
+    SPI0_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD;
+    xfer(EOS_FLASH_SER);
+    xfer(addr >> 16);
+    xfer(addr >> 8);
+    xfer(addr);
+    SPI0_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
+}
+
+__attribute__ ((section (".itim.flash")))
+void eos_flash_pp(uint32_t addr, uint8_t *buf) {
+    int i;
+
+    SPI0_REG(SPI_REG_FMT) |= SPI_FMT_DIR(SPI_DIR_TX);
+    SPI0_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD;
+    send(EOS_FLASH_PP);
+    send(addr >> 16);
+    send(addr >> 8);
+    send(addr);
+    for (i=0; i<256; i++) {
+        send(buf[i]);
+    }
+    while (!(SPI0_REG(SPI_REG_IP) & SPI_IP_TXWM));
+    SPI0_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
+    SPI0_REG(SPI_REG_FMT) &= ~SPI_FMT_DIR(SPI_DIR_TX);
+}
diff --git a/fw/fe310/eos/dev/flash.h b/fw/fe310/eos/dev/flash.h
new file mode 100644
index 0000000..6f792cb
--- /dev/null
+++ b/fw/fe310/eos/dev/flash.h
@@ -0,0 +1,25 @@
+#include <stdint.h>
+
+#define EOS_FLASH_RDSR      0x05
+
+#define EOS_FLASH_NORD      0x03
+#define EOS_FLASH_FRD       0x0b
+
+#define EOS_FLASH_WREN      0x06
+#define EOS_FLASH_SER       0x20
+#define EOS_FLASH_PP        0x02
+
+#define EOS_FLASH_QPIEN     0x35
+#define EOS_FLASH_QPIDI     0xF5
+
+#define EOS_FLASH_WIP       0x01
+#define EOS_FLASH_WEL       0x02
+
+void eos_flash_init(void);
+void eos_flash_norm(void);
+void eos_flash_fast(void);
+
+void eos_flash_wip(void);
+void eos_flash_wren(void);
+void eos_flash_ser(uint32_t addr);
+void eos_flash_pp(uint32_t addr, uint8_t *buf);
\ No newline at end of file
diff --git a/fw/fe310/eos/dev/gt911.c b/fw/fe310/eos/dev/gt911.c
index 6fc2e1f..d047ef2 100644
--- a/fw/fe310/eos/dev/gt911.c
+++ b/fw/fe310/eos/dev/gt911.c
@@ -130,7 +130,7 @@ static uint8_t gt911_chksum(uint8_t *buf,  uint8_t len) {
         csum += buf[i];
     }
 
-    //csum %= 256;
+    // csum %= 256;
     csum = (~csum) + 1;
 
     return csum;
diff --git a/fw/fe310/eos/dev/net.c b/fw/fe310/eos/dev/net.c
index 3811368..11250bc 100644
--- a/fw/fe310/eos/dev/net.c
+++ b/fw/fe310/eos/dev/net.c
@@ -91,7 +91,6 @@ static void net_xchg_wake(void) {
     SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
 }
 
-__attribute__ ((section (".itim")))
 static void net_xchg_reset(void) {
     volatile uint32_t x = 0;
     net_state_flags &= ~NET_STATE_FLAG_CTS;
@@ -104,7 +103,6 @@ static void net_xchg_reset(void) {
     SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
 }
 
-__attribute__ ((section (".itim")))
 static void net_xchg_start(unsigned char type, unsigned char *buffer, uint16_t len) {
     net_state_flags &= ~NET_STATE_FLAG_CTS;
     net_state_flags |= (NET_STATE_FLAG_INIT | NET_STATE_FLAG_XCHG);
@@ -125,7 +123,6 @@ static void net_xchg_start(unsigned char type, unsigned char *buffer, uint16_t l
     SPI1_REG(SPI_REG_IE) = SPI_IP_RXWM;
 }
 
-__attribute__ ((section (".itim")))
 static int net_xchg_next(unsigned char *_buffer) {
     unsigned char type;
     unsigned char *buffer = NULL;
@@ -148,7 +145,6 @@ static int net_xchg_next(unsigned char *_buffer) {
     return ret;
 }
 
-__attribute__ ((section (".itim")))
 static void net_handle_xchg(void) {
     if (net_state_flags & NET_STATE_FLAG_INIT) {
         volatile uint32_t r1, r2, r3;
@@ -207,7 +203,6 @@ static void net_handle_xchg(void) {
     }
 }
 
-// __attribute__ ((section (".itim")))
 static void net_handle_cts(void) {
     GPIO_REG(GPIO_RISE_IP) = (1 << NET_PIN_CTS);
     net_state_flags |= NET_STATE_FLAG_CTS;
@@ -217,7 +212,6 @@ static void net_handle_cts(void) {
     }
 }
 
-__attribute__ ((section (".itim")))
 static void net_handle_rts(void) {
     uint32_t rts_offset = (1 << NET_PIN_RTS);
 
@@ -233,7 +227,6 @@ static void net_handle_rts(void) {
     }
 }
 
-__attribute__ ((section (".itim")))
 static void net_handle_evt(unsigned char type, unsigned char *buffer, uint16_t len) {
     unsigned char idx = (type & ~EOS_EVT_MASK) - 1;
 
@@ -244,7 +237,6 @@ static void net_handle_evt(unsigned char type, unsigned char *buffer, uint16_t l
     }
 }
 
-__attribute__ ((section (".itim")))
 static int net_acquire(unsigned char reserved) {
     int ret = 0;
 
@@ -271,7 +263,6 @@ static int net_acquire(unsigned char reserved) {
     return ret;
 }
 
-__attribute__ ((section (".itim")))
 static void evt_handler_wrapper(unsigned char type, unsigned char *buffer, uint16_t len, unsigned char idx, uint16_t flag) {
     int ok;
 
@@ -286,7 +277,6 @@ static void evt_handler_wrapper(unsigned char type, unsigned char *buffer, uint1
     }
 }
 
-__attribute__ ((section (".itim")))
 static void evt_handler(unsigned char type, unsigned char *buffer, uint16_t len) {
     unsigned char idx = (type & EOS_EVT_MASK) >> 4;
 
@@ -413,8 +403,7 @@ void eos_net_stop(void) {
 }
 
 int eos_net_sleep(uint32_t timeout) {
-    volatile uint64_t *mtime = (uint64_t *) (CLINT_CTRL_ADDR + CLINT_MTIME);
-    uint64_t then_ms = timeout + *mtime * 1000 / EOS_TIMER_RTC_FREQ;
+    uint32_t start;
     uint8_t done = 0;
     int rv = EOS_OK;
 
@@ -424,8 +413,9 @@ int eos_net_sleep(uint32_t timeout) {
 
     if (rv) return rv;
 
+    start = eos_time_get_tick();
     do {
-        if (*mtime * 1000 / EOS_TIMER_RTC_FREQ > then_ms) return EOS_ERR_TIMEOUT;
+        if (eos_time_delta_ms(start) > timeout) return EOS_ERR_TIMEOUT;
         clear_csr(mstatus, MSTATUS_MIE);
         eos_evtq_flush_isr();
         done = (eos_msgq_len(&net_send_q) == 0);
@@ -438,7 +428,7 @@ int eos_net_sleep(uint32_t timeout) {
     } while (!done);
 
     while (!(GPIO_REG(GPIO_RISE_IP) & (1 << NET_PIN_CTS))) {
-        if (*mtime * 1000 / EOS_TIMER_RTC_FREQ > then_ms) {
+        if (eos_time_delta_ms(start) > timeout) {
             rv = EOS_ERR_TIMEOUT;
             break;
         }
@@ -476,13 +466,11 @@ void eos_net_acquire_for_evt(unsigned char type, char acq) {
     }
 }
 
-__attribute__ ((section (".itim")))
 void eos_net_acquire(void) {
     unsigned char acq = net_acquire(0);
     if (!acq) net_acquire(1);
 }
 
-__attribute__ ((section (".itim")))
 void eos_net_release(void) {
     clear_csr(mstatus, MSTATUS_MIE);
     if (!net_state_next_cnt && net_state_next_buf) {
@@ -492,7 +480,6 @@ void eos_net_release(void) {
     set_csr(mstatus, MSTATUS_MIE);
 }
 
-__attribute__ ((section (".itim")))
 unsigned char *eos_net_alloc(void) {
     unsigned char *ret = NULL;
 
@@ -510,7 +497,6 @@ unsigned char *eos_net_alloc(void) {
     return ret;
 }
 
-__attribute__ ((section (".itim")))
 void eos_net_free(unsigned char *buffer, unsigned char more) {
     uint8_t do_release = 1;
 
@@ -528,7 +514,6 @@ void eos_net_free(unsigned char *buffer, unsigned char more) {
     set_csr(mstatus, MSTATUS_MIE);
 }
 
-__attribute__ ((section (".itim")))
 static int net_xchg(unsigned char *type, unsigned char *buffer, uint16_t *len, unsigned char flags) {
     int rv = EOS_OK;
     int _sync = 0;
@@ -594,7 +579,6 @@ int eos_net_send(unsigned char type, unsigned char *buffer, uint16_t len) {
     return net_xchg(&type, buffer, &len, (EOS_NET_FLAG_ONEW | EOS_NET_FLAG_SYNC));
 }
 
-__attribute__ ((section (".itim")))
 int eos_net_send_async(unsigned char type, unsigned char *buffer, uint16_t len, unsigned char more) {
     int rv;
 
diff --git a/fw/fe310/eos/dev/sdcard.c b/fw/fe310/eos/dev/sdcard.c
index 656d27a..a2ee598 100644
--- a/fw/fe310/eos/dev/sdcard.c
+++ b/fw/fe310/eos/dev/sdcard.c
@@ -170,6 +170,7 @@ static int sdc_ready(uint32_t timeout) {
     uint32_t start;
 
     if (timeout == 0) return EOS_ERR_BUSY;
+
     start = eos_time_get_tick();
     do {
         if (eos_time_delta_ms(start) > timeout) break;
@@ -185,6 +186,7 @@ static int sdc_block_read(uint8_t *buffer, uint16_t len, uint32_t timeout) {
     uint32_t start;
 
     if (timeout == 0) return EOS_ERR_BUSY;
+
     start = eos_time_get_tick();
     do {
         if (eos_time_delta_ms(start) > timeout) break;
@@ -254,8 +256,8 @@ static int sdc_init(uint32_t timeout) {
     uint8_t _type;
     uint8_t ocr[4];
     uint32_t start;
-    start = eos_time_get_tick();
 
+    start = eos_time_get_tick();
     eos_time_sleep(100);
     for (i=10; i--;) sdc_xchg8(0xff);     /* 80 dummy cycles */
 
@@ -380,8 +382,9 @@ uint8_t eos_sdc_cap(void) {
 int eos_sdc_get_sect_count(uint32_t timeout, uint32_t *sectors) {
     int rv;
     uint8_t csd[16];
-    uint32_t start = eos_time_get_tick();
+    uint32_t start;
 
+    start = eos_time_get_tick();
     sdc_select();
     rv = sdc_cmd(SEND_CSD, 0, SDC_CMD_FLAG_NOCS, timeout);
     if (rv == SDC_R1_READY) {
@@ -406,8 +409,9 @@ int eos_sdc_get_sect_count(uint32_t timeout, uint32_t *sectors) {
 int eos_sdc_get_blk_size(uint32_t timeout, uint32_t *size) {
     int rv;
     uint8_t rbl[64];    /* SD Status or CSD register */
-    uint32_t start = eos_time_get_tick();
-
+    uint32_t start;
+    
+    start = eos_time_get_tick();
     sdc_select();
     if (sdc_type & EOS_SDC_TYPE_SDC2) {
         rv = sdc_acmd(SD_STATUS, 0, SDC_CMD_FLAG_NOCS, timeout);