code layout

19 files changed, 247 insertions, 1196 deletions

diff --git a/fw/fe310/eos/soc/Makefile b/fw/fe310/eos/soc/Makefile
new file mode 100644
index 0000000..1404c81
--- /dev/null
+++ b/fw/fe310/eos/soc/Makefile
@@ -0,0 +1,20 @@
+include ../../common.mk
+CFLAGS += -I$(bsp_dir)/include -I$(bsp_dir)/drivers
+
+obj = trap_entry.o interrupt.o timer.o pwr.o i2s.o i2c.o uart.o spi.o
+lib = ../../libeos-soc.a
+
+
+%.o: %.c %.h
+	$(CC) $(CFLAGS) -c $<
+
+%.o: %.S
+	$(CC) $(CFLAGS) -c $<
+
+all: $(lib)
+
+$(lib): $(obj)
+	$(AR) rcs $@ $(obj)
+
+clean:
+	rm -f *.o $(lib)
diff --git a/fw/fe310/eos/soc/i2c.c b/fw/fe310/eos/soc/i2c.c
index a507af1..553a9bf 100644
--- a/fw/fe310/eos/soc/i2c.c
+++ b/fw/fe310/eos/soc/i2c.c
@@ -11,22 +11,28 @@
 
 int eos_i2c_init(uint8_t wakeup_cause) {
     eos_i2c_speed(EOS_I2C_SPEED);
-    // eos_i2c_start();
+    eos_i2c_enable();
 
     return EOS_OK;
 }
 
-void eos_i2c_start(void) {
+void eos_i2c_enable(void) {
     I2C0_REGB(I2C_CONTROL)  |=  I2C_CONTROL_EN;
+
     GPIO_REG(GPIO_IOF_SEL)  &= ~IOF0_I2C0_MASK;
     GPIO_REG(GPIO_IOF_EN)   |=  IOF0_I2C0_MASK;
 }
 
-void eos_i2c_stop(void) {
+void eos_i2c_disable(void) {
     GPIO_REG(GPIO_IOF_EN)   &= ~IOF0_I2C0_MASK;
+
     I2C0_REGB(I2C_CONTROL)  &= ~I2C_CONTROL_EN;
 }
 
+int eos_i2c_enabled(void) {
+    return !!(GPIO_REG(GPIO_IOF_EN) & IOF0_I2C0_MASK);
+}
+
 void eos_i2c_speed(uint32_t baud_rate) {
     unsigned long clock_rate = PRCI_get_cpu_freq();
     uint16_t prescaler = (clock_rate / (baud_rate * 5)) - 1;
diff --git a/fw/fe310/eos/soc/i2c.h b/fw/fe310/eos/soc/i2c.h
index 20d3dc7..5032988 100644
--- a/fw/fe310/eos/soc/i2c.h
+++ b/fw/fe310/eos/soc/i2c.h
@@ -3,9 +3,9 @@
 #define EOS_I2C_SPEED       100000
 
 int eos_i2c_init(uint8_t wakeup_cause);
-int eos_i2c_run(uint8_t wakeup_cause);
-void eos_i2c_start(void);
-void eos_i2c_stop(void);
+void eos_i2c_enable(void);
+void eos_i2c_disable(void);
+int eos_i2c_enabled(void);
 void eos_i2c_speed(uint32_t baud_rate);
 int eos_i2c_read8(uint8_t addr, uint8_t reg, uint8_t *buffer, uint16_t len);
 int eos_i2c_read16(uint8_t addr, uint16_t reg, uint8_t *buffer, uint16_t len);
diff --git a/fw/fe310/eos/soc/i2s.c b/fw/fe310/eos/soc/i2s.c
index 9cc9d9c..5e5eaa7 100644
--- a/fw/fe310/eos/soc/i2s.c
+++ b/fw/fe310/eos/soc/i2s.c
@@ -25,41 +25,20 @@
 
 #define EOS_ABUF_IDX_MASK(IDX, SIZE)  ((IDX) & ((SIZE) - 1))
 
-EOSABuf i2s_mic_buf;
-EOSABuf i2s_spk_buf;
+EOSABuf _eos_i2s_mic_buf;
+EOSABuf _eos_i2s_spk_buf;
+uint32_t _eos_i2s_fmt = 0;
+uint32_t _eos_i2s_mic_wm = 0;
+uint32_t _eos_i2s_spk_wm = 0;
+uint32_t _eos_i2s_mic_evt_enable = 0;
+uint32_t _eos_i2s_spk_evt_enable = 0;
 
-static eos_i2s_handler_t i2s_mic_handler = NULL;
 static eos_i2s_handler_t i2s_spk_handler = NULL;
+static eos_i2s_handler_t i2s_mic_handler = NULL;
 static uint32_t i2s_clk_period;
 static uint8_t i2s_mic_volume = 0;      /* 0 - 8 */
 static uint8_t i2s_spk_volume = 16;     /* 0 - 16 */
 
-uint32_t _eos_i2s_drvr[] = {
-    0,                      /* I2S_MIC_BUF  */
-    0,                      /* I2S_SPK_BUF  */
-    EOS_I2S_FMT_PCM16,      /* I2S_FMT      */
-    EOS_I2S_MODE_STEREO,    /* I2S_MODE     */
-    0,                      /* I2S_MIC_WM   */
-    0,                      /* I2S_SPK_WM   */
-    0,                      /* I2S_MIC_EVT  */
-    0,                      /* I2S_SPK_EVT  */
-    0,                      /* I2S_MIC_CMP2 */
-    0,                      /* I2S_MIC_CMP3 */
-    0,                      /* I2S_SAMPLE */
-};
-
-#define I2S_MIC_BUF     0
-#define I2S_SPK_BUF     1
-#define I2S_FMT         2
-#define I2S_MODE        3
-#define I2S_MIC_WM      4
-#define I2S_SPK_WM      5
-#define I2S_MIC_EVT     6
-#define I2S_SPK_EVT     7
-#define I2S_MIC_CMP2    8
-#define I2S_MIC_CMP3    9
-#define I2S_SAMPLE      10
-
 static void _abuf_init(EOSABuf *buf, uint8_t *array, uint16_t size) {
     buf->idx_r = 0;
     buf->idx_w = 0;
@@ -105,6 +84,7 @@ static int _abuf_pop16(EOSABuf *buf, uint16_t *sample) {
     }
 }
 
+
 static void _abuf_flush(EOSABuf *buf) {
     buf->idx_r = 0;
     buf->idx_w = 0;
@@ -117,63 +97,42 @@ static uint16_t _abuf_len(EOSABuf *buf) {
 static void i2s_handle_evt(unsigned char type, unsigned char *buffer, uint16_t len) {
     switch(type & ~EOS_EVT_MASK) {
         case EOS_I2S_ETYPE_MIC:
-            if (i2s_mic_handler) {
-                i2s_mic_handler(type);
-                clear_csr(mstatus, MSTATUS_MIE);
-                _eos_i2s_drvr[I2S_MIC_EVT] = 1;
-                set_csr(mstatus, MSTATUS_MIE);
-            }
+            if (i2s_mic_handler) i2s_mic_handler(type);
+            clear_csr(mstatus, MSTATUS_MIE);
+            _eos_i2s_mic_evt_enable = 1;
+            set_csr(mstatus, MSTATUS_MIE);
             break;
-
         case EOS_I2S_ETYPE_SPK:
-            if (i2s_spk_handler) {
-                i2s_spk_handler(type);
-                clear_csr(mstatus, MSTATUS_MIE);
-                _eos_i2s_drvr[I2S_SPK_EVT] = 1;
-                set_csr(mstatus, MSTATUS_MIE);
-            }
+            if (i2s_spk_handler) i2s_spk_handler(type);
+            clear_csr(mstatus, MSTATUS_MIE);
+            _eos_i2s_spk_evt_enable = 1;
+            set_csr(mstatus, MSTATUS_MIE);
             break;
-
         default:
             eos_evtq_bad_handler(type, buffer, len);
             break;
     }
 }
 
-#define PLIC_PRIORITY     0x0C000000
-
-static void i2s_cmp_set(void) {
-    int c = 7;    /* interrupt will trigger c i2s clocks before spk ws */
-    int spk_ws_offset = i2s_spk_volume - 16 + i2s_mic_volume;
-    volatile  uint32_t *p = (uint32_t *)PLIC_PRIORITY+I2S_IRQ_SD_ID;
-
-    /* interrupt trigger - will start with left channel */
-    if (spk_ws_offset - c < 0) {
-        I2S_REG_WS_SPK(PWM_CMP3) = i2s_clk_period * (64 + spk_ws_offset - c);
-    } else {
-        I2S_REG_WS_SPK(PWM_CMP3) = i2s_clk_period * (spk_ws_offset - c);
-    }
-
-    /* disable interrupt for this cycle */
-    *p = 0;
+static void _mic_vol_set(uint8_t vol) {
+    I2S_REG_WS_MIC(PWM_CMP2) = i2s_clk_period * (vol + 1);
+    I2S_REG_WS_MIC(PWM_CMP3) = I2S_REG_WS_MIC(PWM_CMP2) + i2s_clk_period * 16;
+}
 
-    /* empty buffers */
-    // i2s_mic_buf.idx_r = i2s_mic_buf.idx_w;
-    // i2s_spk_buf.idx_w = i2s_spk_buf.idx_r;
+static void _spk_vol_set(uint8_t vol) {
+    int spk_cmp = vol + i2s_mic_volume - 16;
 
-    /* adjust spk ws relative to mic ws */
-    if (spk_ws_offset <= 0) {
-        spk_ws_offset += 32;
+    if (spk_cmp <= 0) {
+        I2S_REG_WS_SPK(PWM_CMP1) = i2s_clk_period * (32 + spk_cmp);
+        I2S_REG_WS_SPK(PWM_CMP2) = i2s_clk_period * (64 + spk_cmp);
+        I2S_REG_WS_SPK(PWM_CMP3) = i2s_clk_period * 33;
         GPIO_REG(GPIO_OUTPUT_XOR) &= ~(1 << I2S_PIN_WS_SPK);
     } else {
-        GPIO_REG(GPIO_OUTPUT_XOR) |=  (1 << I2S_PIN_WS_SPK);
+        I2S_REG_WS_SPK(PWM_CMP1) = i2s_clk_period * spk_cmp;
+        I2S_REG_WS_SPK(PWM_CMP2) = i2s_clk_period * (32 + spk_cmp);
+        I2S_REG_WS_SPK(PWM_CMP3) = i2s_clk_period * (33 + spk_cmp);
+        GPIO_REG(GPIO_OUTPUT_XOR) |= (1 << I2S_PIN_WS_SPK);
     }
-    I2S_REG_WS_SPK(PWM_CMP1) = i2s_clk_period * spk_ws_offset;
-    I2S_REG_WS_SPK(PWM_CMP2) = i2s_clk_period * (32 + spk_ws_offset);
-
-    /* mic cmp2 relative to interrupt trigger */
-    _eos_i2s_drvr[I2S_MIC_CMP2] = (17 + c - i2s_spk_volume) * i2s_clk_period;   /* (17 + c - i2s_spk_volume) == (1 + i2s_mic_volume) - (spk_ws_offset - c) */
-    _eos_i2s_drvr[I2S_MIC_CMP3] = 16 * i2s_clk_period;
 }
 
 extern void _eos_i2s_start_pwm(void);
@@ -181,10 +140,6 @@ extern void _eos_i2s_start_pwm(void);
 int eos_i2s_init(uint8_t wakeup_cause) {
     eos_evtq_set_handler(EOS_EVT_I2S, i2s_handle_evt);
 
-    I2S_REG_CK(PWM_CFG)         = 0;
-    I2S_REG_WS_MIC(PWM_CFG)     = 0;
-    I2S_REG_WS_SPK(PWM_CFG)     = 0;
-
     eos_i2s_init_mux();
 
     GPIO_REG(GPIO_OUTPUT_VAL)   |=  (1 << I2S_PIN_CK_SW);
@@ -218,7 +173,7 @@ void eos_i2s_init_mux(void) {
     GPIO_REG(GPIO_OUTPUT_EN)    &= ~(1 << I2S_PIN_SD_OUT);
 }
 
-void eos_i2s_start(uint32_t sample_rate) {
+void eos_i2s_start(uint32_t sample_rate, unsigned char fmt) {
     i2s_clk_period = ((PRCI_get_cpu_freq() / (sample_rate * 64)) & ~I2S_PWM_SCALE_CK_MASK) + 1;
 
     GPIO_REG(GPIO_INPUT_EN)     |=  (1 << I2S_PIN_SD_IN);
@@ -234,33 +189,23 @@ void eos_i2s_start(uint32_t sample_rate) {
 
     I2S_REG_WS_MIC(PWM_CMP0)    = i2s_clk_period * 64 - 1;
     I2S_REG_WS_MIC(PWM_CMP1)    = i2s_clk_period * 32;
+    _mic_vol_set(i2s_mic_volume);
 
     I2S_REG_WS_SPK(PWM_CMP0)    = i2s_clk_period * 64 - 1;
-    i2s_cmp_set();
+    _spk_vol_set(i2s_spk_volume);
 
     I2S_REG_CK(PWM_COUNT)       = 0;
     I2S_REG_WS_MIC(PWM_COUNT)   = 0;
     I2S_REG_WS_SPK(PWM_COUNT)   = i2s_clk_period / 2;
 
-    if (i2s_mic_buf.array && i2s_mic_buf.size) {
-        _eos_i2s_drvr[I2S_MIC_BUF] = (uint32_t)&i2s_mic_buf;
-        if (_eos_i2s_drvr[I2S_MIC_WM] == 0) {
-            _eos_i2s_drvr[I2S_MIC_WM] = i2s_mic_buf.size / 2;
-        }
-    }
-    if (i2s_spk_buf.array && i2s_spk_buf.size) {
-        _eos_i2s_drvr[I2S_SPK_BUF] = (uint32_t)&i2s_spk_buf;
-        if (_eos_i2s_drvr[I2S_SPK_WM] == 0) {
-            _eos_i2s_drvr[I2S_SPK_WM] = i2s_spk_buf.size / 2;
-        }
-    }
-    if (i2s_mic_handler) _eos_i2s_drvr[I2S_MIC_EVT] = 1;
-    if (i2s_spk_handler) _eos_i2s_drvr[I2S_SPK_EVT] = 1;
+    _eos_i2s_fmt = fmt;
+    _eos_i2s_mic_evt_enable = 1;
+    _eos_i2s_spk_evt_enable = 1;
 
-    eos_intr_set_priority(I2S_IRQ_SD_ID, IRQ_PRIORITY_I2S_SD);
     eos_intr_set_priority(I2S_IRQ_WS_ID, IRQ_PRIORITY_I2S_WS);
-    eos_intr_enable(I2S_IRQ_SD_ID);
+    eos_intr_set_priority(I2S_IRQ_SD_ID, 0);
     eos_intr_enable(I2S_IRQ_WS_ID);
+    eos_intr_enable(I2S_IRQ_SD_ID);
 
     _eos_i2s_start_pwm();
     /*
@@ -269,13 +214,9 @@ void eos_i2s_start(uint32_t sample_rate) {
     I2S_REG_WS_SPK(PWM_CFG)     = PWM_CFG_ENALWAYS | PWM_CFG_ZEROCMP | PWM_CFG_CMP1GANG;
     */
 
-    GPIO_REG(GPIO_OUTPUT_VAL)   |=  (1 << I2S_PIN_WS_MIC);
-    GPIO_REG(GPIO_INPUT_EN)     &= ~(1 << I2S_PIN_WS_MIC);
-    GPIO_REG(GPIO_OUTPUT_EN)    |=  (1 << I2S_PIN_WS_MIC);
-
-    GPIO_REG(GPIO_OUTPUT_VAL)   |=  (1 << I2S_PIN_CK_SR);
-    GPIO_REG(GPIO_IOF_SEL)      |=  I2S_PIN_PWM;
-    GPIO_REG(GPIO_IOF_EN)       |=  I2S_PIN_PWM;
+    GPIO_REG(GPIO_OUTPUT_VAL)   |= (1 << I2S_PIN_CK_SR);
+    GPIO_REG(GPIO_IOF_SEL)      |= I2S_PIN_PWM;
+    GPIO_REG(GPIO_IOF_EN)       |= I2S_PIN_PWM;
 }
 
 void eos_i2s_stop(void) {
@@ -286,14 +227,10 @@ void eos_i2s_stop(void) {
     I2S_REG_WS_MIC(PWM_COUNT)   = 0;
     I2S_REG_WS_SPK(PWM_COUNT)   = 0;
 
-    _eos_i2s_drvr[I2S_MIC_BUF]  = 0;
-    _eos_i2s_drvr[I2S_MIC_EVT]  = 0;
-    _eos_i2s_drvr[I2S_MIC_WM]   = 0;
-
-    _eos_i2s_drvr[I2S_SPK_BUF]  = 0;
-    _eos_i2s_drvr[I2S_SPK_EVT]  = 0;
-    _eos_i2s_drvr[I2S_SPK_WM]   = 0;
-
+    _eos_i2s_mic_evt_enable = 0;
+    _eos_i2s_spk_evt_enable = 0;
+    eos_intr_set_priority(I2S_IRQ_WS_ID, 0);
+    eos_intr_set_priority(I2S_IRQ_SD_ID, 0);
     eos_intr_disable(I2S_IRQ_WS_ID);
     eos_intr_disable(I2S_IRQ_SD_ID);
 
@@ -302,26 +239,15 @@ void eos_i2s_stop(void) {
 
     GPIO_REG(GPIO_OUTPUT_XOR)   &= ~(1 << I2S_PIN_WS_SPK);
     GPIO_REG(GPIO_IOF_EN)       &= ~I2S_PIN_PWM;
-
-    eos_i2s_mic_set_wm(0);
-    eos_i2s_spk_set_wm(0);
 }
 
 int eos_i2s_running(void) {
-    return !!(GPIO_REG(GPIO_IOF_EN) & (1 << I2S_PIN_CK));
-}
-
-void eos_i2s_set_fmt(unsigned char fmt) {
-    _eos_i2s_drvr[I2S_FMT] = fmt;
-}
-
-void eos_i2s_set_mode(unsigned char mode) {
-    _eos_i2s_drvr[I2S_MODE] = mode;
+    return !!(GPIO_REG(GPIO_IOF_EN) & I2S_PIN_PWM);
 }
 
 void eos_i2s_mic_init(uint8_t *mic_arr, uint16_t mic_arr_size) {
     clear_csr(mstatus, MSTATUS_MIE);
-    _abuf_init(&i2s_mic_buf, mic_arr, mic_arr_size);
+    _abuf_init(&_eos_i2s_mic_buf, mic_arr, mic_arr_size);
     set_csr(mstatus, MSTATUS_MIE);
 }
 
@@ -333,14 +259,14 @@ void eos_i2s_mic_set_handler(eos_i2s_handler_t wm_handler) {
 
 void eos_i2s_mic_set_wm(uint16_t wm) {
     clear_csr(mstatus, MSTATUS_MIE);
-    _eos_i2s_drvr[I2S_MIC_WM] = wm;
+    _eos_i2s_mic_wm = wm;
     set_csr(mstatus, MSTATUS_MIE);
 
 }
 
 uint16_t eos_i2s_mic_len(void) {
     clear_csr(mstatus, MSTATUS_MIE);
-    uint16_t ret = _abuf_len(&i2s_mic_buf);
+    uint16_t ret = _abuf_len(&_eos_i2s_mic_buf);
     set_csr(mstatus, MSTATUS_MIE);
     return ret;
 }
@@ -350,37 +276,31 @@ uint16_t eos_i2s_mic_read(uint8_t *sample, uint16_t ssize) {
     uint16_t _ssize = 0;
 
     clear_csr(mstatus, MSTATUS_MIE);
-    _ssize = MIN(ssize, _abuf_len(&i2s_mic_buf));
+    _ssize = MIN(ssize, _abuf_len(&_eos_i2s_mic_buf));
     set_csr(mstatus, MSTATUS_MIE);
 
     for (i=0; i<_ssize; i++) {
-        sample[i] = i2s_mic_buf.array[EOS_ABUF_IDX_MASK(i2s_mic_buf.idx_r + i, i2s_mic_buf.size)];
+        sample[i] = _eos_i2s_mic_buf.array[EOS_ABUF_IDX_MASK(_eos_i2s_mic_buf.idx_r + i, _eos_i2s_mic_buf.size)];
     }
 
     clear_csr(mstatus, MSTATUS_MIE);
-    i2s_mic_buf.idx_r += _ssize;
+    _eos_i2s_mic_buf.idx_r += _ssize;
     set_csr(mstatus, MSTATUS_MIE);
 
     return _ssize;
 }
 
 int eos_i2s_mic_pop8(uint8_t *sample) {
-    int ret;
-
     clear_csr(mstatus, MSTATUS_MIE);
-    ret = _abuf_pop8(&i2s_mic_buf, sample);
+    int ret = _abuf_pop8(&_eos_i2s_mic_buf, sample);
     set_csr(mstatus, MSTATUS_MIE);
-
     return ret;
 }
 
 int eos_i2s_mic_pop16(uint16_t *sample) {
-    int ret;
-
     clear_csr(mstatus, MSTATUS_MIE);
-    ret = _abuf_pop16(&i2s_mic_buf, sample);
+    int ret = _abuf_pop16(&_eos_i2s_mic_buf, sample);
     set_csr(mstatus, MSTATUS_MIE);
-
     return ret;
 }
 
@@ -394,13 +314,14 @@ void eos_i2s_mic_vol_set(int vol) {
     i2s_mic_volume = vol;
 
     clear_csr(mstatus, MSTATUS_MIE);
-    i2s_cmp_set();
+    _mic_vol_set(vol);
+    _spk_vol_set(i2s_spk_volume);
     set_csr(mstatus, MSTATUS_MIE);
 }
 
 void eos_i2s_spk_init(uint8_t *spk_arr, uint16_t spk_arr_size) {
     clear_csr(mstatus, MSTATUS_MIE);
-    _abuf_init(&i2s_spk_buf, spk_arr, spk_arr_size);
+    _abuf_init(&_eos_i2s_spk_buf, spk_arr, spk_arr_size);
     set_csr(mstatus, MSTATUS_MIE);
 }
 
@@ -412,13 +333,13 @@ void eos_i2s_spk_set_handler(eos_i2s_handler_t wm_handler) {
 
 void eos_i2s_spk_set_wm(uint16_t wm) {
     clear_csr(mstatus, MSTATUS_MIE);
-    _eos_i2s_drvr[I2S_SPK_WM] = wm;
+    _eos_i2s_spk_wm = wm;
     set_csr(mstatus, MSTATUS_MIE);
 }
 
 uint16_t eos_i2s_spk_len(void) {
     clear_csr(mstatus, MSTATUS_MIE);
-    uint16_t ret = _abuf_len(&i2s_spk_buf);
+    uint16_t ret = _abuf_len(&_eos_i2s_spk_buf);
     set_csr(mstatus, MSTATUS_MIE);
     return ret;
 }
@@ -428,37 +349,31 @@ uint16_t eos_i2s_spk_write(uint8_t *sample, uint16_t ssize) {
     uint16_t _ssize = 0;
 
     clear_csr(mstatus, MSTATUS_MIE);
-    _ssize = MIN(ssize, i2s_spk_buf.size - _abuf_len(&i2s_spk_buf));
+    _ssize = MIN(ssize, _eos_i2s_spk_buf.size - _abuf_len(&_eos_i2s_spk_buf));
     set_csr(mstatus, MSTATUS_MIE);
 
     for (i=0; i<_ssize; i++) {
-        i2s_spk_buf.array[EOS_ABUF_IDX_MASK(i2s_spk_buf.idx_w + i, i2s_spk_buf.size)] = sample[i];
+        _eos_i2s_spk_buf.array[EOS_ABUF_IDX_MASK(_eos_i2s_spk_buf.idx_w + i, _eos_i2s_spk_buf.size)] = sample[i];
     }
 
     clear_csr(mstatus, MSTATUS_MIE);
-    i2s_spk_buf.idx_w += _ssize;
+    _eos_i2s_spk_buf.idx_w += _ssize;
     set_csr(mstatus, MSTATUS_MIE);
 
     return _ssize;
 }
 
 int eos_i2s_spk_push8(uint8_t sample) {
-    int ret;
-
     clear_csr(mstatus, MSTATUS_MIE);
-    ret = _abuf_push8(&i2s_spk_buf, sample);
+    int ret = _abuf_push8(&_eos_i2s_spk_buf, sample);
     set_csr(mstatus, MSTATUS_MIE);
-
     return ret;
 }
 
 int eos_i2s_spk_push16(uint16_t sample) {
-    int ret;
-
     clear_csr(mstatus, MSTATUS_MIE);
-    ret = _abuf_push16(&i2s_spk_buf, sample);
+    int ret = _abuf_push16(&_eos_i2s_spk_buf, sample);
     set_csr(mstatus, MSTATUS_MIE);
-
     return ret;
 }
 
@@ -472,6 +387,6 @@ void eos_i2s_spk_vol_set(int vol) {
     i2s_spk_volume = vol;
 
     clear_csr(mstatus, MSTATUS_MIE);
-    i2s_cmp_set();
+    _spk_vol_set(vol);
     set_csr(mstatus, MSTATUS_MIE);
 }
diff --git a/fw/fe310/eos/soc/i2s.h b/fw/fe310/eos/soc/i2s.h
index 81b4ade..f53e183 100644
--- a/fw/fe310/eos/soc/i2s.h
+++ b/fw/fe310/eos/soc/i2s.h
@@ -13,11 +13,9 @@ typedef void (*eos_i2s_handler_t) (unsigned char);
 
 int eos_i2s_init(uint8_t wakeup_cause);
 void eos_i2s_init_mux(void);
-void eos_i2s_start(uint32_t sample_rate);
+void eos_i2s_start(uint32_t sample_rate, unsigned char fmt);
 void eos_i2s_stop(void);
 int eos_i2s_running(void);
-void eos_i2s_set_fmt(unsigned char fmt);
-void eos_i2s_set_mode(unsigned char mode);
 void eos_i2s_mic_init(uint8_t *mic_arr, uint16_t mic_arr_size);
 void eos_i2s_mic_set_handler(eos_i2s_handler_t wm_handler);
 void eos_i2s_mic_set_wm(uint16_t wm);
diff --git a/fw/fe310/eos/soc/interrupt.h b/fw/fe310/eos/soc/interrupt.h
index a239934..c6252b5 100644
--- a/fw/fe310/eos/soc/interrupt.h
+++ b/fw/fe310/eos/soc/interrupt.h
@@ -1,6 +1,6 @@
 #include <stdint.h>
 
-#include "irq_def.h"
+#include "../irq_def.h"
 
 typedef void (*eos_intr_handler_t) (void);
 
@@ -10,4 +10,4 @@ void eos_intr_set_handler(uint8_t int_num, eos_intr_handler_t handler);
 void eos_intr_set_priority(uint8_t int_num, uint8_t priority);
 void eos_intr_enable(uint8_t int_num);
 void eos_intr_disable(uint8_t int_num);
-void eos_intr_mask(uint8_t priority);
\ No newline at end of file
+void eos_intr_mask(uint8_t priority);
diff --git a/fw/fe310/eos/soc/net.c b/fw/fe310/eos/soc/net.c
deleted file mode 100644
index 33b71c2..0000000
--- a/fw/fe310/eos/soc/net.c
+++ /dev/null
@@ -1,602 +0,0 @@
-#include <stdlib.h>
-#include <stdint.h>
-
-#include "encoding.h"
-#include "platform.h"
-
-#include "eos.h"
-#include "msgq.h"
-#include "interrupt.h"
-#include "event.h"
-#include "timer.h"
-#include "pwr.h"
-
-#include "board.h"
-
-#include "spi.h"
-#include "spi_priv.h"
-#include "spi_dev.h"
-
-#include "net.h"
-
-#define NET_SIZE_HDR            3
-#define NET_STATE_FLAG_RUN      0x01
-#define NET_STATE_FLAG_INIT     0x02
-#define NET_STATE_FLAG_XCHG     0x04
-#define NET_STATE_FLAG_ONEW     0x10
-#define NET_STATE_FLAG_SYNC     0x20
-#define NET_STATE_FLAG_RTS      0x40
-#define NET_STATE_FLAG_CTS      0x80
-
-#define MIN(X, Y)               (((X) < (Y)) ? (X) : (Y))
-#define MAX(X, Y)               (((X) > (Y)) ? (X) : (Y))
-
-static EOSBufQ net_buf_q;
-static unsigned char *net_bufq_array[EOS_NET_SIZE_BUFQ];
-static unsigned char net_bufq_buffer[EOS_NET_SIZE_BUFQ][EOS_NET_SIZE_BUF];
-
-static EOSMsgQ net_send_q;
-static EOSMsgItem net_sndq_array[EOS_NET_SIZE_BUFQ];
-
-static volatile uint8_t net_state_flags = 0;
-static unsigned char net_state_type = 0;
-static uint32_t net_state_len_tx = 0;
-static uint32_t net_state_len_rx = 0;
-unsigned char *net_state_buf = NULL;
-
-static uint8_t net_state_next_cnt = 0;
-static unsigned char *net_state_next_buf = NULL;
-
-static eos_evt_handler_t net_handler[EOS_NET_MAX_MTYPE];
-static uint16_t net_wrapper_acq[EOS_EVT_MAX_EVT];
-static uint16_t net_flags_acq[EOS_EVT_MAX_EVT];
-
-static int net_xchg_sleep(void) {
-    int i;
-    int rv = EOS_OK;
-    volatile uint32_t x = 0;
-    net_state_flags &= ~NET_STATE_FLAG_CTS;
-
-    SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD;
-
-    SPI1_REG(SPI_REG_TXFIFO) = 0xFF;
-    while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY);
-    if (x & 0xFF) rv = EOS_ERR_BUSY;
-
-    for (i=0; i<7; i++) {
-        while (SPI1_REG(SPI_REG_TXFIFO) & SPI_TXFIFO_FULL);
-        SPI1_REG(SPI_REG_TXFIFO) = 0;
-        while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY);
-    }
-
-    SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
-
-    return rv;
-}
-
-static void net_xchg_wake(void) {
-    int i;
-    volatile uint32_t x = 0;
-    net_state_flags &= ~NET_STATE_FLAG_CTS;
-
-    SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD;
-
-    for (i=0; i<8; i++) {
-        while (SPI1_REG(SPI_REG_TXFIFO) & SPI_TXFIFO_FULL);
-        SPI1_REG(SPI_REG_TXFIFO) = 0;
-        while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY);
-    }
-
-    SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
-}
-
-static void net_xchg_reset(void) {
-    volatile uint32_t x = 0;
-    net_state_flags &= ~NET_STATE_FLAG_CTS;
-
-    SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD;
-
-    SPI1_REG(SPI_REG_TXFIFO) = 0;
-    while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY);
-
-    SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
-}
-
-static void net_xchg_start(unsigned char type, unsigned char *buffer, uint16_t len) {
-    net_state_flags &= ~NET_STATE_FLAG_CTS;
-    net_state_flags |= (NET_STATE_FLAG_INIT | NET_STATE_FLAG_XCHG);
-
-    if (net_state_next_cnt && (net_state_next_buf == NULL)) type |= EOS_NET_MTYPE_FLAG_ONEW;
-    if (type & EOS_NET_MTYPE_FLAG_ONEW) net_state_flags |= NET_STATE_FLAG_ONEW;
-
-    net_state_type = type;
-    net_state_len_tx = len;
-    net_state_len_rx = 0;
-    net_state_buf = buffer;
-
-    SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD;
-    SPI1_REG(SPI_REG_TXFIFO) = type;
-    SPI1_REG(SPI_REG_TXFIFO) = (len >> 8) & 0xFF;
-    SPI1_REG(SPI_REG_TXFIFO) = (len & 0xFF);
-    SPI1_REG(SPI_REG_RXCTRL) = SPI_RXWM(2);
-    SPI1_REG(SPI_REG_IE) = SPI_IP_RXWM;
-}
-
-static int net_xchg_next(unsigned char *_buffer) {
-    unsigned char type;
-    unsigned char *buffer = NULL;
-    uint16_t len;
-    int ret = _buffer ? 1 : 0;
-
-    eos_msgq_pop(&net_send_q, &type, &buffer, &len);
-    if (type) {
-        net_xchg_start(type, buffer, len);
-    } else if (net_state_flags & NET_STATE_FLAG_RTS) {
-        if (_buffer) {
-            buffer = _buffer;
-            ret = 0;
-        } else {
-            buffer = eos_bufq_pop(&net_buf_q);
-        }
-        if (buffer) net_xchg_start(0, buffer, 0);
-    }
-
-    return ret;
-}
-
-static void net_handle_xchg(void) {
-    volatile uint32_t r1, r2, r3;
-    uint32_t len;
-
-    if (net_state_flags & NET_STATE_FLAG_INIT) {
-        net_state_flags &= ~NET_STATE_FLAG_INIT;
-
-        r1 = SPI1_REG(SPI_REG_RXFIFO);
-        r2 = SPI1_REG(SPI_REG_RXFIFO);
-        r3 = SPI1_REG(SPI_REG_RXFIFO);
-
-        if (net_state_flags & NET_STATE_FLAG_ONEW) {
-            r1 = 0;
-            r2 = 0;
-            r3 = 0;
-        }
-
-        net_state_type    = (r1 & 0xFF);
-        net_state_len_rx  = (r2 & 0xFF) << 8;
-        net_state_len_rx |= (r3 & 0xFF);
-        len = MAX(net_state_len_tx, net_state_len_rx);
-
-        if (len > EOS_NET_MTU) {
-            net_state_flags &= ~NET_STATE_FLAG_XCHG;
-            SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
-            SPI1_REG(SPI_REG_IE) = 0x0;
-            return;
-        }
-
-        // esp32 dma workaraund
-        if (len < 8 - NET_SIZE_HDR) {
-            len = 8 - NET_SIZE_HDR;
-        } else if ((len + NET_SIZE_HDR) % 4 != 0) {
-            len = ((len + NET_SIZE_HDR)/4 + 1) * 4 - NET_SIZE_HDR;
-        }
-
-        _eos_spi_xchg_init(net_state_buf, len, 0);
-        SPI1_REG(SPI_REG_TXCTRL) = SPI_TXWM(SPI_SIZE_WM);
-        SPI1_REG(SPI_REG_IE) = SPI_IP_TXWM;
-        return;
-    }
-
-    eos_spi_handle_xchg();
-    if (SPI1_REG(SPI_REG_CSMODE) == SPI_CSMODE_AUTO) {  // exchange done
-        if (!(net_state_flags & NET_STATE_FLAG_SYNC)) {
-            if (net_state_type) {
-                int r = eos_evtq_push_isr(EOS_EVT_NET | net_state_type, net_state_buf, net_state_len_rx);
-                if (r) eos_bufq_push(&net_buf_q, net_state_buf);
-            } else if (((net_state_flags & NET_STATE_FLAG_ONEW) || net_state_next_cnt) && (net_state_next_buf == NULL)) {
-                net_state_next_buf = net_state_buf;
-            } else {
-                eos_bufq_push(&net_buf_q, net_state_buf);
-            }
-        }
-        net_state_flags &= ~(NET_STATE_FLAG_ONEW | NET_STATE_FLAG_XCHG);
-    }
-}
-
-static void net_handle_cts(void) {
-    GPIO_REG(GPIO_RISE_IP) = (1 << NET_PIN_CTS);
-    net_state_flags |= NET_STATE_FLAG_CTS;
-
-    if (net_state_flags & NET_STATE_FLAG_RUN) {
-        net_xchg_next(NULL);
-    }
-}
-
-static void net_handle_rts(void) {
-    uint32_t rts_offset = (1 << NET_PIN_RTS);
-
-    if (GPIO_REG(GPIO_RISE_IP) & rts_offset) {
-        GPIO_REG(GPIO_RISE_IP) = rts_offset;
-        net_state_flags |= NET_STATE_FLAG_RTS;
-        if ((net_state_flags & NET_STATE_FLAG_RUN) && (net_state_flags & NET_STATE_FLAG_CTS)) {
-            net_xchg_reset();
-        }
-    } else if (GPIO_REG(GPIO_FALL_IP) & rts_offset) {
-        GPIO_REG(GPIO_FALL_IP) = rts_offset;
-        net_state_flags &= ~NET_STATE_FLAG_RTS;
-    }
-}
-
-static void net_handle_evt(unsigned char type, unsigned char *buffer, uint16_t len) {
-    unsigned char idx = (type & ~EOS_EVT_MASK) - 1;
-
-    if (idx < EOS_NET_MAX_MTYPE) {
-        net_handler[idx](type, buffer, len);
-    } else {
-        eos_net_bad_handler(type, buffer, len);
-    }
-}
-
-static int net_acquire(unsigned char reserved) {
-    int ret = 0;
-
-    if (reserved) {
-        while (!ret) {
-            clear_csr(mstatus, MSTATUS_MIE);
-            if (net_state_next_buf) {
-                ret = 1;
-                net_state_next_cnt--;
-            } else {
-                asm volatile ("wfi");
-            }
-            set_csr(mstatus, MSTATUS_MIE);
-        }
-    } else {
-        clear_csr(mstatus, MSTATUS_MIE);
-        if (net_state_next_buf == NULL) net_state_next_buf = eos_bufq_pop(&net_buf_q);
-        ret = (net_state_next_buf != NULL);
-        if (!ret) net_state_next_cnt++;
-        set_csr(mstatus, MSTATUS_MIE);
-    }
-    return ret;
-}
-
-static void evt_handler_wrapper(unsigned char type, unsigned char *buffer, uint16_t len, unsigned char idx, uint16_t flag) {
-    int ok;
-
-    ok = net_acquire(net_wrapper_acq[idx] & flag);
-    if (ok) {
-        eos_evtq_get_handler(type)(type, buffer, len);
-        eos_net_release();
-        net_wrapper_acq[idx] &= ~flag;
-    } else {
-        net_wrapper_acq[idx] |= flag;
-        eos_evtq_push(type, buffer, len);
-    }
-}
-
-static void evt_handler(unsigned char type, unsigned char *buffer, uint16_t len) {
-    unsigned char idx = (type & EOS_EVT_MASK) >> 4;
-
-    if (idx && (idx <= EOS_EVT_MAX_EVT)) {
-        uint16_t flag = (uint16_t)1 << (type & ~EOS_EVT_MASK);
-
-        idx--;
-        if (flag & net_flags_acq[idx]) {
-            evt_handler_wrapper(type, buffer, len, idx, flag);
-        } else {
-            eos_evtq_get_handler(type)(type, buffer, len);
-        }
-    } else {
-        eos_evtq_bad_handler(type, buffer, len);
-    }
-}
-
-static void net_pause(void) {
-    net_state_flags &= ~NET_STATE_FLAG_RUN;
-}
-
-static void net_resume(void) {
-    net_state_flags |= NET_STATE_FLAG_RUN;
-    if (net_state_flags & NET_STATE_FLAG_CTS) {
-        net_xchg_next(NULL);
-    }
-}
-
-static void net_start(void) {
-    eos_intr_set_handler(INT_SPI1_BASE, net_handle_xchg);
-    SPI1_REG(SPI_REG_SCKDIV) = eos_spi_div(EOS_SPI_DEV_NET);
-    SPI1_REG(SPI_REG_CSID) = eos_spi_csid(EOS_SPI_DEV_NET);
-}
-
-static void net_stop(void) {
-    eos_intr_set_handler(INT_SPI1_BASE, NULL);
-}
-
-int eos_net_init(uint8_t wakeup_cause) {
-    int i;
-
-    eos_msgq_init(&net_send_q, net_sndq_array, EOS_NET_SIZE_BUFQ);
-    eos_bufq_init(&net_buf_q, net_bufq_array, EOS_NET_SIZE_BUFQ);
-    for (i=0; i<EOS_NET_SIZE_BUFQ; i++) {
-        eos_bufq_push(&net_buf_q, net_bufq_buffer[i]);
-    }
-
-    for (i=0; i<EOS_NET_MAX_MTYPE; i++) {
-        net_handler[i] = eos_net_bad_handler;
-    }
-    eos_evtq_set_handler(0, evt_handler);
-    eos_evtq_set_handler(EOS_EVT_NET, net_handle_evt);
-
-    GPIO_REG(GPIO_INPUT_EN)     |=  (1 << NET_PIN_CTS);
-    GPIO_REG(GPIO_OUTPUT_EN)    &= ~(1 << NET_PIN_CTS);
-
-    GPIO_REG(GPIO_RISE_IE)      |=  (1 << NET_PIN_CTS);
-    eos_intr_set(INT_GPIO_BASE + NET_PIN_CTS, IRQ_PRIORITY_NET_CTS, net_handle_cts);
-
-    GPIO_REG(GPIO_INPUT_EN)     |=  (1 << NET_PIN_RTS);
-    GPIO_REG(GPIO_OUTPUT_EN)    &= ~(1 << NET_PIN_RTS);
-
-    GPIO_REG(GPIO_RISE_IE)      |=  (1 << NET_PIN_RTS);
-    GPIO_REG(GPIO_FALL_IE)      |=  (1 << NET_PIN_RTS);
-    eos_intr_set(INT_GPIO_BASE + NET_PIN_RTS, IRQ_PRIORITY_NET_RTS, net_handle_rts);
-
-    /* set initial state */
-    clear_csr(mstatus, MSTATUS_MIE);
-    if (GPIO_REG(GPIO_INPUT_VAL) & (1 << NET_PIN_CTS)) net_state_flags |= NET_STATE_FLAG_CTS;
-    if (GPIO_REG(GPIO_INPUT_VAL) & (1 << NET_PIN_RTS)) net_state_flags |= NET_STATE_FLAG_RTS;
-    set_csr(mstatus, MSTATUS_MIE);
-
-    return EOS_OK;
-}
-
-int eos_net_run(uint8_t wakeup_cause) {
-    net_start();
-
-    clear_csr(mstatus, MSTATUS_MIE);
-    if (wakeup_cause != EOS_PWR_WAKE_RST) {
-        if (wakeup_cause != EOS_PWR_WAKE_BTN) {
-            net_xchg_wake();
-        }
-        if (!(net_state_flags & NET_STATE_FLAG_CTS)) {
-            while (!(GPIO_REG(GPIO_RISE_IP) & (1 << NET_PIN_CTS))) {
-                asm volatile ("wfi");
-            }
-            GPIO_REG(GPIO_RISE_IP) = (1 << NET_PIN_CTS);
-        }
-        net_xchg_reset();
-    }
-    net_resume();
-    set_csr(mstatus, MSTATUS_MIE);
-
-    return EOS_OK;
-}
-
-void eos_net_start(void) {
-    net_start();
-
-    clear_csr(mstatus, MSTATUS_MIE);
-    net_resume();
-    set_csr(mstatus, MSTATUS_MIE);
-}
-
-void eos_net_stop(void) {
-    uint8_t done = 0;
-
-    clear_csr(mstatus, MSTATUS_MIE);
-    if (net_state_flags & NET_STATE_FLAG_RUN) {
-        net_state_flags &= ~NET_STATE_FLAG_RUN;
-        done = !(net_state_flags & NET_STATE_FLAG_XCHG);
-    } else {
-        done = 1;
-    }
-    set_csr(mstatus, MSTATUS_MIE);
-
-    while (!done) {
-        clear_csr(mstatus, MSTATUS_MIE);
-        done = !(net_state_flags & NET_STATE_FLAG_XCHG);
-        if (!done) asm volatile ("wfi");
-        set_csr(mstatus, MSTATUS_MIE);
-    }
-    net_stop();
-}
-
-int eos_net_sleep(uint32_t timeout) {
-    volatile uint64_t *mtime = (uint64_t *) (CLINT_CTRL_ADDR + CLINT_MTIME);
-    uint64_t then_ms = timeout + *mtime * 1000 / EOS_TIMER_RTC_FREQ;
-    uint8_t done = 0;
-    int rv = EOS_OK;
-
-    clear_csr(mstatus, MSTATUS_MIE);
-    if (!(net_state_flags & NET_STATE_FLAG_RUN)) rv = EOS_ERR;
-    set_csr(mstatus, MSTATUS_MIE);
-
-    if (rv) return rv;
-
-    do {
-        if (*mtime * 1000 / EOS_TIMER_RTC_FREQ > then_ms) return EOS_ERR_TIMEOUT;
-        clear_csr(mstatus, MSTATUS_MIE);
-        eos_evtq_flush_isr();
-        done = (eos_msgq_len(&net_send_q) == 0);
-        done = done && (!(net_state_flags & NET_STATE_FLAG_RTS) && (net_state_flags & NET_STATE_FLAG_CTS));
-        if (done) done = (net_xchg_sleep() == EOS_OK);
-        if (!done) {
-            asm volatile ("wfi");
-            set_csr(mstatus, MSTATUS_MIE);
-        }
-    } while (!done);
-
-    while (!(GPIO_REG(GPIO_RISE_IP) & (1 << NET_PIN_CTS))) {
-        if (*mtime * 1000 / EOS_TIMER_RTC_FREQ > then_ms) {
-            rv = EOS_ERR_TIMEOUT;
-            break;
-        }
-        asm volatile ("wfi");
-    }
-
-    if (!rv) {
-        GPIO_REG(GPIO_RISE_IP) = (1 << NET_PIN_CTS);
-        net_state_flags &= ~NET_STATE_FLAG_RUN;
-    }
-
-    set_csr(mstatus, MSTATUS_MIE);
-
-    return rv;
-}
-
-void eos_net_bad_handler(unsigned char type, unsigned char *buffer, uint16_t len) {
-    eos_evtq_bad_handler(type, buffer, len);
-    if (buffer) eos_net_free(buffer, 0);
-}
-
-void eos_net_set_handler(unsigned char mtype, eos_evt_handler_t handler) {
-    if (handler == NULL) handler = eos_net_bad_handler;
-    if (mtype && (mtype <= EOS_NET_MAX_MTYPE)) net_handler[mtype - 1] = handler;
-}
-
-void eos_net_acquire_for_evt(unsigned char type, char acq) {
-    unsigned char idx = (type & EOS_EVT_MASK) >> 4;
-    uint16_t flag = type & ~EOS_EVT_MASK ? (uint16_t)1 << (type & ~EOS_EVT_MASK) : 0xFFFF;
-
-    if (idx && (idx <= EOS_EVT_MAX_EVT)) {
-        idx--;
-        net_flags_acq[idx] &= ~flag;
-        if (acq) net_flags_acq[idx] |= flag;
-    }
-}
-
-void eos_net_acquire(void) {
-    unsigned char acq = net_acquire(0);
-    if (!acq) net_acquire(1);
-}
-
-void eos_net_release(void) {
-    clear_csr(mstatus, MSTATUS_MIE);
-    if (!net_state_next_cnt && net_state_next_buf) {
-        eos_bufq_push(&net_buf_q, net_state_next_buf);
-        net_state_next_buf = NULL;
-    }
-    set_csr(mstatus, MSTATUS_MIE);
-}
-
-unsigned char *eos_net_alloc(void) {
-    unsigned char *ret = NULL;
-
-    while (!ret) {
-        clear_csr(mstatus, MSTATUS_MIE);
-        if (net_state_next_buf) {
-            ret = net_state_next_buf;
-            net_state_next_buf = NULL;
-        } else {
-            asm volatile ("wfi");
-        }
-        set_csr(mstatus, MSTATUS_MIE);
-    }
-
-    return ret;
-}
-
-void eos_net_free(unsigned char *buffer, unsigned char more) {
-    uint8_t do_release = 1;
-
-    clear_csr(mstatus, MSTATUS_MIE);
-    if ((more || net_state_next_cnt) && (net_state_next_buf == NULL)) {
-        net_state_next_buf = buffer;
-    } else {
-        if ((net_state_flags & NET_STATE_FLAG_RUN) && (net_state_flags & NET_STATE_FLAG_CTS)) {
-            do_release = net_xchg_next(buffer);
-        }
-        if (do_release) {
-            eos_bufq_push(&net_buf_q, buffer);
-        }
-    }
-    set_csr(mstatus, MSTATUS_MIE);
-}
-
-static int net_xchg(unsigned char *type, unsigned char *buffer, uint16_t *len, unsigned char flags) {
-    int rv = EOS_OK;
-    int _sync = 0;
-    unsigned char _type = *type;
-    uint16_t _len = *len;
-    uint8_t spi_dev = EOS_SPI_DEV_NET;
-
-    if (flags & EOS_NET_FLAG_ONEW) _type |= EOS_NET_MTYPE_FLAG_ONEW;
-    if (flags & EOS_NET_FLAG_REPL) _type |= EOS_NET_MTYPE_FLAG_REPL;
-    if (flags & EOS_NET_FLAG_SYNC) _sync = 1;
-
-    clear_csr(mstatus, MSTATUS_MIE);
-    if ((flags & EOS_NET_FLAG_ONEW) && !(net_state_flags & NET_STATE_FLAG_RUN)) _sync = 1;
-
-    if (_sync && !(net_state_flags & NET_STATE_FLAG_RUN)) {
-        int _rv;
-
-        set_csr(mstatus, MSTATUS_MIE);
-        spi_dev = eos_spi_dev();
-        _rv = eos_spi_deselect();
-        if (_rv) return _rv;
-        clear_csr(mstatus, MSTATUS_MIE);
-    }
-
-    if (_sync) {
-        net_pause();
-        while (!(net_state_flags & NET_STATE_FLAG_CTS)) {
-            asm volatile ("wfi");
-            set_csr(mstatus, MSTATUS_MIE);
-            clear_csr(mstatus, MSTATUS_MIE);
-        }
-        if (flags & EOS_NET_FLAG_SYNC) {
-            net_state_flags |= NET_STATE_FLAG_SYNC;
-        }
-        net_xchg_start(_type, buffer, _len);
-        if (flags & EOS_NET_FLAG_SYNC) {
-            if (flags & EOS_NET_FLAG_REPL) {
-                while (!(net_state_flags & NET_STATE_FLAG_CTS)) {
-                    asm volatile ("wfi");
-                    set_csr(mstatus, MSTATUS_MIE);
-                    clear_csr(mstatus, MSTATUS_MIE);
-                }
-                net_xchg_start(0, buffer, 0);
-            }
-            while (net_state_flags & NET_STATE_FLAG_XCHG) {
-                asm volatile ("wfi");
-                set_csr(mstatus, MSTATUS_MIE);
-                clear_csr(mstatus, MSTATUS_MIE);
-            }
-            net_state_flags &= ~NET_STATE_FLAG_SYNC;
-            *type = net_state_type;
-            *len = net_state_len_rx;
-        }
-        net_resume();
-    } else {
-        if ((net_state_flags & NET_STATE_FLAG_RUN) && (net_state_flags & NET_STATE_FLAG_CTS)) {
-            net_xchg_start(_type, buffer, _len);
-        } else {
-            rv = eos_msgq_push(&net_send_q, _type, buffer, _len);
-            if (rv) eos_bufq_push(&net_buf_q, buffer);
-        }
-    }
-
-    set_csr(mstatus, MSTATUS_MIE);
-    if (spi_dev != EOS_SPI_DEV_NET) eos_spi_select(spi_dev);
-
-    return rv;
-}
-
-int eos_net_xchg(unsigned char *type, unsigned char *buffer, uint16_t *len) {
-    return net_xchg(type, buffer, len, (EOS_NET_FLAG_ONEW | EOS_NET_FLAG_SYNC | EOS_NET_FLAG_REPL));
-}
-
-int eos_net_send(unsigned char type, unsigned char *buffer, uint16_t len) {
-    return net_xchg(&type, buffer, &len, (EOS_NET_FLAG_ONEW | EOS_NET_FLAG_SYNC));
-}
-
-int eos_net_send_async(unsigned char type, unsigned char *buffer, uint16_t len, unsigned char more) {
-    return net_xchg(&type, buffer, &len, more ? EOS_NET_FLAG_ONEW : 0);
-}
-
-int _eos_net_send(unsigned char type, unsigned char *buffer, uint16_t len, unsigned char async, unsigned char more) {
-    if (async) {
-        eos_net_send_async(type, buffer, len, more);
-    } else {
-        eos_net_send(type, buffer, len);
-    }
-}
diff --git a/fw/fe310/eos/soc/net.h b/fw/fe310/eos/soc/net.h
deleted file mode 100644
index 79caf4b..0000000
--- a/fw/fe310/eos/soc/net.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#include <stdint.h>
-#include "event.h"
-
-/* common */
-#define EOS_NET_MTU                 1500
-#define EOS_NET_SIZE_BUF            EOS_NET_MTU
-
-#define EOS_NET_MTYPE_SOCK          1
-#define EOS_NET_MTYPE_RNG         	3
-#define EOS_NET_MTYPE_POWER         4
-
-#define EOS_NET_MTYPE_WIFI          5
-#define EOS_NET_MTYPE_CELL          6
-#define EOS_NET_MTYPE_SIP           7
-#define EOS_NET_MTYPE_APP           8
-
-#define EOS_NET_MAX_MTYPE           8
-
-#define EOS_NET_MTYPE_FLAG_ONEW     0x40
-#define EOS_NET_MTYPE_FLAG_REPL     0x80
-#define EOS_NET_MTYPE_FLAG_MASK     0xc0
-
-/* fe310 specific */
-#define EOS_NET_SIZE_BUFQ           2
-
-#define EOS_NET_FLAG_ONEW           0x1
-#define EOS_NET_FLAG_SYNC           0x2
-#define EOS_NET_FLAG_REPL           0x4
-
-int eos_net_init(uint8_t wakeup_cause);
-int eos_net_run(uint8_t wakeup_cause);
-void eos_net_start(void);
-void eos_net_stop(void);
-int eos_net_sleep(uint32_t timeout);
-
-void eos_net_bad_handler(unsigned char type, unsigned char *buffer, uint16_t len);
-void eos_net_set_handler(unsigned char type, eos_evt_handler_t handler);
-void eos_net_acquire_for_evt(unsigned char type, char acq);
-
-void eos_net_acquire(void);
-void eos_net_release(void);
-unsigned char *eos_net_alloc(void);
-void eos_net_free(unsigned char *buffer, unsigned char more);
-int eos_net_xchg(unsigned char *type, unsigned char *buffer, uint16_t *len);
-int eos_net_send(unsigned char type, unsigned char *buffer, uint16_t len);
-int eos_net_send_async(unsigned char type, unsigned char *buffer, uint16_t len, unsigned char more);
-int _eos_net_send(unsigned char type, unsigned char *buffer, uint16_t len, unsigned char async, unsigned char more);
diff --git a/fw/fe310/eos/soc/pwr.c b/fw/fe310/eos/soc/pwr.c
index 802e593..a2adfd4 100644
--- a/fw/fe310/eos/soc/pwr.c
+++ b/fw/fe310/eos/soc/pwr.c
@@ -5,22 +5,14 @@
 #include "platform.h"
 
 #include "eos.h"
-#include "event.h"
 #include "timer.h"
-#include "spi.h"
-#include "spi_dev.h"
-#include "net.h"
-#include "lcd.h"
-#include "eve/eve.h"
+#include "dev/net.h"
 
 #include "pwr.h"
 
 #define PWR_RTC_SCALE   15
 #define PWR_RTC_SFREQ   (EOS_TIMER_RTC_FREQ >> PWR_RTC_SCALE)
 
-static eos_evt_handler_t evt_handler[EOS_PWR_MAX_MTYPE];
-static unsigned char power_btn_down;
-
 int eos_pwr_init(uint8_t wakeup_cause) {
     AON_REG(AON_PMUKEY) = 0x51F15E;
     AON_REG(AON_PMUIE) = 0x5;
@@ -44,13 +36,6 @@ uint8_t eos_pwr_reset_cause(void) {
 int eos_pwr_sleep(void) {
     int rv;
 
-    rv = eos_lcd_sleep();
-    if (rv) return rv;
-
-    eos_spi_select(EOS_SPI_DEV_EVE);
-    eve_pwr_sleep();
-    eos_spi_deselect();
-
     rv = eos_net_sleep(1000);
     if (rv) return rv;
 
@@ -83,51 +68,3 @@ void eos_pwr_wake_disable(void) {
     AON_REG(AON_PMUKEY) = 0x51F15E;
     AON_REG(AON_PMUIE) = pmuie;
 }
-
-static void pwr_handle_msg(unsigned char type, unsigned char *buffer, uint16_t len) {
-    unsigned char mtype;
-
-    if ((buffer == NULL) || (len < 1)) {
-        eos_net_bad_handler(type, buffer, len);
-        return;
-    }
-
-    mtype = buffer[0];
-    if ((mtype < EOS_PWR_MAX_MTYPE) && evt_handler[mtype]) {
-        evt_handler[mtype](mtype, buffer, len);
-    } else {
-        eos_net_bad_handler(type, buffer, len);
-    }
-}
-
-static void pwr_handle_btn(unsigned char type, unsigned char *buffer, uint16_t len) {
-    unsigned char level = buffer[1];
-
-    eos_net_free(buffer, 0);
-    if (!level) {
-        power_btn_down = 1;
-        return;
-    }
-    if (!power_btn_down) return;
-
-    eos_pwr_sleep();
-}
-
-void eos_pwr_netinit(void) {
-    int i;
-
-    for (i=0; i<EOS_PWR_MAX_MTYPE; i++) {
-        evt_handler[i] = NULL;
-    }
-    eos_net_set_handler(EOS_NET_MTYPE_POWER, pwr_handle_msg);
-    eos_pwr_set_handler(EOS_PWR_MTYPE_BUTTON, pwr_handle_btn);
-}
-
-void eos_pwr_set_handler(unsigned char mtype, eos_evt_handler_t handler) {
-    if (mtype < EOS_PWR_MAX_MTYPE) evt_handler[mtype] = handler;
-}
-
-eos_evt_handler_t eos_pwr_get_handler(unsigned char mtype) {
-    if (mtype < EOS_PWR_MAX_MTYPE) return evt_handler[mtype];
-    return NULL;
-}
diff --git a/fw/fe310/eos/soc/pwr.h b/fw/fe310/eos/soc/pwr.h
index 264436b..1a0d17a 100644
--- a/fw/fe310/eos/soc/pwr.h
+++ b/fw/fe310/eos/soc/pwr.h
@@ -1,9 +1,4 @@
 #include <stdint.h>
-#include "event.h"
-
-#define EOS_PWR_MTYPE_BUTTON    1
-
-#define EOS_PWR_MAX_MTYPE       2
 
 #define EOS_PWR_WAKE_RST        0
 #define EOS_PWR_WAKE_RTC        1
@@ -19,7 +14,3 @@ uint8_t eos_pwr_reset_cause(void);
 int eos_pwr_sleep(void);
 void eos_pwr_wake_at(uint32_t msec);
 void eos_pwr_wake_disable(void);
-
-void eos_pwr_netinit(void);
-void eos_pwr_set_handler(unsigned char mtype, eos_evt_handler_t handler);
-eos_evt_handler_t eos_pwr_get_handler(unsigned char mtype);
\ No newline at end of file
diff --git a/fw/fe310/eos/soc/spi.c b/fw/fe310/eos/soc/spi.c
index 05c9448..2c36109 100644
--- a/fw/fe310/eos/soc/spi.c
+++ b/fw/fe310/eos/soc/spi.c
@@ -21,6 +21,8 @@
 
 #define SPI_FLAG_XCHG           0x10
 
+#define SPI_CSID_NONE           1
+
 #define MIN(X, Y)               (((X) < (Y)) ? (X) : (Y))
 #define MAX(X, Y)               (((X) > (Y)) ? (X) : (Y))
 
@@ -52,19 +54,7 @@ int eos_spi_init(uint8_t wakeup_cause) {
         evt_handler[i] = eos_evtq_bad_handler;
     }
     eos_evtq_set_handler(EOS_EVT_SPI, spi_handle_evt);
-    eos_intr_set(INT_SPI1_BASE, IRQ_PRIORITY_SPI_XCHG, NULL);
-
-    GPIO_REG(GPIO_OUTPUT_VAL)   &= ~(1 << IOF_SPI1_SCK);
-    GPIO_REG(GPIO_OUTPUT_VAL)   |=  (1 << IOF_SPI1_MOSI);
-
-    GPIO_REG(GPIO_INPUT_EN)     &= ~(1 << IOF_SPI1_SCK);
-    GPIO_REG(GPIO_OUTPUT_EN)    |=  (1 << IOF_SPI1_SCK);
-
-    GPIO_REG(GPIO_INPUT_EN)     &= ~(1 << IOF_SPI1_MOSI);
-    GPIO_REG(GPIO_OUTPUT_EN)    |=  (1 << IOF_SPI1_MOSI);
-
-    GPIO_REG(GPIO_INPUT_EN)     |=  (1 << IOF_SPI1_MISO);
-    GPIO_REG(GPIO_OUTPUT_EN)    &= ~(1 << IOF_SPI1_MISO);
+    eos_intr_set_priority(INT_SPI1_BASE, IRQ_PRIORITY_SPI_XCHG);
 
     SPI1_REG(SPI_REG_SCKMODE) = SPI_MODE0;
     SPI1_REG(SPI_REG_FMT) = SPI_FMT_PROTO(SPI_PROTO_S) |
@@ -72,25 +62,34 @@ int eos_spi_init(uint8_t wakeup_cause) {
       SPI_FMT_DIR(SPI_DIR_RX) |
       SPI_FMT_LEN(8);
 
-    GPIO_REG(GPIO_IOF_SEL)      &= ~SPI_IOF_MASK;
-    GPIO_REG(GPIO_IOF_EN)       |=  SPI_IOF_MASK;
+    /* for spi 9bit protocol */
+    GPIO_REG(GPIO_OUTPUT_EN)    |=  (1 << IOF_SPI1_SCK);
+    GPIO_REG(GPIO_OUTPUT_EN)    |=  (1 << IOF_SPI1_MOSI);
+    GPIO_REG(GPIO_INPUT_EN)     |=  (1 << IOF_SPI1_MISO);
+
+    eos_spi_enable();
 
     // There is no way here to change the CS polarity.
     // SPI1_REG(SPI_REG_CSDEF) = 0xFFFF;
     return EOS_OK;
 }
 
-void eos_spi_start(uint16_t div, uint8_t csid, uint8_t cspin, unsigned char evt) {
+void eos_spi_configure(uint16_t div, int8_t csid, int8_t cspin, unsigned char evt) {
     spi_state_flags = 0;
     spi_evt = evt;
     SPI1_REG(SPI_REG_SCKDIV) = div;
-    SPI1_REG(SPI_REG_CSID) = csid;
-    if (csid != SPI_CSID_NONE) {
+    if (csid != -1) {
+        SPI1_REG(SPI_REG_CSID) = csid;
         SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
     } else {
         spi_cspin = cspin;
+        SPI1_REG(SPI_REG_CSID) = SPI_CSID_NONE;
         SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_OFF;
     }
+}
+
+void eos_spi_start(uint16_t div, int8_t csid, int8_t cspin, unsigned char evt) {
+    eos_spi_configure(div, csid, cspin, evt);
     eos_intr_set_handler(INT_SPI1_BASE, eos_spi_handle_xchg);
 }
 
@@ -100,6 +99,19 @@ void eos_spi_stop(void) {
     spi_evt = 0;
 }
 
+void eos_spi_enable(void) {
+    eos_intr_enable(INT_SPI1_BASE);
+
+    GPIO_REG(GPIO_IOF_SEL)      &= ~SPI_IOF_MASK;
+    GPIO_REG(GPIO_IOF_EN)       |=  SPI_IOF_MASK;
+}
+
+void eos_spi_disable(void) {
+    GPIO_REG(GPIO_IOF_EN)       &= ~SPI_IOF_MASK;
+
+    eos_intr_disable(INT_SPI1_BASE);
+}
+
 void eos_spi_set_handler(unsigned char evt, eos_evt_handler_t handler) {
     if (handler == NULL) handler = eos_evtq_bad_handler;
     if (evt && (evt <= EOS_SPI_MAX_EVT)) evt_handler[evt - 1] = handler;
diff --git a/fw/fe310/eos/soc/spi.h b/fw/fe310/eos/soc/spi.h
index a23a235..0c2de4b 100644
--- a/fw/fe310/eos/soc/spi.h
+++ b/fw/fe310/eos/soc/spi.h
@@ -1,5 +1,5 @@
 #include <stdint.h>
-#include "event.h"
+#include "../event.h"
 
 #define EOS_SPI_FLAG_TX         0x01
 #define EOS_SPI_FLAG_MORE       0x02
@@ -11,8 +11,12 @@
 #define EOS_SPI_MAX_EVT         2
 
 int eos_spi_init(uint8_t wakeup_cause);
-void eos_spi_start(uint16_t div, uint8_t csid, uint8_t cspin, unsigned char evt);
+void eos_spi_configure(uint16_t div, int8_t csid, int8_t cspin, unsigned char evt);
+void eos_spi_start(uint16_t div, int8_t csid, int8_t cspin, unsigned char evt);
 void eos_spi_stop(void);
+void eos_spi_enable(void);
+void eos_spi_disable(void);
+
 void eos_spi_set_handler(unsigned char evt, eos_evt_handler_t handler);
 
 void _eos_spi_xchg_init(unsigned char *buffer, uint16_t len, uint8_t flags);
diff --git a/fw/fe310/eos/soc/spi_cfg.h b/fw/fe310/eos/soc/spi_cfg.h
deleted file mode 100644
index 84ab8bb..0000000
--- a/fw/fe310/eos/soc/spi_cfg.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#include <stdint.h>
-
-#define EOS_SPI_MAX_DEV         4
-
-typedef struct {
-    uint16_t div;
-    uint8_t csid;
-    uint8_t cspin;
-    unsigned char evt;
-} SPIConfig;
-
-static const SPIConfig spi_cfg[EOS_SPI_MAX_DEV] = {
-    {   // DEV_NET
-        .div = SPI_DIV_NET,
-        .csid = SPI_CSID_NET,
-        .cspin = SPI_CSPIN_NET,
-        .evt = 0,   // Not SPI event
-    },
-    {   // DEV_EVE
-        .div = SPI_DIV_EVE,
-        .csid = SPI_CSID_EVE,
-        .cspin = SPI_CSPIN_EVE,
-        .evt = 0,
-    },
-    {   // DEV_SDC
-        .div = SPI_DIV_SDC,
-        .csid = SPI_CSID_SDC,
-        .cspin = SPI_CSPIN_SDC,
-        .evt = EOS_SPI_EVT_SDC,
-    },
-    {   // DEV_CAM
-        .div = SPI_DIV_CAM,
-        .csid = SPI_CSID_CAM,
-        .cspin = SPI_CSPIN_CAM,
-        .evt = EOS_SPI_EVT_CAM,
-    },
-};
diff --git a/fw/fe310/eos/soc/spi_dev.c b/fw/fe310/eos/soc/spi_dev.c
deleted file mode 100644
index c0c21b0..0000000
--- a/fw/fe310/eos/soc/spi_dev.c
+++ /dev/null
@@ -1,97 +0,0 @@
-#include <stdlib.h>
-#include <stdint.h>
-
-#include "encoding.h"
-#include "platform.h"
-
-#include "eos.h"
-#include "msgq.h"
-#include "interrupt.h"
-#include "event.h"
-
-#include "board.h"
-
-#include "net.h"
-#include "spi.h"
-#include "spi_priv.h"
-#include "spi_cfg.h"
-#include "spi_dev.h"
-
-static uint8_t spi_dev;
-static uint8_t spi_lock;
-static uint16_t spi_div[EOS_SPI_MAX_DEV];
-
-int eos_spi_dev_init(uint8_t wakeup_cause) {
-    int i;
-
-    for (i=0; i<EOS_SPI_MAX_DEV; i++) {
-        spi_div[i] = spi_cfg[i].div;
-        if (spi_cfg[i].cspin != SPI_CSPIN_NONE) {
-            GPIO_REG(GPIO_OUTPUT_VAL)   |=  (1 << spi_cfg[i].cspin);
-
-            GPIO_REG(GPIO_INPUT_EN)     &= ~(1 << spi_cfg[i].cspin);
-            GPIO_REG(GPIO_OUTPUT_EN)    |=  (1 << spi_cfg[i].cspin);
-        }
-    }
-
-    return EOS_OK;
-}
-
-int eos_spi_select(unsigned char dev) {
-    if (spi_lock) return EOS_ERR_BUSY;
-
-    if (spi_dev == EOS_SPI_DEV_NET) {
-        eos_net_stop();
-    } else {
-        eos_spi_stop();
-    }
-
-    spi_dev = dev;
-    if (dev == EOS_SPI_DEV_NET) {
-        eos_net_start();
-    } else {
-        eos_spi_start(spi_div[dev], spi_cfg[dev].csid, spi_cfg[dev].cspin, spi_cfg[dev].evt);
-    }
-
-    return EOS_OK;
-}
-
-int eos_spi_deselect(void) {
-    if (spi_lock) return EOS_ERR_BUSY;
-    if (spi_dev == EOS_SPI_DEV_NET) return EOS_ERR;
-
-    eos_spi_stop();
-
-    spi_dev = EOS_SPI_DEV_NET;
-    eos_net_start();
-
-    return EOS_OK;
-}
-
-uint8_t eos_spi_dev(void) {
-    return spi_dev;
-}
-
-uint16_t eos_spi_div(unsigned char dev) {
-    return spi_div[dev];
-}
-
-uint8_t eos_spi_csid(unsigned char dev) {
-    return spi_cfg[dev].csid;
-}
-
-uint8_t eos_spi_cspin(unsigned char dev) {
-    return spi_cfg[dev].cspin;
-}
-
-void eos_spi_lock(void) {
-    spi_lock = 1;
-}
-
-void eos_spi_unlock(void) {
-    spi_lock = 0;
-}
-
-void eos_spi_set_div(unsigned char dev, uint16_t div) {
-    spi_div[dev] = div;
-}
diff --git a/fw/fe310/eos/soc/spi_dev.h b/fw/fe310/eos/soc/spi_dev.h
deleted file mode 100644
index e801f7e..0000000
--- a/fw/fe310/eos/soc/spi_dev.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#include <stdint.h>
-
-#define EOS_SPI_DEV_NET         0
-#define EOS_SPI_DEV_EVE         1
-#define EOS_SPI_DEV_SDC         2
-#define EOS_SPI_DEV_CAM         3
-
-int eos_spi_dev_init(uint8_t wakeup_cause);
-int eos_spi_select(unsigned char dev);
-int eos_spi_deselect(void);
-
-uint8_t eos_spi_dev(void);
-uint16_t eos_spi_div(unsigned char dev);
-uint8_t eos_spi_csid(unsigned char dev);
-uint8_t eos_spi_cspin(unsigned char dev);
-
-void eos_spi_lock(void);
-void eos_spi_unlock(void);
-void eos_spi_set_div(unsigned char dev, uint16_t div);
diff --git a/fw/fe310/eos/soc/spi_priv.h b/fw/fe310/eos/soc/spi_priv.h
index 72c2dae..17081a3 100644
--- a/fw/fe310/eos/soc/spi_priv.h
+++ b/fw/fe310/eos/soc/spi_priv.h
@@ -1,8 +1,5 @@
 #include <stdint.h>
 
-#define SPI_CSID_NONE           1
-#define SPI_CSPIN_NONE          0xff
-
 /* DO NOT TOUCH THEESE */
 #define SPI_SIZE_CHUNK          4
 #define SPI_SIZE_WM             2
diff --git a/fw/fe310/eos/soc/trap_entry.S b/fw/fe310/eos/soc/trap_entry.S
index fb2b121..96024cb 100644
--- a/fw/fe310/eos/soc/trap_entry.S
+++ b/fw/fe310/eos/soc/trap_entry.S
@@ -25,18 +25,6 @@
 #define INT_PWM1_BASE     44
 #define INT_PWM2_BASE     48
 
-#define I2S_MIC_BUF     (0*4)
-#define I2S_SPK_BUF     (1*4)
-#define I2S_FMT         (2*4)
-#define I2S_MODE        (3*4)
-#define I2S_MIC_WM      (4*4)
-#define I2S_SPK_WM      (5*4)
-#define I2S_MIC_EVT     (6*4)
-#define I2S_SPK_EVT     (7*4)
-#define I2S_MIC_CMP2    (8*4)
-#define I2S_MIC_CMP3    (9*4)
-#define I2S_SAMPLE      (10*4)
-
 #include "board.h"
 #include "irq_def.h"
 #include "evt_def.h"
@@ -49,7 +37,7 @@
 
 .global eos_trap_entry
 eos_trap_entry:
-  addi sp, sp, -12*REGBYTES
+  addi sp, sp, -8*REGBYTES
   STORE x8, 0*REGBYTES(sp)
   STORE x9, 1*REGBYTES(sp)
   STORE x18, 2*REGBYTES(sp)
@@ -58,10 +46,6 @@ eos_trap_entry:
   STORE x21, 5*REGBYTES(sp)
   STORE x22, 6*REGBYTES(sp)
   STORE x23, 7*REGBYTES(sp)
-  STORE x24, 8*REGBYTES(sp)     # format:   0 - PCM16;  1 - ALAW
-  STORE x25, 9*REGBYTES(sp)     # mode:     0 - stereo; 1 - mono
-  STORE x26, 10*REGBYTES(sp)    # channel:  0 - left;   1 - right
-  STORE x27, 11*REGBYTES(sp)    # _eos_event_q addr
 
   csrr x8, mcause
   li x18, MCAUSE_EXT
@@ -100,68 +84,34 @@ evtq_push:
   jalr x0, x21
 
 i2s_handle_sd:
-  li x8, I2S_CTRL_ADDR_WS_SPK
-  lw x18, PWM_COUNT(x8)
-  lw x19, PWM_CMP3(x8)
-
   # exit if too early
-  bltu x18, x19, i2s_sd_exit
-
-  la x27, _eos_i2s_drvr
-
-  # move CMPs for next channel and store channel bit to x26
-  lw x20, I2S_MIC_CMP2(x27)
-  lw x21, I2S_MIC_CMP3(x27) # 16-bit period
-
-  add x23, x19, x20
-  add x24, x23, x21
-  slli x20, x21, 1      # 32-bit period
-  slli x21, x20, 1      # 64-bit period
-  bltu x24, x21, 0f
-  neg x21, x21
-  add x23, x23, x21
-  add x24, x24, x21
-0:
-  li x26, 0
-  bltu x23, x20, 0f
-  li x26, 1
-0:
-  bltu x19, x20, 0f
-  neg x20, x20
+  li x18, I2S_CTRL_ADDR_WS_SPK
+  lw x8, PWM_COUNT(x18)
+  lw x9, PWM_CMP3(x18)
+  bltu x8, x9, i2s_handle_sd_exit
+
+  # disable sd irq
   li x18, PLIC_PRIORITY
   sw x0, 4*I2S_IRQ_SD_ID(x18)
-0:
-  add x19, x19, x20
 
-  li x9, I2S_CTRL_ADDR_WS_MIC
-  sw x19, PWM_CMP3(x8)
-  sw x23, PWM_CMP2(x9)
-  sw x24, PWM_CMP3(x9)
-
-  lw x24, I2S_FMT(x27)
-  lw x25, I2S_MODE(x27)
+  la x9, _eos_i2s_fmt
+  lw x23, 0(x9)
 
 i2s_abuf_pop:
-  and x8, x25, x26
-  beqz x8, 0f
-
-  lw x8, I2S_SAMPLE(x27)
-  j i2s_sd_xchg
-0:
   # pop from spk buf -> x8
-  lw x9, I2S_SPK_BUF(x27)
-  beqz x9, i2s_sd_xchg
+  mv x8, x0
+  la x9, _eos_i2s_spk_buf
   lhu x18, I2S_ABUF_OFF_IDXR(x9)
   lhu x19, I2S_ABUF_OFF_IDXW(x9)
   lhu x20, I2S_ABUF_OFF_SIZE(x9)
 
-  beq x18, x19, 2f
+  beq x18, x19, i2s_handle_sd_xchg
 
   addi x20, x20, -1
   and x20, x20, x18
   lw x21, I2S_ABUF_OFF_ARRAY(x9)
   add x21, x21, x20
-  beqz x24, 0f
+  beqz x23, 0f
   lbu x8, 0(x21)
   addi x18, x18, 1
   j 1f
@@ -174,18 +124,20 @@ i2s_abuf_pop:
 1:
   sh x18, I2S_ABUF_OFF_IDXR(x9)
 
-2:
   li x21, 0xffff
   sub x18, x19, x18
   and x18, x18, x21
 
   # check for push to event queue
-  lw x9, I2S_SPK_WM(x27)
-  bgtu x18, x9, i2s_decode
+  la x9, _eos_i2s_spk_wm
+  lw x20, 0(x9)
+  beqz x20, i2s_decode
+  bgtu x18, x20, i2s_decode
 
-  lw x9, I2S_SPK_EVT(x27)
-  beqz x9, i2s_decode
-  sw x0, I2S_SPK_EVT(x27)
+  la x9, _eos_i2s_spk_evt_enable
+  lw x18, 0(x9)
+  beqz x18, i2s_decode
+  sw x0, 0(x9)
 
   # push to event queue
   jal x22, evtq_push
@@ -194,7 +146,7 @@ i2s_abuf_pop:
   sb x18, MSGQ_ITEM_OFF_TYPE(x21)
 
 i2s_decode:
-  beqz x24, 3f
+  beqz x23, i2s_handle_sd_xchg
   # aLaw decode -> x8
   xori x8, x8, 0x55
   andi x9, x8, 0x80
@@ -229,13 +181,10 @@ i2s_decode:
   slli x8, x8, 1
   ori x8, x8, 1
 2:
-  beqz x9, 3f
+  beqz x9, i2s_handle_sd_xchg
   mul x8, x8, x9
-3:
-  beqz x25, i2s_sd_xchg
-  sw x8, I2S_SAMPLE(x27)
 
-i2s_sd_xchg:
+i2s_handle_sd_xchg:
   # read/write shift reg: x8 -> sr -> x8
   li x18, GPIO_CTRL_ADDR
   li x19, (0x1 << I2S_PIN_SD_IN)
@@ -285,15 +234,17 @@ i2s_sd_xchg:
   xor x22, x22, x21
   sw x22, GPIO_OUTPUT_VAL(x18)
 
-  addi x23, x23, -1
-  bnez x23, 0b
-
   # idle
   li x9, I2S_IDLE_CYCLES
 1:
   addi x9, x9, -1
   bnez x9, 1b
 
+  addi x23, x23, -1
+  beqz x23, 2f
+  j 0b
+
+2:
   # 74HC595 ck low (I2S_PIN_CK_SR high)
   xor x22, x22, x21
   sw x22, GPIO_OUTPUT_VAL(x18)
@@ -305,8 +256,11 @@ i2s_sd_xchg:
   slli x8, x8, 16
   srai x8, x8, 16
 
+  la x9, _eos_i2s_fmt
+  lw x23, 0(x9)
+
 i2s_encode:
-  beqz x24, i2s_abuf_push
+  beqz x23, i2s_abuf_push
   # aLaw encode -> x8
   li x18, 0x800
   li x19, 7
@@ -338,12 +292,8 @@ i2s_encode:
   andi x8, x8, 0xff
 
 i2s_abuf_push:
-  # check channel
-  # bnez x26, i2s_sd_exit
-
   # push to mic buf
-  lw x9, I2S_MIC_BUF(x27)
-  beqz x9, i2s_sd_exit
+  la x9, _eos_i2s_mic_buf
   lhu x18, I2S_ABUF_OFF_IDXR(x9)
   lhu x19, I2S_ABUF_OFF_IDXW(x9)
   lhu x20, I2S_ABUF_OFF_SIZE(x9)
@@ -351,13 +301,13 @@ i2s_abuf_push:
 
   sub x18, x19, x18
   and x18, x18, x21
-  beq x18, x20, 2f
+  beq x18, x20, i2s_handle_sd_exit
 
   addi x20, x20, -1
   and x20, x20, x19
   lw x21, I2S_ABUF_OFF_ARRAY(x9)
   add x21, x21, x20
-  beqz x24, 0f
+  beqz x23, 0f
   sb x8, 0(x21)
   addi x19, x19, 1
   addi x18, x18, 1
@@ -371,22 +321,24 @@ i2s_abuf_push:
 1:
   sh x19, I2S_ABUF_OFF_IDXW(x9)
 
-2:
   # check for push to event queue
-  lw x9, I2S_MIC_WM(x27)
-  bltu x18, x9, i2s_sd_exit
+  la x9, _eos_i2s_mic_wm
+  lw x20, 0(x9)
+  beqz x20, i2s_handle_sd_exit
+  bltu x18, x20, i2s_handle_sd_exit
 
-  lw x9, I2S_MIC_EVT(x27)
-  beqz x9, i2s_sd_exit
-  sw x0, I2S_MIC_EVT(x27)
+  la x9, _eos_i2s_mic_evt_enable
+  lw x18, 0(x9)
+  beqz x18, i2s_handle_sd_exit
+  sw x0, 0(x9)
 
   # push to event queue
   jal x22, evtq_push
-  beqz x21, i2s_sd_exit
+  beqz x21, i2s_handle_sd_exit
   li x18, (EOS_EVT_I2S | EOS_I2S_ETYPE_MIC)
   sb x18, MSGQ_ITEM_OFF_TYPE(x21)
 
-i2s_sd_exit:
+i2s_handle_sd_exit:
   # complete
   li x18, I2S_IRQ_SD_ID
   li x19, PLIC_CLAIM
@@ -443,6 +395,16 @@ _eos_i2s_start_pwm:
 
   ret
 
+.global _eos_flash_set
+_eos_flash_set:
+  li a3, SPI0_CTRL_ADDR
+  sw x0, SPI_REG_FCTRL(a3)
+  sw a0, SPI_REG_SCKDIV(a3)
+  sw a1, SPI_REG_FFMT(a3)
+  li a0, 1
+  sw a0, SPI_REG_FCTRL(a3)
+  ret
+
 trap_exit_data:
   # Remain in M-mode after mret
   li x18, MSTATUS_MPP
@@ -456,11 +418,7 @@ trap_exit_data:
   LOAD x21, 5*REGBYTES(sp)
   LOAD x22, 6*REGBYTES(sp)
   LOAD x23, 7*REGBYTES(sp)
-  LOAD x24, 8*REGBYTES(sp)
-  LOAD x25, 9*REGBYTES(sp)
-  LOAD x26, 10*REGBYTES(sp)
-  LOAD x27, 11*REGBYTES(sp)
-  addi sp, sp, 12*REGBYTES
+  addi sp, sp, 8*REGBYTES
 
   mret
 
@@ -473,7 +431,7 @@ handle_intr:
   .align 4
 
 trap_entry_text:
-  addi sp, sp, -20*REGBYTES
+  addi sp, sp, -24*REGBYTES
 
   STORE x1, 0*REGBYTES(sp)
   STORE x2, 1*REGBYTES(sp)
@@ -490,10 +448,14 @@ trap_entry_text:
   STORE x15, 12*REGBYTES(sp)
   STORE x16, 13*REGBYTES(sp)
   STORE x17, 14*REGBYTES(sp)
-  STORE x28, 15*REGBYTES(sp)
-  STORE x29, 16*REGBYTES(sp)
-  STORE x30, 17*REGBYTES(sp)
-  STORE x31, 18*REGBYTES(sp)
+  STORE x24, 15*REGBYTES(sp)
+  STORE x25, 16*REGBYTES(sp)
+  STORE x26, 17*REGBYTES(sp)
+  STORE x27, 18*REGBYTES(sp)
+  STORE x28, 19*REGBYTES(sp)
+  STORE x29, 20*REGBYTES(sp)
+  STORE x30, 21*REGBYTES(sp)
+  STORE x31, 22*REGBYTES(sp)
 
   li x18, MCAUSE_TIMER
   beq x8, x18, handle_timer
@@ -511,6 +473,7 @@ handle_ext:
   call eos_intr_handle
   li x18, PLIC_CLAIM
   sw a0, 0(x18)
+  j trap_exit_text
 
 trap_exit_text:
   # Remain in M-mode after mret
@@ -532,23 +495,23 @@ trap_exit_text:
   LOAD x15, 12*REGBYTES(sp)
   LOAD x16, 13*REGBYTES(sp)
   LOAD x17, 14*REGBYTES(sp)
-  LOAD x28, 15*REGBYTES(sp)
-  LOAD x29, 16*REGBYTES(sp)
-  LOAD x30, 17*REGBYTES(sp)
-  LOAD x31, 18*REGBYTES(sp)
-
-  LOAD x8, 20*REGBYTES(sp)
-  LOAD x9, 21*REGBYTES(sp)
-  LOAD x18, 22*REGBYTES(sp)
-  LOAD x19, 23*REGBYTES(sp)
-  LOAD x20, 24*REGBYTES(sp)
-  LOAD x21, 25*REGBYTES(sp)
-  LOAD x22, 26*REGBYTES(sp)
-  LOAD x23, 27*REGBYTES(sp)
-  LOAD x24, 28*REGBYTES(sp)
-  LOAD x25, 29*REGBYTES(sp)
-  LOAD x26, 30*REGBYTES(sp)
-  LOAD x27, 31*REGBYTES(sp)
+  LOAD x24, 15*REGBYTES(sp)
+  LOAD x25, 16*REGBYTES(sp)
+  LOAD x26, 17*REGBYTES(sp)
+  LOAD x27, 18*REGBYTES(sp)
+  LOAD x28, 19*REGBYTES(sp)
+  LOAD x29, 20*REGBYTES(sp)
+  LOAD x30, 21*REGBYTES(sp)
+  LOAD x31, 22*REGBYTES(sp)
+
+  LOAD x8, 24*REGBYTES(sp)
+  LOAD x9, 25*REGBYTES(sp)
+  LOAD x18, 26*REGBYTES(sp)
+  LOAD x19, 27*REGBYTES(sp)
+  LOAD x20, 28*REGBYTES(sp)
+  LOAD x21, 29*REGBYTES(sp)
+  LOAD x22, 30*REGBYTES(sp)
+  LOAD x23, 31*REGBYTES(sp)
 
   addi sp, sp, 32*REGBYTES
   mret
diff --git a/fw/fe310/eos/soc/uart.c b/fw/fe310/eos/soc/uart.c
index 30f76d9..589832a 100644
--- a/fw/fe310/eos/soc/uart.c
+++ b/fw/fe310/eos/soc/uart.c
@@ -9,6 +9,7 @@
 #include "eos.h"
 #include "interrupt.h"
 #include "event.h"
+#include "i2s.h"
 
 #include "uart.h"
 
@@ -44,22 +45,30 @@ int eos_uart_init(uint8_t wakeup_cause) {
     eos_evtq_set_handler(EOS_EVT_UART, uart_handle_evt);
     eos_intr_set(INT_UART0_BASE, IRQ_PRIORITY_UART, uart_handle_intr);
 
-    UART0_REG(UART_REG_TXCTRL)  |=  UART_TXEN;
-    UART0_REG(UART_REG_RXCTRL)  |=  UART_RXEN;
-
     eos_uart_speed(EOS_UART_SPEED);
-    eos_uart_start();
+
+    eos_uart_enable();
 
     return EOS_OK;
 }
 
-void eos_uart_start(void) {
+void eos_uart_enable(void) {
+    UART0_REG(UART_REG_TXCTRL)  |=  UART_TXEN;
+    UART0_REG(UART_REG_RXCTRL)  |=  UART_RXEN;
+
     GPIO_REG(GPIO_IOF_SEL)      &= ~IOF0_UART0_MASK;
     GPIO_REG(GPIO_IOF_EN)       |=  IOF0_UART0_MASK;
 }
 
-void eos_uart_stop(void) {
+void eos_uart_disable(void) {
     GPIO_REG(GPIO_IOF_EN)       &= ~IOF0_UART0_MASK;
+
+    UART0_REG(UART_REG_TXCTRL)  &= ~UART_TXEN;
+    UART0_REG(UART_REG_RXCTRL)  &= ~UART_RXEN;
+}
+
+int eos_uart_enabled(void) {
+    return !!(GPIO_REG(GPIO_IOF_EN) & IOF0_UART0_MASK);
 }
 
 void eos_uart_speed(uint32_t baud_rate) {
@@ -90,8 +99,8 @@ void eos_uart_rxwm_clear(void) {
     UART0_REG(UART_REG_IE)      &= ~UART_IP_RXWM;
 }
 
-int eos_uart_putc(int c, char b) {
-    if (b) {
+int eos_uart_putc(int c, int block) {
+    if (block) {
         while (UART0_REG(UART_REG_TXFIFO) & 0x80000000);
         UART0_REG(UART_REG_TXFIFO) = c & 0xff;
     } else {
@@ -101,14 +110,14 @@ int eos_uart_putc(int c, char b) {
     return EOS_OK;
 }
 
-int eos_uart_getc(char b) {
+int eos_uart_getc(int block) {
     volatile uint32_t r;
 
-    if (b) {
+    if (block) {
         while ((r = UART0_REG(UART_REG_RXFIFO)) & 0x80000000);
     } else {
         r = UART0_REG(UART_REG_RXFIFO);
         if (r & 0x80000000) return EOS_ERR_EMPTY;
     }
     return r & 0xff;
-}
\ No newline at end of file
+}
diff --git a/fw/fe310/eos/soc/uart.h b/fw/fe310/eos/soc/uart.h
index 94999e6..caaf6c6 100644
--- a/fw/fe310/eos/soc/uart.h
+++ b/fw/fe310/eos/soc/uart.h
@@ -10,8 +10,9 @@
 typedef void (*eos_uart_handler_t) (unsigned char);
 
 int eos_uart_init(uint8_t wakeup_cause);
-void eos_uart_start(void);
-void eos_uart_stop(void);
+void eos_uart_enable(void);
+void eos_uart_disable(void);
+int eos_uart_enabled(void);
 void eos_uart_speed(uint32_t baud_rate);
 
 void eos_uart_set_handler(unsigned char type, eos_uart_handler_t handler);
@@ -20,5 +21,5 @@ void eos_uart_txwm_set(uint8_t wm);
 void eos_uart_txwm_clear(void);
 void eos_uart_rxwm_set(uint8_t wm);
 void eos_uart_rxwm_clear(void);
-int eos_uart_putc(int c, char b);
-int eos_uart_getc(char b);
\ No newline at end of file
+int eos_uart_putc(int c, int block);
+int eos_uart_getc(int block);
\ No newline at end of file