i2s driver fixed; added uart programming;

5 files changed, 52 insertions, 36 deletions

diff --git a/fw/fe310/eos/soc/i2s.c b/fw/fe310/eos/soc/i2s.c
index c5b52bf..8416ec1 100644
--- a/fw/fe310/eos/soc/i2s.c
+++ b/fw/fe310/eos/soc/i2s.c
@@ -108,7 +108,6 @@ static uint16_t _abuf_len(EOSABuf *buf) {
     return buf->idx_w - buf->idx_r;
 }
 
-__attribute__ ((section (".itim")))
 static void i2s_handle_evt(unsigned char type, unsigned char *buffer, uint16_t len) {
     switch(type & ~EOS_EVT_MASK) {
         case EOS_I2S_ETYPE_MIC:
@@ -298,7 +297,6 @@ void eos_i2s_mic_set_wm(uint16_t wm) {
     set_csr(mstatus, MSTATUS_MIE);
 }
 
-__attribute__ ((section (".itim")))
 uint16_t eos_i2s_mic_len(void) {
     uint16_t ret;
 
@@ -309,7 +307,6 @@ uint16_t eos_i2s_mic_len(void) {
     return ret;
 }
 
-__attribute__ ((section (".itim")))
 uint16_t eos_i2s_mic_read(uint8_t *sample, uint16_t ssize) {
     uint16_t i;
     uint16_t _ssize = 0;
@@ -381,7 +378,6 @@ void eos_i2s_spk_set_wm(uint16_t wm) {
     set_csr(mstatus, MSTATUS_MIE);
 }
 
-__attribute__ ((section (".itim")))
 uint16_t eos_i2s_spk_len(void) {
     uint16_t ret;
 
@@ -392,7 +388,6 @@ uint16_t eos_i2s_spk_len(void) {
     return ret;
 }
 
-__attribute__ ((section (".itim")))
 uint16_t eos_i2s_spk_write(uint8_t *sample, uint16_t ssize) {
     uint16_t i;
     uint16_t _ssize = 0;
diff --git a/fw/fe310/eos/soc/pwr.c b/fw/fe310/eos/soc/pwr.c
index a2adfd4..970db8b 100644
--- a/fw/fe310/eos/soc/pwr.c
+++ b/fw/fe310/eos/soc/pwr.c
@@ -6,6 +6,7 @@
 
 #include "eos.h"
 #include "timer.h"
+#include "dev/flash.h"
 #include "dev/net.h"
 
 #include "pwr.h"
@@ -39,6 +40,8 @@ int eos_pwr_sleep(void) {
     rv = eos_net_sleep(1000);
     if (rv) return rv;
 
+    eos_flash_norm();
+
     AON_REG(AON_PMUKEY) = 0x51F15E;
     AON_REG(AON_PMUSLEEP) = 1;
 
diff --git a/fw/fe310/eos/soc/spi.c b/fw/fe310/eos/soc/spi.c
index b722c7e..351c9c8 100644
--- a/fw/fe310/eos/soc/spi.c
+++ b/fw/fe310/eos/soc/spi.c
@@ -57,10 +57,11 @@ int eos_spi_init(uint8_t wakeup_cause) {
     eos_intr_set_priority(INT_SPI1_BASE, IRQ_PRIORITY_SPI_XCHG);
 
     SPI1_REG(SPI_REG_SCKMODE) = SPI_MODE0;
-    SPI1_REG(SPI_REG_FMT) = SPI_FMT_PROTO(SPI_PROTO_S) |
-      SPI_FMT_ENDIAN(SPI_ENDIAN_MSB) |
-      SPI_FMT_DIR(SPI_DIR_RX) |
-      SPI_FMT_LEN(8);
+    SPI1_REG(SPI_REG_FMT) = \
+        SPI_FMT_PROTO(SPI_PROTO_S)      |
+        SPI_FMT_ENDIAN(SPI_ENDIAN_MSB)  |
+        SPI_FMT_DIR(SPI_DIR_RX)         |
+        SPI_FMT_LEN(8);
 
     /* for spi 9bit protocol */
     GPIO_REG(GPIO_OUTPUT_EN)    |=  (1 << IOF_SPI1_SCK);
@@ -69,8 +70,6 @@ int eos_spi_init(uint8_t wakeup_cause) {
 
     eos_spi_enable();
 
-    // There is no way here to change the CS polarity.
-    // SPI1_REG(SPI_REG_CSDEF) = 0xFFFF;
     return EOS_OK;
 }
 
@@ -117,7 +116,6 @@ void eos_spi_set_handler(unsigned char evt, eos_evt_handler_t handler) {
     if (evt && (evt <= EOS_SPI_MAX_EVT)) evt_handler[evt - 1] = handler;
 }
 
-__attribute__ ((section (".itim")))
 void _eos_spi_xchg_init(unsigned char *buffer, uint16_t len, uint8_t flags) {
     spi_state_flags &= 0xF0;
     spi_state_flags |= (SPI_FLAG_XCHG | flags);
@@ -127,7 +125,7 @@ void _eos_spi_xchg_init(unsigned char *buffer, uint16_t len, uint8_t flags) {
     spi_state_idx_rx = 0;
 }
 
-static void spi_xchg_finish(void) {
+static void spi_wait4xchg(void) {
     uint8_t done = 0;
 
     while (!done) {
@@ -140,7 +138,7 @@ static void spi_xchg_finish(void) {
 }
 
 void eos_spi_xchg(unsigned char *buffer, uint16_t len, uint8_t flags) {
-    if (spi_in_xchg) spi_xchg_finish();
+    if (spi_in_xchg) spi_wait4xchg();
 
     spi_in_xchg = 1;
     _eos_spi_xchg_init(buffer, len, flags);
@@ -150,7 +148,6 @@ void eos_spi_xchg(unsigned char *buffer, uint16_t len, uint8_t flags) {
     SPI1_REG(SPI_REG_IE) = SPI_IP_TXWM;
 }
 
-__attribute__ ((section (".itim")))
 void eos_spi_handle_xchg(void) {
     int i;
     uint16_t sz_chunk = MIN(spi_state_len - spi_state_idx_tx, SPI_SIZE_CHUNK);
@@ -162,15 +159,21 @@ void eos_spi_handle_xchg(void) {
     }
     spi_state_idx_tx += i;
 
-    for (i=0; i<spi_state_idx_tx - spi_state_idx_rx; i++) {
-        volatile uint32_t x = SPI1_REG(SPI_REG_RXFIFO);
-        if (x & SPI_RXFIFO_EMPTY) break;
-        spi_state_buf[spi_state_idx_rx+i] = x & 0xFF;
+    if (!(spi_state_flags & EOS_SPI_FLAG_TX)) {
+        for (i=0; i<spi_state_idx_tx - spi_state_idx_rx; i++) {
+            volatile uint32_t x = SPI1_REG(SPI_REG_RXFIFO);
+            if (x & SPI_RXFIFO_EMPTY) break;
+            spi_state_buf[spi_state_idx_rx+i] = x & 0xFF;
+        }
+        spi_state_idx_rx += i;
     }
-    spi_state_idx_rx += i;
 
     if (spi_state_idx_tx == spi_state_len) {
-        if ((spi_state_idx_rx == spi_state_len) || (spi_state_flags & EOS_SPI_FLAG_TX)) {
+        if ((spi_state_flags & EOS_SPI_FLAG_TX) || (spi_state_idx_rx == spi_state_len)) {
+            if ((spi_state_flags & EOS_SPI_FLAG_TX) && (SPI1_REG(SPI_REG_TXCTRL) != SPI_TXWM(1))) {
+                SPI1_REG(SPI_REG_TXCTRL) = SPI_TXWM(1);
+                return;
+            }
             spi_state_flags &= ~SPI_FLAG_XCHG;
             if (!(spi_state_flags & EOS_SPI_FLAG_MORE)) eos_spi_cs_clear();
             SPI1_REG(SPI_REG_IE) = 0x0;
@@ -182,7 +185,6 @@ void eos_spi_handle_xchg(void) {
     }
 }
 
-__attribute__ ((section (".itim")))
 void eos_spi_cs_set(void) {
 	/* cs low */
     if (SPI1_REG(SPI_REG_CSMODE) == SPI_CSMODE_OFF) {
@@ -192,7 +194,6 @@ void eos_spi_cs_set(void) {
     }
 }
 
-__attribute__ ((section (".itim")))
 void eos_spi_cs_clear(void) {
 	/* cs high */
     if (SPI1_REG(SPI_REG_CSMODE) == SPI_CSMODE_OFF) {
@@ -355,12 +356,21 @@ uint32_t eos_spi_xchg32(uint32_t data, uint8_t flags) {
 }
 
 void eos_spi_flush(void) {
-    volatile uint32_t x = 0;
+    if (spi_in_xchg) {
+        spi_wait4xchg();
+    } else {
+        SPI1_REG(SPI_REG_TXCTRL) = SPI_TXWM(1);
+        while (!(SPI1_REG(SPI_REG_IP) & SPI_IP_TXWM));
+        while (!(SPI1_REG(SPI_REG_RXFIFO) & SPI_RXFIFO_EMPTY));
+    }
 
-    if (spi_in_xchg) spi_xchg_finish();
+    /*
+    volatile uint32_t x = 0;
 
-    SPI1_REG(SPI_REG_TXCTRL) = SPI_TXWM(1);
     while (!x) {
-        if (SPI1_REG(SPI_REG_IP) & SPI_IP_TXWM) x = SPI1_REG(SPI_REG_RXFIFO) & SPI_RXFIFO_EMPTY;
+        if (SPI1_REG(SPI_REG_IP) & SPI_IP_TXWM) {
+            x = SPI1_REG(SPI_REG_RXFIFO) & SPI_RXFIFO_EMPTY;
+        }
     }
+    */
 }
diff --git a/fw/fe310/eos/soc/timer.c b/fw/fe310/eos/soc/timer.c
index 91861a3..8d74c6d 100644
--- a/fw/fe310/eos/soc/timer.c
+++ b/fw/fe310/eos/soc/timer.c
@@ -26,12 +26,13 @@ static void timer_handle_evt(unsigned char type, unsigned char *buffer, uint16_t
 }
 
 void _eos_timer_handle(void) {
-    int i;
     volatile uint64_t *mtime = (uint64_t *) (CLINT_CTRL_ADDR + CLINT_MTIME);
     uint64_t *mtimecmp = (uint64_t *) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
-    uint64_t now = *mtime;
+    uint64_t now;
     uint64_t next = 0;
+    int i;
 
+    now = *mtime;
     for (i=0; i<=EOS_TIMER_MAX_ETYPE; i++) {
         if (timer_next[i] && (timer_next[i] <= now)) {
             timer_next[i] = 0;
@@ -48,8 +49,8 @@ void _eos_timer_handle(void) {
 }
 
 int eos_timer_init(uint8_t wakeup_cause) {
-    int i;
     uint64_t *mtimecmp = (uint64_t *) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
+    int i;
 
     clear_csr(mie, MIP_MTIP);
     *mtimecmp = 0;
@@ -89,11 +90,11 @@ uint32_t eos_timer_get(unsigned char evt) {
 }
 
 void eos_timer_set(unsigned char evt, uint32_t msec) {
-    int i;
     volatile uint64_t *mtime = (uint64_t *) (CLINT_CTRL_ADDR + CLINT_MTIME);
     uint64_t *mtimecmp = (uint64_t *) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
     uint64_t tick = *mtime + msec * (uint64_t)EOS_TIMER_RTC_FREQ / 1000;
     uint64_t next = 0;
+    int i;
 
     if (*mtimecmp != 0) clear_csr(mie, MIP_MTIP);
     timer_next[evt] = tick;
@@ -105,9 +106,9 @@ void eos_timer_set(unsigned char evt, uint32_t msec) {
 }
 
 void eos_timer_clear(unsigned char evt) {
-    int i;
     uint64_t *mtimecmp = (uint64_t *) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
     uint64_t next = 0;
+    int i;
 
     if (*mtimecmp != 0) clear_csr(mie, MIP_MTIP);
     if (timer_next[evt]) {
@@ -122,16 +123,22 @@ void eos_timer_clear(unsigned char evt) {
 
 void eos_time_sleep(uint32_t msec) {
     volatile uint64_t *mtime = (uint64_t *) (CLINT_CTRL_ADDR + CLINT_MTIME);
-    uint64_t mtime0 = *mtime;
+    uint32_t mtime0 = *mtime;
 
     while ((*mtime - mtime0) < (msec * EOS_TIMER_RTC_FREQ / 1000 + 1));
 }
 
-uint64_t eos_time_get_tick(void) {
+uint32_t eos_time_get_tick(void) {
     volatile uint64_t *mtime = (uint64_t *) (CLINT_CTRL_ADDR + CLINT_MTIME);
     return *mtime;
 }
 
+uint64_t eos_time_get_tick64(void) {
+    volatile uint64_t *mtime = (uint64_t *) (CLINT_CTRL_ADDR + CLINT_MTIME);
+    return *mtime;
+}
+
+
 uint32_t eos_time_delta_ms(uint32_t tick) {
-    return ((uint32_t)eos_time_get_tick() - tick) * 1000 / EOS_TIMER_RTC_FREQ;
+    return (eos_time_get_tick() - tick) * 1000 / EOS_TIMER_RTC_FREQ;
 }
diff --git a/fw/fe310/eos/soc/timer.h b/fw/fe310/eos/soc/timer.h
index 6e77502..227aeee 100644
--- a/fw/fe310/eos/soc/timer.h
+++ b/fw/fe310/eos/soc/timer.h
@@ -20,5 +20,6 @@ void eos_timer_set(unsigned char evt, uint32_t msec);
 void eos_timer_clear(unsigned char evt);
 
 void eos_time_sleep(uint32_t msec);
-uint64_t eos_time_get_tick(void);
+uint32_t eos_time_get_tick(void);
+uint64_t eos_time_get_tick64(void);
 uint32_t eos_time_delta_ms(uint32_t tick);