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authorUros Majstorovic <majstor@majstor.org>2021-11-25 05:21:17 +0100
committerUros Majstorovic <majstor@majstor.org>2021-11-25 05:21:17 +0100
commit0a6233e3acf598e09dd5d676c37883cbbf444130 (patch)
tree4a6f3ec5024b8f2389086de1356c8e7333854c38 /fw
parent6a31936e80ae2743376dcbf9d39cd92461c4deca (diff)
spi display driver initial commit
Diffstat (limited to 'fw')
-rw-r--r--fw/fe310/eos/Makefile2
-rw-r--r--fw/fe310/eos/board.h12
-rw-r--r--fw/fe310/eos/display.c71
-rw-r--r--fw/fe310/eos/display.h8
-rw-r--r--fw/fe310/eos/i2s.c6
-rw-r--r--fw/fe310/eos/spi.c20
-rw-r--r--fw/fe310/eos/spi_dev.c5
-rw-r--r--fw/fe310/eos/spi_dev.h1
8 files changed, 111 insertions, 14 deletions
diff --git a/fw/fe310/eos/Makefile b/fw/fe310/eos/Makefile
index abdcbac..ebba204 100644
--- a/fw/fe310/eos/Makefile
+++ b/fw/fe310/eos/Makefile
@@ -4,7 +4,7 @@ CRYPTO_DIR = ../../../crypto
CFLAGS += -I. -I../bsp/include -I../bsp/drivers -I$(CRYPTO_DIR)
-obj = trap_entry.o eos.o msgq.o event.o interrupt.o timer.o power.o i2s.o i2c.o uart.o spi.o spi_dev.o sdcard.o sdc_crypto.o cam.o net.o wifi.o cell.o sock.o unicode.o
+obj = trap_entry.o eos.o msgq.o event.o interrupt.o timer.o power.o i2s.o i2c.o uart.o spi.o spi_dev.o display.o sdcard.o sdc_crypto.o cam.o net.o wifi.o cell.o sock.o unicode.o
%.o: %.c %.h
diff --git a/fw/fe310/eos/board.h b/fw/fe310/eos/board.h
index b92d500..79465b0 100644
--- a/fw/fe310/eos/board.h
+++ b/fw/fe310/eos/board.h
@@ -8,16 +8,18 @@
#define SPI_CSID_SDC SPI_CSID_NONE
#define SPI_CSID_CAM 2
-#define SPI_CSPIN_NET SPI_CSPIN_NONE
-#define SPI_CSPIN_EVE SPI_CSPIN_NONE
-#define SPI_CSPIN_SDC 0
-#define SPI_CSPIN_CAM SPI_CSPIN_NONE
+#define SPI_IOF_MASK ((1 << IOF_SPI1_SCK) | (1 << IOF_SPI1_MOSI) | (1 << IOF_SPI1_MISO) | (1 << IOF_SPI1_SS0) | (1 << IOF_SPI1_SS2) | (1 << IOF_SPI1_SS3))
-#define SPI_IOF_MASK_CS (((uint32_t)1 << IOF_SPI1_SS0) | ((uint32_t)1 << IOF_SPI1_SS2) | ((uint32_t)1 << IOF_SPI1_SS3))
+#define SPI_CSPIN_NET 2
+#define SPI_CSPIN_EVE 10
+#define SPI_CSPIN_SDC 0
+#define SPI_CSPIN_CAM 9
#define NET_PIN_RTS 20
#define NET_PIN_CTS 22
+#define DISP_PIN_CS 11
+
#define EVE_PIN_INTR 23
#define I2S_PIN_CK 1 /* PWM 0.1 */
diff --git a/fw/fe310/eos/display.c b/fw/fe310/eos/display.c
new file mode 100644
index 0000000..bc181cb
--- /dev/null
+++ b/fw/fe310/eos/display.c
@@ -0,0 +1,71 @@
+#include <stdlib.h>
+#include <stdint.h>
+
+#include "encoding.h"
+#include "platform.h"
+
+#include "eos.h"
+
+#include "board.h"
+
+#include "i2s.h"
+#include "net.h"
+#include "spi_dev.h"
+#include "display.h"
+
+#define BIT_PUT(b, pin) if (b) GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << (pin)); else GPIO_REG(GPIO_OUTPUT_VAL) &= ~(1 << (pin));
+#define BIT_GET(pin) ((GPIO_REG(GPIO_INPUT_VAL) & (1 << (pin))) >> (pin))
+
+int eos_disp_select(void) {
+ if (eos_i2s_running()) return EOS_ERR_BUSY;
+ if (eos_spi_dev() != EOS_SPI_DEV_NET) return EOS_ERR_BUSY;
+
+ eos_net_stop();
+ GPIO_REG(GPIO_IOF_EN) &= ~SPI_IOF_MASK;
+}
+
+void eos_disp_deselect(void) {
+ GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << IOF_SPI1_MOSI);
+ GPIO_REG(GPIO_IOF_EN) |= SPI_IOF_MASK;
+ eos_net_start(0);
+}
+
+void eos_disp_cs_set(void) {
+ GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << DISP_PIN_CS);
+}
+
+void eos_disp_cs_clear(void) {
+ GPIO_REG(GPIO_OUTPUT_VAL) &= ~(1 << DISP_PIN_CS);
+}
+
+void eos_disp_write(uint8_t dc, uint8_t data) {
+ int i;
+
+ BIT_PUT(dc, IOF_SPI1_MOSI);
+ // sleep
+ BIT_PUT(1, IOF_SPI1_SCK);
+ for (i=0; i<8; i++) {
+ // sleep
+ BIT_PUT(0, IOF_SPI1_SCK);
+ BIT_PUT(data & 0x80, IOF_SPI1_MOSI);
+ // sleep
+ BIT_PUT(1, IOF_SPI1_SCK);
+ data = data << 1;
+ }
+ // sleep
+ BIT_PUT(0, IOF_SPI1_SCK);
+}
+
+void eos_disp_read(uint8_t *data) {
+ int i;
+
+ *data = 0;
+ for (i=0; i<8; i++) {
+ // sleep
+ BIT_PUT(1, IOF_SPI1_SCK);
+ *data = *data << 1;
+ *data |= BIT_GET(IOF_SPI1_MISO);
+ // sleep
+ BIT_PUT(0, IOF_SPI1_SCK);
+ }
+}
diff --git a/fw/fe310/eos/display.h b/fw/fe310/eos/display.h
new file mode 100644
index 0000000..61effca
--- /dev/null
+++ b/fw/fe310/eos/display.h
@@ -0,0 +1,8 @@
+#include <stdint.h>
+
+int eos_disp_select(void);
+void eos_disp_deselect(void);
+void eos_disp_cs_set(void);
+void eos_disp_cs_clear(void);
+void eos_disp_write(uint8_t dc, uint8_t data);
+void eos_disp_read(uint8_t *data); \ No newline at end of file
diff --git a/fw/fe310/eos/i2s.c b/fw/fe310/eos/i2s.c
index 695967a..0a2742b 100644
--- a/fw/fe310/eos/i2s.c
+++ b/fw/fe310/eos/i2s.c
@@ -140,6 +140,9 @@ extern void _eos_i2s_start_pwm(void);
void eos_i2s_init(uint8_t wakeup_cause) {
eos_evtq_set_handler(EOS_EVT_I2S, i2s_handle_evt);
+ GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << I2S_PIN_CK_SW);
+ GPIO_REG(GPIO_OUTPUT_VAL) &= ~((1 << I2S_PIN_CK) | (1 << I2S_PIN_CK_SR) | (1 << I2S_PIN_WS_MIC) | (1 << I2S_PIN_WS_SPK));
+
GPIO_REG(GPIO_INPUT_EN) &= ~(1 << I2S_PIN_CK);
GPIO_REG(GPIO_OUTPUT_EN) |= (1 << I2S_PIN_CK);
GPIO_REG(GPIO_PULLUP_EN) &= ~(1 << I2S_PIN_CK);
@@ -177,9 +180,6 @@ void eos_i2s_init(uint8_t wakeup_cause) {
GPIO_REG(GPIO_IOF_EN) &= ~I2S_PIN_PWM;
GPIO_REG(GPIO_IOF_SEL) |= I2S_PIN_PWM;
-
- GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << I2S_PIN_CK_SW);
- GPIO_REG(GPIO_OUTPUT_VAL) &= ~((1 << I2S_PIN_CK) | (1 << I2S_PIN_CK_SR) | (1 << I2S_PIN_WS_MIC) | (1 << I2S_PIN_WS_SPK));
}
void eos_i2s_start(uint32_t sample_rate, unsigned char fmt) {
diff --git a/fw/fe310/eos/spi.c b/fw/fe310/eos/spi.c
index 085802c..234bff6 100644
--- a/fw/fe310/eos/spi.c
+++ b/fw/fe310/eos/spi.c
@@ -21,8 +21,6 @@
#define SPI_FLAG_XCHG 0x10
-#define SPI_IOF_MASK (((uint32_t)1 << IOF_SPI1_SCK) | ((uint32_t)1 << IOF_SPI1_MOSI) | ((uint32_t)1 << IOF_SPI1_MISO)) | SPI_IOF_MASK_CS
-
#define MIN(X, Y) (((X) < (Y)) ? (X) : (Y))
#define MAX(X, Y) (((X) > (Y)) ? (X) : (Y))
@@ -56,6 +54,24 @@ void eos_spi_init(uint8_t wakeup_cause) {
eos_evtq_set_handler(EOS_EVT_SPI, spi_handle_evt);
eos_intr_set(INT_SPI1_BASE, IRQ_PRIORITY_SPI_XCHG, NULL);
+ GPIO_REG(GPIO_OUTPUT_VAL) &= ~(1 << IOF_SPI1_SCK);
+ GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << IOF_SPI1_MOSI);
+
+ GPIO_REG(GPIO_INPUT_EN) &= ~(1 << IOF_SPI1_SCK);
+ GPIO_REG(GPIO_OUTPUT_EN) |= (1 << IOF_SPI1_SCK);
+ GPIO_REG(GPIO_PULLUP_EN) &= ~(1 << IOF_SPI1_SCK);
+ GPIO_REG(GPIO_OUTPUT_XOR) &= ~(1 << IOF_SPI1_SCK);
+
+ GPIO_REG(GPIO_INPUT_EN) &= ~(1 << IOF_SPI1_MOSI);
+ GPIO_REG(GPIO_OUTPUT_EN) |= (1 << IOF_SPI1_MOSI);
+ GPIO_REG(GPIO_PULLUP_EN) &= ~(1 << IOF_SPI1_MOSI);
+ GPIO_REG(GPIO_OUTPUT_XOR) &= ~(1 << IOF_SPI1_MOSI);
+
+ GPIO_REG(GPIO_INPUT_EN) |= (1 << IOF_SPI1_MISO);
+ GPIO_REG(GPIO_OUTPUT_EN) &= ~(1 << IOF_SPI1_MISO);
+ GPIO_REG(GPIO_PULLUP_EN) &= ~(1 << IOF_SPI1_MISO);
+ GPIO_REG(GPIO_OUTPUT_XOR) &= ~(1 << IOF_SPI1_MISO);
+
SPI1_REG(SPI_REG_SCKMODE) = SPI_MODE0;
SPI1_REG(SPI_REG_FMT) = SPI_FMT_PROTO(SPI_PROTO_S) |
SPI_FMT_ENDIAN(SPI_ENDIAN_MSB) |
diff --git a/fw/fe310/eos/spi_dev.c b/fw/fe310/eos/spi_dev.c
index 4daa137..09a4a83 100644
--- a/fw/fe310/eos/spi_dev.c
+++ b/fw/fe310/eos/spi_dev.c
@@ -26,12 +26,13 @@ void eos_spi_dev_init(uint8_t wakeup_cause) {
for (i=0; i<EOS_SPI_MAX_DEV; i++) {
spi_div[i] = spi_cfg[i].div;
- if (spi_cfg[i].csid == SPI_CSID_NONE) {
+ if (spi_cfg[i].cspin != SPI_CSPIN_NONE) {
+ GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << spi_cfg[i].cspin);
+
GPIO_REG(GPIO_INPUT_EN) &= ~(1 << spi_cfg[i].cspin);
GPIO_REG(GPIO_OUTPUT_EN) |= (1 << spi_cfg[i].cspin);
GPIO_REG(GPIO_PULLUP_EN) &= ~(1 << spi_cfg[i].cspin);
GPIO_REG(GPIO_OUTPUT_XOR) &= ~(1 << spi_cfg[i].cspin);
- GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << spi_cfg[i].cspin);
}
}
}
diff --git a/fw/fe310/eos/spi_dev.h b/fw/fe310/eos/spi_dev.h
index d5ddeb3..c18466a 100644
--- a/fw/fe310/eos/spi_dev.h
+++ b/fw/fe310/eos/spi_dev.h
@@ -4,7 +4,6 @@
#define EOS_SPI_DEV_EVE 1
#define EOS_SPI_DEV_SDC 2
#define EOS_SPI_DEV_CAM 3
-#define EOS_SPI_DEV_DISP 4
void eos_spi_dev_init(uint8_t wakeup_cause);
int eos_spi_select(unsigned char dev);