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-rw-r--r--fw/fe310/eos/Makefile2
-rw-r--r--fw/fe310/eos/board.h2
-rw-r--r--fw/fe310/eos/eos.c2
-rw-r--r--fw/fe310/eos/eve/eve_platform.h1
-rw-r--r--fw/fe310/eos/net.c1
-rw-r--r--fw/fe310/eos/power.c2
-rw-r--r--fw/fe310/eos/spi.c92
-rw-r--r--fw/fe310/eos/spi.h25
-rw-r--r--fw/fe310/eos/spi_cfg.h35
-rw-r--r--fw/fe310/eos/spi_dev.c89
-rw-r--r--fw/fe310/eos/spi_dev.h21
-rw-r--r--fw/fe310/eos/spi_priv.h44
12 files changed, 189 insertions, 127 deletions
diff --git a/fw/fe310/eos/Makefile b/fw/fe310/eos/Makefile
index 366e69a..0b3d6fe 100644
--- a/fw/fe310/eos/Makefile
+++ b/fw/fe310/eos/Makefile
@@ -2,7 +2,7 @@ include ../common.mk
CFLAGS += -I. -I../bsp/include -I../bsp/drivers
-obj = trap_entry.o eos.o msgq.o event.o interrupt.o timer.o power.o i2s.o i2c.o uart.o spi.o net.o wifi.o cell.o sock.o unicode.o
+obj = trap_entry.o eos.o msgq.o event.o interrupt.o timer.o power.o i2s.o i2c.o uart.o spi.o spi_dev.o net.o wifi.o cell.o sock.o unicode.o
%.o: %.c %.h
diff --git a/fw/fe310/eos/board.h b/fw/fe310/eos/board.h
index 98741da..e663f62 100644
--- a/fw/fe310/eos/board.h
+++ b/fw/fe310/eos/board.h
@@ -13,6 +13,8 @@
#define SPI_CSPIN_SDC SPI_CSPIN_NONE
#define SPI_CSPIN_CAM 23
+#define SPI_IOF_MASK_CS (((uint32_t)1 << IOF_SPI1_SS0) | ((uint32_t)1 << IOF_SPI1_SS2) | ((uint32_t)1 << IOF_SPI1_SS3))
+
#define NET_PIN_RTS 20
#define NET_PIN_CTS 22
diff --git a/fw/fe310/eos/eos.c b/fw/fe310/eos/eos.c
index 490e68b..aa374a0 100644
--- a/fw/fe310/eos/eos.c
+++ b/fw/fe310/eos/eos.c
@@ -7,6 +7,7 @@
#include "i2s.h"
#include "uart.h"
#include "spi.h"
+#include "spi_dev.h"
#include "net.h"
#include "wifi.h"
#include "cell.h"
@@ -28,6 +29,7 @@ void eos_init(void) {
eos_i2s_init();
eos_uart_init();
eos_spi_init();
+ eos_spi_dev_init();
eos_net_init();
eos_power_init();
eos_wifi_init();
diff --git a/fw/fe310/eos/eve/eve_platform.h b/fw/fe310/eos/eve/eve_platform.h
index 48ea00b..7975fbc 100644
--- a/fw/fe310/eos/eve/eve_platform.h
+++ b/fw/fe310/eos/eve/eve_platform.h
@@ -1,6 +1,7 @@
#include <stdint.h>
#include "spi.h"
+#include "spi_dev.h"
#include "timer.h"
#define EVE_ETYPE_INTR 1
diff --git a/fw/fe310/eos/net.c b/fw/fe310/eos/net.c
index c9bbc63..5edb013 100644
--- a/fw/fe310/eos/net.c
+++ b/fw/fe310/eos/net.c
@@ -15,6 +15,7 @@
#include "spi.h"
#include "spi_priv.h"
+#include "spi_dev.h"
#include "net.h"
diff --git a/fw/fe310/eos/power.c b/fw/fe310/eos/power.c
index 6f292b8..5f44a94 100644
--- a/fw/fe310/eos/power.c
+++ b/fw/fe310/eos/power.c
@@ -7,6 +7,8 @@
#include "eos.h"
#include "event.h"
#include "timer.h"
+#include "spi.h"
+#include "spi_dev.h"
#include "net.h"
#include "eve/eve.h"
diff --git a/fw/fe310/eos/spi.c b/fw/fe310/eos/spi.c
index 932c5f1..2966ab9 100644
--- a/fw/fe310/eos/spi.c
+++ b/fw/fe310/eos/spi.c
@@ -11,18 +11,24 @@
#include "board.h"
-#include "net.h"
#include "spi.h"
#include "spi_priv.h"
+#define SPI_MODE0 0x00
+#define SPI_MODE1 0x01
+#define SPI_MODE2 0x02
+#define SPI_MODE3 0x03
+
+#define SPI_FLAG_XCHG 0x10
+
+#define SPI_IOF_MASK (((uint32_t)1 << IOF_SPI1_SCK) | ((uint32_t)1 << IOF_SPI1_MOSI) | ((uint32_t)1 << IOF_SPI1_MISO)) | SPI_IOF_MASK_CS
+
#define MIN(X, Y) (((X) < (Y)) ? (X) : (Y))
#define MAX(X, Y) (((X) > (Y)) ? (X) : (Y))
-static uint8_t spi_dev;
static uint8_t spi_cspin;
-static uint8_t spi_lock;
-static uint16_t spi_div[EOS_SPI_MAX_DEV];
static volatile uint8_t spi_state_flags;
+static unsigned char spi_evt;
static unsigned char spi_in_xchg;
static uint32_t spi_state_len = 0;
@@ -30,11 +36,11 @@ static uint32_t spi_state_idx_tx = 0;
static uint32_t spi_state_idx_rx = 0;
static unsigned char *spi_state_buf = NULL;
-static eos_evt_handler_t evt_handler[EOS_SPI_MAX_DEV];
+static eos_evt_handler_t evt_handler[EOS_SPI_MAX_EVT];
static void spi_handle_evt(unsigned char type, unsigned char *buffer, uint16_t len) {
unsigned char idx = (type & ~EOS_EVT_MASK) - 1;
- if (idx < EOS_SPI_MAX_DEV) {
+ if (idx < EOS_SPI_MAX_EVT) {
evt_handler[idx](type, buffer, len);
} else {
eos_evtq_bad_handler(type, buffer, len);
@@ -44,7 +50,7 @@ static void spi_handle_evt(unsigned char type, unsigned char *buffer, uint16_t l
void eos_spi_init(void) {
int i;
- for (i=0; i<EOS_SPI_MAX_DEV; i++) {
+ for (i=0; i<EOS_SPI_MAX_EVT; i++) {
evt_handler[i] = eos_evtq_bad_handler;
}
eos_evtq_set_handler(EOS_EVT_SPI, spi_handle_evt);
@@ -61,80 +67,30 @@ void eos_spi_init(void) {
// There is no way here to change the CS polarity.
// SPI1_REG(SPI_REG_CSDEF) = 0xFFFF;
-
- for (i=0; i<EOS_SPI_MAX_DEV; i++) {
- spi_div[i] = spi_cfg[i].div;
- if (spi_cfg[i].csid == SPI_CSID_NONE) {
- GPIO_REG(GPIO_INPUT_EN) &= ~(1 << spi_cfg[i].cspin);
- GPIO_REG(GPIO_OUTPUT_EN) |= (1 << spi_cfg[i].cspin);
- GPIO_REG(GPIO_PULLUP_EN) &= ~(1 << spi_cfg[i].cspin);
- GPIO_REG(GPIO_OUTPUT_XOR) &= ~(1 << spi_cfg[i].cspin);
- GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << spi_cfg[i].cspin);
- }
- }
}
-int eos_spi_select(unsigned char dev) {
- if (dev == EOS_SPI_DEV_NET) return EOS_ERR;
- if (spi_dev != EOS_SPI_DEV_NET) return EOS_ERR;
-
- eos_net_stop();
+void eos_spi_start(uint8_t div, uint8_t csid, uint8_t cspin, unsigned char evt) {
spi_state_flags = 0;
- SPI1_REG(SPI_REG_SCKDIV) = spi_div[dev];
- SPI1_REG(SPI_REG_CSID) = spi_cfg[dev].csid;
- if (spi_cfg[dev].csid != SPI_CSID_NONE) {
+ spi_evt = evt;
+ SPI1_REG(SPI_REG_SCKDIV) = div;
+ SPI1_REG(SPI_REG_CSID) = csid;
+ if (csid != SPI_CSID_NONE) {
SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
} else {
SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_OFF;
- spi_cspin = spi_cfg[dev].cspin;
+ spi_cspin = cspin;
}
eos_intr_set_handler(INT_SPI1_BASE, eos_spi_handle_xchg);
-
- return EOS_OK;
}
-int eos_spi_deselect(void) {
- if (spi_dev == EOS_SPI_DEV_NET) return EOS_ERR;
- if (spi_lock) return EOS_ERR_BUSY;
-
+void eos_spi_stop(void) {
eos_spi_flush();
- eos_net_start();
- spi_dev = EOS_SPI_DEV_NET;
-
- return EOS_OK;
-}
-
-uint8_t eos_spi_dev(void) {
- return spi_dev;
-}
-
-uint16_t eos_spi_div(unsigned char dev) {
- return spi_div[dev];
-}
-
-uint16_t eos_spi_csid(unsigned char dev) {
- return spi_cfg[dev].csid;
-}
-
-uint16_t eos_spi_cspin(unsigned char dev) {
- return spi_cfg[dev].cspin;
-}
-
-void eos_spi_lock(void) {
- spi_lock = 1;
-}
-
-void eos_spi_unlock(void) {
- spi_lock = 0;
-}
-
-void eos_spi_set_div(unsigned char dev, uint16_t div) {
- spi_div[dev] = div;
+ spi_evt = 0;
}
-void eos_spi_set_handler(unsigned char dev, eos_evt_handler_t handler) {
+void eos_spi_set_handler(unsigned char evt, eos_evt_handler_t handler) {
if (handler == NULL) handler = eos_evtq_bad_handler;
- if (dev && (dev <= EOS_SPI_MAX_DEV)) evt_handler[dev - 1] = handler;
+ if (evt && (evt <= EOS_SPI_MAX_EVT)) evt_handler[evt - 1] = handler;
}
void _eos_spi_xchg_init(unsigned char *buffer, uint16_t len, uint8_t flags) {
@@ -192,7 +148,7 @@ void eos_spi_handle_xchg(void) {
spi_state_flags &= ~SPI_FLAG_XCHG;
if (!(spi_state_flags & EOS_SPI_FLAG_MORE)) eos_spi_cs_clear();
SPI1_REG(SPI_REG_IE) = 0x0;
- if (spi_dev != EOS_SPI_DEV_NET) eos_evtq_push_isr(EOS_EVT_SPI | spi_dev, spi_state_buf, spi_state_len);
+ if (spi_evt) eos_evtq_push_isr(EOS_EVT_SPI | spi_evt, spi_state_buf, spi_state_len);
} else {
SPI1_REG(SPI_REG_RXCTRL) = SPI_RXWM(MIN(spi_state_len - spi_state_idx_rx - 1, SPI_SIZE_WM - 1));
SPI1_REG(SPI_REG_IE) = SPI_IP_RXWM;
diff --git a/fw/fe310/eos/spi.h b/fw/fe310/eos/spi.h
index ba04cc0..1463c66 100644
--- a/fw/fe310/eos/spi.h
+++ b/fw/fe310/eos/spi.h
@@ -1,30 +1,19 @@
#include <stdint.h>
#include "event.h"
-#define EOS_SPI_DEV_NET 0
-#define EOS_SPI_DEV_EVE 1
-#define EOS_SPI_DEV_SDC 2
-#define EOS_SPI_DEV_CAM 3
-
-#define EOS_SPI_MAX_DEV 4
-
#define EOS_SPI_FLAG_TX 0x01
#define EOS_SPI_FLAG_MORE 0x02
#define EOS_SPI_FLAG_BSWAP 0x04
-void eos_spi_init(void);
-int eos_spi_select(unsigned char dev);
-int eos_spi_deselect(void);
+#define EOS_SPI_EVT_SDC 1
+#define EOS_SPI_EVT_CAM 2
-uint8_t eos_spi_dev(void);
-uint16_t eos_spi_div(unsigned char dev);
-uint16_t eos_spi_csid(unsigned char dev);
-uint16_t eos_spi_cspin(unsigned char dev);
+#define EOS_SPI_MAX_EVT 2
-void eos_spi_lock(void);
-void eos_spi_unlock(void);
-void eos_spi_set_div(unsigned char dev, uint16_t div);
-void eos_spi_set_handler(unsigned char dev, eos_evt_handler_t handler);
+void eos_spi_init(void);
+void eos_spi_start(uint8_t div, uint8_t csid, uint8_t cspin, unsigned char evt);
+void eos_spi_stop(void);
+void eos_spi_set_handler(unsigned char evt, eos_evt_handler_t handler);
void _eos_spi_xchg_init(unsigned char *buffer, uint16_t len, uint8_t flags);
void eos_spi_xchg(unsigned char *buffer, uint16_t len, uint8_t flags);
diff --git a/fw/fe310/eos/spi_cfg.h b/fw/fe310/eos/spi_cfg.h
new file mode 100644
index 0000000..43b0763
--- /dev/null
+++ b/fw/fe310/eos/spi_cfg.h
@@ -0,0 +1,35 @@
+#include <stdint.h>
+
+typedef struct {
+ uint16_t div;
+ uint8_t csid;
+ uint8_t cspin;
+ unsigned char evt;
+} SPIConfig;
+
+static const SPIConfig spi_cfg[] = {
+ { // DEV_NET
+ .div = SPI_DIV_NET,
+ .csid = SPI_CSID_NET,
+ .cspin = SPI_CSPIN_NET,
+ .evt = 0, // Not SPI event
+ },
+ { // DEV_EVE
+ .div = SPI_DIV_EVE,
+ .csid = SPI_CSID_EVE,
+ .cspin = SPI_CSPIN_EVE,
+ .evt = 0,
+ },
+ { // DEV_SDC
+ .div = SPI_DIV_SDC,
+ .csid = SPI_CSID_SDC,
+ .cspin = SPI_CSPIN_SDC,
+ .evt = EOS_SPI_EVT_SDC,
+ },
+ { // DEV_CAM
+ .div = SPI_DIV_CAM,
+ .csid = SPI_CSID_CAM,
+ .cspin = SPI_CSPIN_CAM,
+ .evt = EOS_SPI_EVT_CAM,
+ },
+};
diff --git a/fw/fe310/eos/spi_dev.c b/fw/fe310/eos/spi_dev.c
new file mode 100644
index 0000000..d279faf
--- /dev/null
+++ b/fw/fe310/eos/spi_dev.c
@@ -0,0 +1,89 @@
+#include <stdlib.h>
+#include <stdint.h>
+
+#include "encoding.h"
+#include "platform.h"
+
+#include "eos.h"
+#include "msgq.h"
+#include "interrupt.h"
+#include "event.h"
+
+#include "board.h"
+
+#include "net.h"
+#include "spi.h"
+#include "spi_priv.h"
+#include "spi_cfg.h"
+#include "spi_dev.h"
+
+static uint8_t spi_dev;
+static uint8_t spi_lock;
+static uint16_t spi_div[EOS_SPI_MAX_DEV];
+
+void eos_spi_dev_init(void) {
+ int i;
+
+ for (i=0; i<EOS_SPI_MAX_DEV; i++) {
+ spi_div[i] = spi_cfg[i].div;
+ if (spi_cfg[i].csid == SPI_CSID_NONE) {
+ GPIO_REG(GPIO_INPUT_EN) &= ~(1 << spi_cfg[i].cspin);
+ GPIO_REG(GPIO_OUTPUT_EN) |= (1 << spi_cfg[i].cspin);
+ GPIO_REG(GPIO_PULLUP_EN) &= ~(1 << spi_cfg[i].cspin);
+ GPIO_REG(GPIO_OUTPUT_XOR) &= ~(1 << spi_cfg[i].cspin);
+ GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << spi_cfg[i].cspin);
+ }
+ }
+}
+
+int eos_spi_select(unsigned char dev) {
+ if (dev == EOS_SPI_DEV_NET) return EOS_ERR;
+ if (spi_dev != EOS_SPI_DEV_NET) return EOS_ERR;
+
+ eos_net_stop();
+
+ spi_dev = dev;
+ eos_spi_start(spi_div[dev], spi_cfg[dev].csid, spi_cfg[dev].cspin, spi_cfg[dev].evt);
+
+ return EOS_OK;
+}
+
+int eos_spi_deselect(void) {
+ if (spi_lock) return EOS_ERR_BUSY;
+ if (spi_dev == EOS_SPI_DEV_NET) return EOS_ERR;
+
+ eos_spi_stop();
+
+ spi_dev = EOS_SPI_DEV_NET;
+ eos_net_start();
+
+ return EOS_OK;
+}
+
+uint8_t eos_spi_dev(void) {
+ return spi_dev;
+}
+
+uint16_t eos_spi_div(unsigned char dev) {
+ return spi_div[dev];
+}
+
+uint8_t eos_spi_csid(unsigned char dev) {
+ return spi_cfg[dev].csid;
+}
+
+uint8_t eos_spi_cspin(unsigned char dev) {
+ return spi_cfg[dev].cspin;
+}
+
+void eos_spi_lock(void) {
+ spi_lock = 1;
+}
+
+void eos_spi_unlock(void) {
+ spi_lock = 0;
+}
+
+void eos_spi_set_div(unsigned char dev, uint16_t div) {
+ spi_div[dev] = div;
+}
diff --git a/fw/fe310/eos/spi_dev.h b/fw/fe310/eos/spi_dev.h
new file mode 100644
index 0000000..ff0e2a6
--- /dev/null
+++ b/fw/fe310/eos/spi_dev.h
@@ -0,0 +1,21 @@
+#include <stdint.h>
+
+#define EOS_SPI_DEV_NET 0
+#define EOS_SPI_DEV_EVE 1
+#define EOS_SPI_DEV_SDC 2
+#define EOS_SPI_DEV_CAM 3
+
+#define EOS_SPI_MAX_DEV 4
+
+void eos_spi_dev_init(void);
+int eos_spi_select(unsigned char dev);
+int eos_spi_deselect(void);
+
+uint8_t eos_spi_dev(void);
+uint16_t eos_spi_div(unsigned char dev);
+uint8_t eos_spi_csid(unsigned char dev);
+uint8_t eos_spi_cspin(unsigned char dev);
+
+void eos_spi_lock(void);
+void eos_spi_unlock(void);
+void eos_spi_set_div(unsigned char dev, uint16_t div);
diff --git a/fw/fe310/eos/spi_priv.h b/fw/fe310/eos/spi_priv.h
index a0344ff..72c2dae 100644
--- a/fw/fe310/eos/spi_priv.h
+++ b/fw/fe310/eos/spi_priv.h
@@ -1,44 +1,8 @@
-#define SPI_MODE0 0x00
-#define SPI_MODE1 0x01
-#define SPI_MODE2 0x02
-#define SPI_MODE3 0x03
-
-/* DO NOT TOUCH THEESE */
-#define SPI_SIZE_CHUNK 4
-#define SPI_SIZE_WM 2
-
-#define SPI_FLAG_XCHG 0x10
+#include <stdint.h>
#define SPI_CSID_NONE 1
#define SPI_CSPIN_NONE 0xff
-#define SPI_IOF_MASK (((uint32_t)1 << IOF_SPI1_SCK) | ((uint32_t)1 << IOF_SPI1_MOSI) | ((uint32_t)1 << IOF_SPI1_MISO)) | ((uint32_t)1 << IOF_SPI1_SS0) | ((uint32_t)1 << IOF_SPI1_SS2) | ((uint32_t)1 << IOF_SPI1_SS3)
-
-typedef struct {
- uint8_t div;
- uint8_t csid;
- uint8_t cspin;
-} SPIConfig;
-
-static const SPIConfig spi_cfg[] = {
- { // DEV_NET
- .div = SPI_DIV_NET,
- .csid = SPI_CSID_NET,
- .cspin = SPI_CSPIN_NET,
- },
- { // DEV_EVE
- .div = SPI_DIV_EVE,
- .csid = SPI_CSID_EVE,
- .cspin = SPI_CSPIN_EVE,
- },
- { // DEV_SDC
- .div = SPI_DIV_SDC,
- .csid = SPI_CSID_SDC,
- .cspin = SPI_CSPIN_SDC,
- },
- { // DEV_CAM
- .div = SPI_DIV_CAM,
- .csid = SPI_CSID_CAM,
- .cspin = SPI_CSPIN_CAM,
- },
-}; \ No newline at end of file
+/* DO NOT TOUCH THEESE */
+#define SPI_SIZE_CHUNK 4
+#define SPI_SIZE_WM 2
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-04 07:49:41 +0000