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Diffstat (limited to 'fw/fe310/eos/soc/trap_entry.S')
-rw-r--r--fw/fe310/eos/soc/trap_entry.S224
1 files changed, 107 insertions, 117 deletions
diff --git a/fw/fe310/eos/soc/trap_entry.S b/fw/fe310/eos/soc/trap_entry.S
index 96024cb..7417254 100644
--- a/fw/fe310/eos/soc/trap_entry.S
+++ b/fw/fe310/eos/soc/trap_entry.S
@@ -8,6 +8,8 @@
#define PLIC_PRIORITY 0x0C000000
#define PLIC_THRESHOLD 0x0C200000
#define PLIC_CLAIM 0x0C200004
+#define PLIC_ENABLE1 0x0C002000
+#define PLIC_ENABLE2 0x0C002004
#define PWM0_CTRL_ADDR 0x10015000
#define PWM1_CTRL_ADDR 0x10025000
@@ -21,10 +23,18 @@
#define SPI1_CTRL_ADDR 0x10024000
#include "sifive/devices/spi.h"
+#define INT_GPIO_BASE 8
#define INT_PWM0_BASE 40
#define INT_PWM1_BASE 44
#define INT_PWM2_BASE 48
+#define I2S_FMT (0*4)
+#define I2S_MODE (1*4)
+#define I2S_MIC_WM (2*4)
+#define I2S_SPK_WM (3*4)
+#define I2S_MIC_EVT (4*4)
+#define I2S_SPK_EVT (5*4)
+
#include "board.h"
#include "irq_def.h"
#include "evt_def.h"
@@ -32,12 +42,12 @@
#include "i2s_priv.h"
#include "msgq_priv.h"
- .section .data.entry
+ .section .itim.trap
.align 4
-.global eos_trap_entry
-eos_trap_entry:
- addi sp, sp, -8*REGBYTES
+.global eos_trap_vector
+eos_trap_vector:
+ addi sp, sp, -12*REGBYTES
STORE x8, 0*REGBYTES(sp)
STORE x9, 1*REGBYTES(sp)
STORE x18, 2*REGBYTES(sp)
@@ -46,14 +56,16 @@ eos_trap_entry:
STORE x21, 5*REGBYTES(sp)
STORE x22, 6*REGBYTES(sp)
STORE x23, 7*REGBYTES(sp)
+ STORE x24, 8*REGBYTES(sp)
+ STORE x25, 9*REGBYTES(sp) # channel: 0 - left; 1 - right
+ STORE x26, 10*REGBYTES(sp) # format: 0 - PCM16; 1 - ALAW
+ STORE x27, 11*REGBYTES(sp) # _eos_i2s_drvr addr
csrr x8, mcause
li x18, MCAUSE_EXT
bne x8, x18, handle_intr
li x18, PLIC_CLAIM
lw x9, 0(x18)
- li x18, I2S_IRQ_WS_ID
- beq x9, x18, i2s_handle_ws
li x18, I2S_IRQ_SD_ID
beq x9, x18, i2s_handle_sd
j handle_intr
@@ -84,34 +96,33 @@ evtq_push:
jalr x0, x21
i2s_handle_sd:
- # exit if too early
- li x18, I2S_CTRL_ADDR_WS_SPK
- lw x8, PWM_COUNT(x18)
- lw x9, PWM_CMP3(x18)
- bltu x8, x9, i2s_handle_sd_exit
+ # store channel bit to x25
+ li x18, I2S_CTRL_ADDR_WS
+ lw x18, PWM_CFG(x18)
+ li x19, (1 << 29)
+ and x25, x18, x19
+ srli x25, x25, 29
- # disable sd irq
- li x18, PLIC_PRIORITY
- sw x0, 4*I2S_IRQ_SD_ID(x18)
+ bnez x25, i2s_sd_complete
- la x9, _eos_i2s_fmt
- lw x23, 0(x9)
+ la x27, _eos_i2s_drvr
+ lw x26, I2S_FMT(x27)
i2s_abuf_pop:
# pop from spk buf -> x8
- mv x8, x0
la x9, _eos_i2s_spk_buf
lhu x18, I2S_ABUF_OFF_IDXR(x9)
lhu x19, I2S_ABUF_OFF_IDXW(x9)
lhu x20, I2S_ABUF_OFF_SIZE(x9)
+ beqz x20, i2s_sd_xchg
- beq x18, x19, i2s_handle_sd_xchg
+ beq x18, x19, 2f
addi x20, x20, -1
and x20, x20, x18
lw x21, I2S_ABUF_OFF_ARRAY(x9)
add x21, x21, x20
- beqz x23, 0f
+ beqz x26, 0f
lbu x8, 0(x21)
addi x18, x18, 1
j 1f
@@ -124,20 +135,18 @@ i2s_abuf_pop:
1:
sh x18, I2S_ABUF_OFF_IDXR(x9)
+2:
li x21, 0xffff
sub x18, x19, x18
and x18, x18, x21
# check for push to event queue
- la x9, _eos_i2s_spk_wm
- lw x20, 0(x9)
- beqz x20, i2s_decode
- bgtu x18, x20, i2s_decode
+ lw x9, I2S_SPK_WM(x27)
+ bgtu x18, x9, i2s_decode
- la x9, _eos_i2s_spk_evt_enable
- lw x18, 0(x9)
- beqz x18, i2s_decode
- sw x0, 0(x9)
+ lw x9, I2S_SPK_EVT(x27)
+ beqz x9, i2s_decode
+ sw x0, I2S_SPK_EVT(x27)
# push to event queue
jal x22, evtq_push
@@ -146,13 +155,12 @@ i2s_abuf_pop:
sb x18, MSGQ_ITEM_OFF_TYPE(x21)
i2s_decode:
- beqz x23, i2s_handle_sd_xchg
+ beqz x26, 3f
# aLaw decode -> x8
xori x8, x8, 0x55
andi x9, x8, 0x80
beqz x9, 0f
- li x9, 1
- slli x9, x9, 7
+ li x9, (1 << 7)
not x9, x9
and x8, x8, x9
li x9, -1
@@ -181,15 +189,18 @@ i2s_decode:
slli x8, x8, 1
ori x8, x8, 1
2:
- beqz x9, i2s_handle_sd_xchg
+ beqz x9, 3f
mul x8, x8, x9
+3:
-i2s_handle_sd_xchg:
+i2s_sd_xchg:
+ # li x18, 0xa5a5
+ # mv x8, x18
# read/write shift reg: x8 -> sr -> x8
li x18, GPIO_CTRL_ADDR
li x19, (0x1 << I2S_PIN_SD_IN)
li x20, (0x1 << I2S_PIN_SD_OUT)
- li x21, (0x1 << I2S_PIN_CK_SR)
+ li x21, (0x1 << I2S_PIN_SR_CK)
lw x22, GPIO_OUTPUT_VAL(x18)
lw x9, GPIO_OUTPUT_EN(x18)
@@ -202,8 +213,7 @@ i2s_handle_sd_xchg:
li x23, 16
0:
# write bit
- li x9, 1
- slli x9, x9, 15
+ li x9, (1 << 15)
and x9, x8, x9
slli x8, x8, 1
#if I2S_PIN_SD_OUT > 15
@@ -214,38 +224,44 @@ i2s_handle_sd_xchg:
and x22, x22, x20
or x22, x22, x9
+#if I2S_IDLE1_CYCLES
+ # idle
+ li x9, I2S_IDLE1_CYCLES
+1:
+ addi x9, x9, -1
+ bnez x9, 1b
+#endif
+
# read bit
lw x9, GPIO_INPUT_VAL(x18)
and x9, x9, x19
srli x9, x9, I2S_PIN_SD_IN
or x8, x8, x9
- # 74HC595 ck low (I2S_PIN_CK_SR high)
+ # 74HC595 ck low (I2S_PIN_SR_CK high)
xor x22, x22, x21
sw x22, GPIO_OUTPUT_VAL(x18)
# idle
- li x9, I2S_IDLE_CYCLES
+ li x9, I2S_IDLE2_CYCLES
1:
addi x9, x9, -1
bnez x9, 1b
- # 74HC595 ck high (I2S_PIN_CK_SR low)
+ # 74HC595 ck high (I2S_PIN_SR_CK low)
xor x22, x22, x21
sw x22, GPIO_OUTPUT_VAL(x18)
+ addi x23, x23, -1
+ bnez x23, 0b
+
# idle
- li x9, I2S_IDLE_CYCLES
+ li x9, I2S_IDLE2_CYCLES
1:
addi x9, x9, -1
bnez x9, 1b
- addi x23, x23, -1
- beqz x23, 2f
- j 0b
-
-2:
- # 74HC595 ck low (I2S_PIN_CK_SR high)
+ # 74HC595 ck low (I2S_PIN_SR_CK high)
xor x22, x22, x21
sw x22, GPIO_OUTPUT_VAL(x18)
@@ -256,11 +272,8 @@ i2s_handle_sd_xchg:
slli x8, x8, 16
srai x8, x8, 16
- la x9, _eos_i2s_fmt
- lw x23, 0(x9)
-
i2s_encode:
- beqz x23, i2s_abuf_push
+ beqz x26, i2s_abuf_push
# aLaw encode -> x8
li x18, 0x800
li x19, 7
@@ -297,17 +310,18 @@ i2s_abuf_push:
lhu x18, I2S_ABUF_OFF_IDXR(x9)
lhu x19, I2S_ABUF_OFF_IDXW(x9)
lhu x20, I2S_ABUF_OFF_SIZE(x9)
+ beqz x20, i2s_sd_complete
li x21, 0xffff
sub x18, x19, x18
and x18, x18, x21
- beq x18, x20, i2s_handle_sd_exit
+ beq x18, x20, 2f
addi x20, x20, -1
and x20, x20, x19
lw x21, I2S_ABUF_OFF_ARRAY(x9)
add x21, x21, x20
- beqz x23, 0f
+ beqz x26, 0f
sb x8, 0(x21)
addi x19, x19, 1
addi x18, x18, 1
@@ -321,40 +335,27 @@ i2s_abuf_push:
1:
sh x19, I2S_ABUF_OFF_IDXW(x9)
+2:
# check for push to event queue
- la x9, _eos_i2s_mic_wm
- lw x20, 0(x9)
- beqz x20, i2s_handle_sd_exit
- bltu x18, x20, i2s_handle_sd_exit
+ lw x9, I2S_MIC_WM(x27)
+ bltu x18, x9, i2s_sd_complete
- la x9, _eos_i2s_mic_evt_enable
- lw x18, 0(x9)
- beqz x18, i2s_handle_sd_exit
- sw x0, 0(x9)
+ lw x9, I2S_MIC_EVT(x27)
+ beqz x9, i2s_sd_complete
+ sw x0, I2S_MIC_EVT(x27)
# push to event queue
jal x22, evtq_push
- beqz x21, i2s_handle_sd_exit
+ beqz x21, i2s_sd_complete
li x18, (EOS_EVT_I2S | EOS_I2S_ETYPE_MIC)
sb x18, MSGQ_ITEM_OFF_TYPE(x21)
-i2s_handle_sd_exit:
- # complete
- li x18, I2S_IRQ_SD_ID
- li x19, PLIC_CLAIM
- sw x18, 0(x19)
-
- # exit
- j trap_exit_data
-
-i2s_handle_ws:
- # enable sd irq
- li x18, PLIC_PRIORITY
- li x19, IRQ_PRIORITY_I2S_SD
- sw x19, 4*I2S_IRQ_SD_ID(x18)
+i2s_sd_complete:
+ li x18, GPIO_CTRL_ADDR
+ li x19, (0x1 << I2S_PIN_INT)
+ sw x19, GPIO_FALL_IP(x18)
- # complete
- li x18, I2S_IRQ_WS_ID
+ li x18, I2S_IRQ_SD_ID
li x19, PLIC_CLAIM
sw x18, 0(x19)
@@ -374,8 +375,8 @@ _eos_i2s_start_pwm:
STORE x23, 7*REGBYTES(sp)
li x18, I2S_CTRL_ADDR_CK
- li x19, I2S_CTRL_ADDR_WS_MIC
- li x20, I2S_CTRL_ADDR_WS_SPK
+ li x19, I2S_CTRL_ADDR_WS
+ li x20, I2S_CTRL_ADDR_SR_SEL
li x21, PWM_CFG_ENALWAYS | PWM_CFG_ZEROCMP | I2S_PWM_SCALE_CK
li x22, PWM_CFG_ENALWAYS | PWM_CFG_ZEROCMP | PWM_CFG_CMP2GANG
li x23, PWM_CFG_ENALWAYS | PWM_CFG_ZEROCMP | PWM_CFG_CMP1GANG
@@ -395,16 +396,6 @@ _eos_i2s_start_pwm:
ret
-.global _eos_flash_set
-_eos_flash_set:
- li a3, SPI0_CTRL_ADDR
- sw x0, SPI_REG_FCTRL(a3)
- sw a0, SPI_REG_SCKDIV(a3)
- sw a1, SPI_REG_FFMT(a3)
- li a0, 1
- sw a0, SPI_REG_FCTRL(a3)
- ret
-
trap_exit_data:
# Remain in M-mode after mret
li x18, MSTATUS_MPP
@@ -418,7 +409,11 @@ trap_exit_data:
LOAD x21, 5*REGBYTES(sp)
LOAD x22, 6*REGBYTES(sp)
LOAD x23, 7*REGBYTES(sp)
- addi sp, sp, 8*REGBYTES
+ LOAD x24, 8*REGBYTES(sp)
+ LOAD x25, 9*REGBYTES(sp)
+ LOAD x26, 10*REGBYTES(sp)
+ LOAD x27, 11*REGBYTES(sp)
+ addi sp, sp, 12*REGBYTES
mret
@@ -427,11 +422,11 @@ handle_intr:
addi x18, x18, %lo(trap_entry_text)
jalr x0, x18
- .section .text.entry
+ .section .text.trap
.align 4
trap_entry_text:
- addi sp, sp, -24*REGBYTES
+ addi sp, sp, -20*REGBYTES
STORE x1, 0*REGBYTES(sp)
STORE x2, 1*REGBYTES(sp)
@@ -448,14 +443,10 @@ trap_entry_text:
STORE x15, 12*REGBYTES(sp)
STORE x16, 13*REGBYTES(sp)
STORE x17, 14*REGBYTES(sp)
- STORE x24, 15*REGBYTES(sp)
- STORE x25, 16*REGBYTES(sp)
- STORE x26, 17*REGBYTES(sp)
- STORE x27, 18*REGBYTES(sp)
- STORE x28, 19*REGBYTES(sp)
- STORE x29, 20*REGBYTES(sp)
- STORE x30, 21*REGBYTES(sp)
- STORE x31, 22*REGBYTES(sp)
+ STORE x28, 15*REGBYTES(sp)
+ STORE x29, 16*REGBYTES(sp)
+ STORE x30, 17*REGBYTES(sp)
+ STORE x31, 18*REGBYTES(sp)
li x18, MCAUSE_TIMER
beq x8, x18, handle_timer
@@ -473,7 +464,6 @@ handle_ext:
call eos_intr_handle
li x18, PLIC_CLAIM
sw a0, 0(x18)
- j trap_exit_text
trap_exit_text:
# Remain in M-mode after mret
@@ -495,23 +485,23 @@ trap_exit_text:
LOAD x15, 12*REGBYTES(sp)
LOAD x16, 13*REGBYTES(sp)
LOAD x17, 14*REGBYTES(sp)
- LOAD x24, 15*REGBYTES(sp)
- LOAD x25, 16*REGBYTES(sp)
- LOAD x26, 17*REGBYTES(sp)
- LOAD x27, 18*REGBYTES(sp)
- LOAD x28, 19*REGBYTES(sp)
- LOAD x29, 20*REGBYTES(sp)
- LOAD x30, 21*REGBYTES(sp)
- LOAD x31, 22*REGBYTES(sp)
-
- LOAD x8, 24*REGBYTES(sp)
- LOAD x9, 25*REGBYTES(sp)
- LOAD x18, 26*REGBYTES(sp)
- LOAD x19, 27*REGBYTES(sp)
- LOAD x20, 28*REGBYTES(sp)
- LOAD x21, 29*REGBYTES(sp)
- LOAD x22, 30*REGBYTES(sp)
- LOAD x23, 31*REGBYTES(sp)
+ LOAD x28, 15*REGBYTES(sp)
+ LOAD x29, 16*REGBYTES(sp)
+ LOAD x30, 17*REGBYTES(sp)
+ LOAD x31, 18*REGBYTES(sp)
+
+ LOAD x8, 20*REGBYTES(sp)
+ LOAD x9, 21*REGBYTES(sp)
+ LOAD x18, 22*REGBYTES(sp)
+ LOAD x19, 23*REGBYTES(sp)
+ LOAD x20, 24*REGBYTES(sp)
+ LOAD x21, 25*REGBYTES(sp)
+ LOAD x22, 26*REGBYTES(sp)
+ LOAD x23, 27*REGBYTES(sp)
+ LOAD x24, 28*REGBYTES(sp)
+ LOAD x25, 29*REGBYTES(sp)
+ LOAD x26, 30*REGBYTES(sp)
+ LOAD x27, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-19 16:29:16 +0000