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update=Thursday, August 08, 2019 at 01:05:55 AM
version=1
last_client=kicad
[cvpcb]
version=1
NetIExt=net
[general]
version=1
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60
[eeschema]
version=1
LibDir=
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=myPhone.net
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1524
MinViaDiameter=0.5
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
ViaDiameter1=0.6096
ViaDrill1=0.3048
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.05
SilkTextSizeV=0.6
SilkTextSizeH=0.6
SilkTextSizeThickness=0.125
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=0.5
CopperTextSizeH=0.5
CopperTextThickness=0.125
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.09999999999999999
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.03
SolderMaskMinWidth=0.13
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Netclasses]
[pcbnew/Netclasses/1]
Name=FE310
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.6096
ViaDrill=0.3048
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
|
