diff options
| author | Uros Majstorovic <majstor@majstor.org> | 2019-08-30 13:31:31 +0200 |
|---|---|---|
| committer | Uros Majstorovic <majstor@majstor.org> | 2019-08-30 13:31:31 +0200 |
| commit | eaf219d0b4cce0bd6853bf29820d01ca6050be65 (patch) | |
| tree | ddb2740d40fd632cfe739ae3fecacc59458893a3 /myPhone/myPhone.pro | |
| parent | 629511a4d61e8a7b06576246f85ad8368a2edba4 (diff) | |
REV1 board
Diffstat (limited to 'myPhone/myPhone.pro')
| -rw-r--r-- | myPhone/myPhone.pro | 49 |
1 files changed, 44 insertions, 5 deletions
diff --git a/myPhone/myPhone.pro b/myPhone/myPhone.pro index 4d6f5a6..0557e48 100644 --- a/myPhone/myPhone.pro +++ b/myPhone/myPhone.pro @@ -1,4 +1,4 @@ -update=Thursday, August 08, 2019 at 01:05:55 AM +update=Thursday, August 29, 2019 at 02:40:17 PM version=1 last_client=kicad [cvpcb] @@ -23,7 +23,7 @@ LibDir= version=1 PageLayoutDescrFile= LastNetListRead=myPhone.net -CopperLayerCount=2 +CopperLayerCount=4 BoardThickness=1.6 AllowMicroVias=0 AllowBlindVias=0 @@ -31,13 +31,13 @@ RequireCourtyardDefinitions=0 ProhibitOverlappingCourtyards=1 MinTrackWidth=0.1524 MinViaDiameter=0.5 -MinViaDrill=0.3 +MinViaDrill=0.2 MinMicroViaDiameter=0.2 MinMicroViaDrill=0.09999999999999999 MinHoleToHole=0.25 TrackWidth1=0.25 -ViaDiameter1=0.6096 -ViaDrill1=0.3048 +ViaDiameter1=0.6 +ViaDrill1=0.3 dPairWidth1=0.2 dPairGap1=0.25 dPairViaGap1=0.25 @@ -65,8 +65,25 @@ SolderMaskClearance=0.03 SolderMaskMinWidth=0.13 SolderPasteClearance=0 SolderPasteRatio=-0 +[pcbnew/Layer.In1.Cu] +Name=GND +Type=1 +[pcbnew/Layer.In2.Cu] +Name=PWR +Type=1 [pcbnew/Netclasses] [pcbnew/Netclasses/1] +Name=DISPLAY +Clearance=0.1524 +TrackWidth=0.1524 +ViaDiameter=0.508 +ViaDrill=0.254 +uViaDiameter=0.3 +uViaDrill=0.1 +dPairWidth=0.175 +dPairGap=0.1524 +dPairViaGap=0.25 +[pcbnew/Netclasses/2] Name=FE310 Clearance=0.1524 TrackWidth=0.1524 @@ -77,3 +94,25 @@ uViaDrill=0.1 dPairWidth=0.2 dPairGap=0.25 dPairViaGap=0.25 +[pcbnew/Netclasses/3] +Name=FE310_L +Clearance=0.2 +TrackWidth=0.2 +ViaDiameter=0.6 +ViaDrill=0.3 +uViaDiameter=0.3 +uViaDrill=0.1 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 +[pcbnew/Netclasses/4] +Name=MODEM_USB +Clearance=0.1524 +TrackWidth=0.1524 +ViaDiameter=0.508 +ViaDrill=0.254 +uViaDiameter=0.3 +uViaDrill=0.1 +dPairWidth=0.2288 +dPairGap=0.1524 +dPairViaGap=0.25 |