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-rw-r--r--fw/fe310/eos/dev/drv/Makefile16
-rw-r--r--fw/fe310/eos/dev/drv/apds9151.c32
-rw-r--r--fw/fe310/eos/dev/drv/arducam.c31
-rw-r--r--fw/fe310/eos/dev/drv/bq25895.c9
-rw-r--r--fw/fe310/eos/dev/drv/bq25895.h1
-rw-r--r--fw/fe310/eos/dev/drv/fxl6408.c20
-rw-r--r--fw/fe310/eos/dev/drv/gt911.c114
-rw-r--r--fw/fe310/eos/dev/drv/gt911.h24
-rw-r--r--fw/fe310/eos/dev/drv/ili9806e.c557
-rw-r--r--fw/fe310/eos/dev/drv/ov2640.c90
-rw-r--r--fw/fe310/eos/dev/drv/ov2640.h69
-rw-r--r--fw/fe310/eos/dev/drv/ov2640_imlib.h12
-rw-r--r--fw/fe310/eos/dev/drv/ov2640_platform.h1
-rw-r--r--fw/fe310/eos/dev/drv/pcm1770.c12
-rw-r--r--fw/fe310/eos/dev/drv/pcm1770.h3
-rw-r--r--fw/fe310/eos/dev/drv/platform.h42
-rw-r--r--fw/fe310/eos/dev/drv/sdc_platform.h22
-rw-r--r--fw/fe310/eos/dev/drv/sdcard.c27
-rw-r--r--fw/fe310/eos/dev/drv/sdcard.h22
-rw-r--r--fw/fe310/eos/dev/drv/tps61052.c36
20 files changed, 571 insertions, 569 deletions
diff --git a/fw/fe310/eos/dev/drv/Makefile b/fw/fe310/eos/dev/drv/Makefile
new file mode 100644
index 0000000..c9b39bd
--- /dev/null
+++ b/fw/fe310/eos/dev/drv/Makefile
@@ -0,0 +1,16 @@
+include ../../../common.mk
+CFLAGS += -I$(bsp_dir)/include
+
+obj = sdcard.o arducam.o apds9151.o bq25895.o fxl6408.o gt911.o ili9806e.o ov2640.o pcm1770.o tps61052.o
+
+
+%.o: %.c %.h
+ $(CC) $(CFLAGS) -c $<
+
+%.o: %.S
+ $(CC) $(CFLAGS) -c $<
+
+all: $(obj)
+
+clean:
+ rm -f *.o $(lib)
diff --git a/fw/fe310/eos/dev/drv/apds9151.c b/fw/fe310/eos/dev/drv/apds9151.c
index a96b70b..796155d 100644
--- a/fw/fe310/eos/dev/drv/apds9151.c
+++ b/fw/fe310/eos/dev/drv/apds9151.c
@@ -1,9 +1,7 @@
#include <stdlib.h>
#include <stdint.h>
-#include "eos.h"
-#include "soc/i2c.h"
-
+#include "platform.h"
#include "apds9151.h"
#define APDS9151_ADDR 0x52
@@ -11,14 +9,14 @@
static int reg_read8(uint8_t reg, uint8_t *data) {
int rv;
- rv = eos_i2c_read8(APDS9151_ADDR, reg, data, 1);
+ rv = drv_i2c_read8(APDS9151_ADDR, reg, data, 1);
return rv;
}
static int reg_write8(uint8_t reg, uint8_t data) {
int rv;
- rv = eos_i2c_write8(APDS9151_ADDR, reg, &data, 1);
+ rv = drv_i2c_write8(APDS9151_ADDR, reg, &data, 1);
return rv;
}
@@ -26,13 +24,13 @@ static int reg_read16(uint8_t reg, uint16_t *data) {
int rv;
uint8_t b[2];
- rv = eos_i2c_read8(APDS9151_ADDR, reg, b, 2);
+ rv = drv_i2c_read8(APDS9151_ADDR, reg, b, 2);
if (rv) return rv;
*data = \
((uint16_t)b[0]) | \
((uint16_t)b[1] << 8);
- return EOS_OK;
+ return DRV_OK;
}
static int reg_write16(uint8_t reg, uint16_t data) {
@@ -41,24 +39,24 @@ static int reg_write16(uint8_t reg, uint16_t data) {
b[0] = data;
b[1] = data >> 8;
- rv = eos_i2c_write8(APDS9151_ADDR, reg, b, 2);
+ rv = drv_i2c_write8(APDS9151_ADDR, reg, b, 2);
if (rv) return rv;
- return EOS_OK;
+ return DRV_OK;
}
static int reg_read32(uint8_t reg, uint32_t *data) {
int rv;
uint8_t b[3];
- rv = eos_i2c_read8(APDS9151_ADDR, reg, b, 3);
+ rv = drv_i2c_read8(APDS9151_ADDR, reg, b, 3);
if (rv) return rv;
*data = \
((uint32_t)b[0]) | \
((uint32_t)b[1] << 8) | \
((uint32_t)b[2] << 16);
- return EOS_OK;
+ return DRV_OK;
}
static int reg_write32(uint8_t reg, uint32_t data) {
@@ -68,14 +66,14 @@ static int reg_write32(uint8_t reg, uint32_t data) {
b[0] = data;
b[1] = data >> 8;
b[2] = data >> 16;
- rv = eos_i2c_write8(APDS9151_ADDR, reg, b, 3);
+ rv = drv_i2c_write8(APDS9151_ADDR, reg, b, 3);
if (rv) return rv;
- return EOS_OK;
+ return DRV_OK;
}
int apds9151_reg_read(uint8_t reg, void *data) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
switch (reg & (~APDS9151_REG_MASK)) {
case APDS9151_REG_SIZE_8: {
@@ -90,14 +88,14 @@ int apds9151_reg_read(uint8_t reg, void *data) {
rv = reg_read32(reg & APDS9151_REG_MASK, (uint32_t *)data);
break;
}
- default: return EOS_ERR;
+ default: return DRV_ERR;
}
return rv;
}
int apds9151_reg_write(uint8_t reg, uint32_t data) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
switch (reg & (~APDS9151_REG_MASK)) {
case APDS9151_REG_SIZE_8: {
@@ -112,7 +110,7 @@ int apds9151_reg_write(uint8_t reg, uint32_t data) {
rv = reg_write32(reg & APDS9151_REG_MASK, (uint32_t)data);
break;
}
- default: return EOS_ERR;
+ default: return DRV_ERR;
}
return rv;
diff --git a/fw/fe310/eos/dev/drv/arducam.c b/fw/fe310/eos/dev/drv/arducam.c
index e41d541..a50830a 100644
--- a/fw/fe310/eos/dev/drv/arducam.c
+++ b/fw/fe310/eos/dev/drv/arducam.c
@@ -1,10 +1,7 @@
#include <stdlib.h>
#include <stdint.h>
-#include "eos.h"
-
-#include "soc/spi.h"
-
+#include "platform.h"
#include "arducam.h"
#define ARDUCAM_REG_CAPTURE_CTRL 0x01
@@ -41,19 +38,19 @@
static uint8_t reg_read(uint8_t addr) {
uint8_t ret;
- eos_spi_cs_set();
- eos_spi_xchg8(addr, 0);
- ret = eos_spi_xchg8(0, 0);
- eos_spi_cs_clear();
+ drv_spi_cs_set();
+ drv_spi_xchg8(addr, 0);
+ ret = drv_spi_xchg8(0, 0);
+ drv_spi_cs_clear();
return ret;
}
static void reg_write(uint8_t addr, uint8_t val) {
- eos_spi_cs_set();
- eos_spi_xchg8(addr | 0x80, 0);
- eos_spi_xchg8(val, 0);
- eos_spi_cs_clear();
+ drv_spi_cs_set();
+ drv_spi_xchg8(addr | 0x80, 0);
+ drv_spi_xchg8(val, 0);
+ drv_spi_cs_clear();
}
void arducam_capture(void) {
@@ -84,14 +81,14 @@ uint32_t arducam_fbuf_size(void) {
void arducam_fbuf_read(uint8_t *buffer, uint16_t sz, int first) {
int i;
- eos_spi_cs_set();
- eos_spi_xchg8(ARDUCAM_REG_READ_BURST, 0);
- if (first) eos_spi_xchg8(0, 0);
+ drv_spi_cs_set();
+ drv_spi_xchg8(ARDUCAM_REG_READ_BURST, 0);
+ if (first) drv_spi_xchg8(0, 0);
for (i=0; i<sz; i++) {
- buffer[i] = eos_spi_xchg8(0, 0);
+ buffer[i] = drv_spi_xchg8(0, 0);
}
- eos_spi_cs_clear();
+ drv_spi_cs_clear();
}
void arducam_fbuf_done(void) {
diff --git a/fw/fe310/eos/dev/drv/bq25895.c b/fw/fe310/eos/dev/drv/bq25895.c
index 6007598..8952edd 100644
--- a/fw/fe310/eos/dev/drv/bq25895.c
+++ b/fw/fe310/eos/dev/drv/bq25895.c
@@ -1,16 +1,15 @@
#include <stdlib.h>
+#include <stdint.h>
-#include "eos.h"
-#include "soc/i2c.h"
-
+#include "platform.h"
#include "bq25895.h"
int bq25895_reg_read(uint8_t reg, uint8_t *data) {
- return eos_i2c_read8(BQ25895_ADDR, reg, data, 1);
+ return drv_i2c_read8(BQ25895_ADDR, reg, data, 1);
}
int bq25895_reg_write(uint8_t reg, uint8_t data) {
- return eos_i2c_write8(BQ25895_ADDR, reg, &data, 1);
+ return drv_i2c_write8(BQ25895_ADDR, reg, &data, 1);
}
int bq25895_read_fault(uint8_t *fault) {
diff --git a/fw/fe310/eos/dev/drv/bq25895.h b/fw/fe310/eos/dev/drv/bq25895.h
index 3fa8cfc..6aa1621 100644
--- a/fw/fe310/eos/dev/drv/bq25895.h
+++ b/fw/fe310/eos/dev/drv/bq25895.h
@@ -2,7 +2,6 @@
#define BQ25895_ADDR 0x6A
-int bq25895_init(uint8_t wakeup_cause);
int bq25895_reg_read(uint8_t reg, uint8_t *data);
int bq25895_reg_write(uint8_t reg, uint8_t data);
int bq25895_read_fault(uint8_t *fault); \ No newline at end of file
diff --git a/fw/fe310/eos/dev/drv/fxl6408.c b/fw/fe310/eos/dev/drv/fxl6408.c
index 2647598..67c7110 100644
--- a/fw/fe310/eos/dev/drv/fxl6408.c
+++ b/fw/fe310/eos/dev/drv/fxl6408.c
@@ -1,9 +1,7 @@
#include <stdlib.h>
#include <stdint.h>
-#include "eos.h"
-#include "soc/i2c.h"
-
+#include "platform.h"
#include "fxl6408.h"
#define FXL6408_ADDR0 0x44
@@ -13,7 +11,7 @@ int fxl6408_reg_read(uint8_t chip_id, uint8_t reg, uint8_t *data) {
uint8_t addr = chip_id ? FXL6408_ADDR1 : FXL6408_ADDR0;
int rv;
- rv = eos_i2c_read8(addr, reg, data, 1);
+ rv = drv_i2c_read8(addr, reg, data, 1);
return rv;
}
@@ -21,7 +19,7 @@ int fxl6408_reg_write(uint8_t chip_id, uint8_t reg, uint8_t data) {
uint8_t addr = chip_id ? FXL6408_ADDR1 : FXL6408_ADDR0;
int rv;
- rv = eos_i2c_write8(addr, reg, &data, 1);
+ rv = drv_i2c_write8(addr, reg, &data, 1);
return rv;
}
@@ -29,15 +27,15 @@ int fxl6408_get_pin(uint8_t chip_id, uint8_t reg, uint8_t pin, uint8_t *val) {
uint8_t addr = chip_id ? FXL6408_ADDR1 : FXL6408_ADDR0;
int rv;
- if (reg == FXL6408_REG_ID_CTRL) return EOS_ERR;
+ if (reg == FXL6408_REG_ID_CTRL) return DRV_ERR;
- rv = eos_i2c_read8(addr, reg, val, 1);
+ rv = drv_i2c_read8(addr, reg, val, 1);
if (rv) return rv;
*val = *val >> pin;
*val &= 0x01;
- return EOS_OK;
+ return DRV_OK;
}
int fxl6408_set_pin(uint8_t chip_id, uint8_t reg, uint8_t pin, uint8_t val) {
@@ -45,15 +43,15 @@ int fxl6408_set_pin(uint8_t chip_id, uint8_t reg, uint8_t pin, uint8_t val) {
uint8_t data;
int rv;
- if ((reg == FXL6408_REG_ID_CTRL) || (reg == FXL6408_REG_I_STATE)) return EOS_ERR;
+ if ((reg == FXL6408_REG_ID_CTRL) || (reg == FXL6408_REG_I_STATE)) return DRV_ERR;
- rv = eos_i2c_read8(addr, reg, &data, 1);
+ rv = drv_i2c_read8(addr, reg, &data, 1);
if (rv) return rv;
val &= 0x01;
data &= ~(1 << pin);
if (val) data |= (1 << pin);
- rv = eos_i2c_write8(addr, reg, &data, 1);
+ rv = drv_i2c_write8(addr, reg, &data, 1);
return rv;
}
diff --git a/fw/fe310/eos/dev/drv/gt911.c b/fw/fe310/eos/dev/drv/gt911.c
index 22b82c6..cd71d9a 100644
--- a/fw/fe310/eos/dev/drv/gt911.c
+++ b/fw/fe310/eos/dev/drv/gt911.c
@@ -3,15 +3,7 @@
#include <string.h>
#include <stdio.h>
-#include "encoding.h"
#include "platform.h"
-#include "board.h"
-
-#include "eos.h"
-
-#include "soc/i2c.h"
-#include "soc/timer.h"
-
#include "gt911.h"
#define CMD_SLEEP 0x05
@@ -37,14 +29,14 @@ static int g911_command(uint8_t command) {
int rv;
if (command > 0x07) {
- rv = eos_i2c_write16(GT911_ADDR, REG_CMD2, &command, 1);
+ rv = drv_i2c_write16(GT911_ADDR, REG_CMD2, &command, 1);
if (rv) return rv;
}
- rv = eos_i2c_write16(GT911_ADDR, REG_CMD, &command, 1);
+ rv = drv_i2c_write16(GT911_ADDR, REG_CMD, &command, 1);
if (rv) return rv;
- return EOS_OK;
+ return DRV_OK;
}
static uint8_t gt911_chksum(uint8_t *buf, uint8_t len) {
@@ -64,90 +56,96 @@ static uint8_t gt911_chksum(uint8_t *buf, uint8_t len) {
static int gt911_chip_id(char *buf) {
int rv;
- rv = eos_i2c_read16(GT911_ADDR, REG_PROD_ID, buf, 4);
+ rv = drv_i2c_read16(GT911_ADDR, REG_PROD_ID, buf, 4);
return rv;
}
static int gt911_fw_ver(char *buf) {
int rv;
- rv = eos_i2c_read16(GT911_ADDR, REG_FW_VER, buf, 2);
+ rv = drv_i2c_read16(GT911_ADDR, REG_FW_VER, buf, 2);
return rv;
}
-void eos_gt911_reset(void) {
+void gt911_reset(void) {
/* INT and RST output and low */
- GPIO_REG(GPIO_OUTPUT_VAL) &= ~((1 << CTP_PIN_INT) | (1 << CTP_PIN_RST));
- GPIO_REG(GPIO_OUTPUT_EN) |= ((1 << CTP_PIN_INT) | (1 << CTP_PIN_RST));
+ drv_gpio_clear(GPIO_INPUT_EN, GT911_PIN_INT);
+ drv_gpio_clear(GPIO_OUTPUT_VAL, GT911_PIN_INT);
+ drv_gpio_clear(GPIO_OUTPUT_VAL, GT911_PIN_RST);
+ drv_gpio_set(GPIO_OUTPUT_EN, GT911_PIN_INT);
+ drv_gpio_set(GPIO_OUTPUT_EN, GT911_PIN_RST);
/* T2: > 10ms */
- eos_sleep(12);
+ drv_sleep(12);
/* high: 0x28/0x29 (0x14 7bit), low: 0xBA/0xBB (0x5D 7bit) */
if (GT911_ADDR == 0x14) {
- GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << CTP_PIN_INT);
+ drv_gpio_set(GPIO_OUTPUT_VAL, GT911_PIN_INT);
}
/* T3: > 100us */
- eos_sleep(1);
- GPIO_REG(GPIO_OUTPUT_EN) &= ~(1 << CTP_PIN_RST);
+ drv_sleep(1);
+ drv_gpio_clear(GPIO_OUTPUT_EN, GT911_PIN_RST);
/* T4: > 5ms */
- eos_sleep(6);
- GPIO_REG(GPIO_OUTPUT_VAL) &= ~(1 << CTP_PIN_INT);
+ drv_sleep(6);
+ drv_gpio_clear(GPIO_OUTPUT_VAL, GT911_PIN_INT);
/* end select I2C slave addr */
/* T5: > 50ms */
- eos_sleep(51);
+ drv_sleep(51);
/* set INT as input */
- GPIO_REG(GPIO_OUTPUT_EN) &= ~(1 << CTP_PIN_INT);
+ drv_gpio_clear(GPIO_OUTPUT_EN, GT911_PIN_INT);
+ drv_gpio_set(GPIO_INPUT_EN, GT911_PIN_INT);
}
-int eos_gt911_sleep(void) {
+int gt911_sleep(void) {
int rv;
- GPIO_REG(GPIO_OUTPUT_VAL) &= ~(1 << CTP_PIN_INT);
- GPIO_REG(GPIO_OUTPUT_EN) |= (1 << CTP_PIN_INT);
+ drv_gpio_clear(GPIO_INPUT_EN, GT911_PIN_INT);
+ drv_gpio_clear(GPIO_OUTPUT_VAL, GT911_PIN_INT);
+ drv_gpio_set(GPIO_OUTPUT_EN, GT911_PIN_INT);
rv = g911_command(CMD_SLEEP);
if (rv) return rv;
- return EOS_OK;
+ return DRV_OK;
}
-void eos_gt911_wake(void) {
- GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << CTP_PIN_INT);
- GPIO_REG(GPIO_OUTPUT_EN) |= (1 << CTP_PIN_INT);
+void gt911_wake(void) {
+ drv_gpio_set(GPIO_OUTPUT_VAL, GT911_PIN_INT);
+ drv_gpio_set(GPIO_OUTPUT_EN, GT911_PIN_INT);
- eos_sleep(5);
+ drv_sleep(5);
- GPIO_REG(GPIO_OUTPUT_EN) &= ~(1 << CTP_PIN_INT);
- GPIO_REG(GPIO_OUTPUT_VAL) &= ~(1 << CTP_PIN_INT);
+ drv_gpio_clear(GPIO_OUTPUT_EN, GT911_PIN_INT);
+ drv_gpio_clear(GPIO_OUTPUT_VAL, GT911_PIN_INT);
+ drv_gpio_set(GPIO_INPUT_EN, GT911_PIN_INT);
}
-int eos_gt911_cfg_read(uint8_t *cfg_buf) {
+int gt911_cfg_read(uint8_t *cfg_buf) {
int rv;
- rv = eos_i2c_read16(GT911_ADDR, REG_CFG, cfg_buf, GT911_SIZE_CFG);
+ rv = drv_i2c_read16(GT911_ADDR, REG_CFG, cfg_buf, GT911_SIZE_CFG);
return rv;
}
-int eos_gt911_cfg_write(uint8_t *cfg_buf) {
+int gt911_cfg_write(uint8_t *cfg_buf) {
int rv;
cfg_buf[GT911_SIZE_CFG - 2] = gt911_chksum(cfg_buf, GT911_SIZE_CFG - 2);
cfg_buf[GT911_SIZE_CFG - 1] = 1;
- rv = eos_i2c_write16(GT911_ADDR, REG_CFG, cfg_buf, GT911_SIZE_CFG);
+ rv = drv_i2c_write16(GT911_ADDR, REG_CFG, cfg_buf, GT911_SIZE_CFG);
return rv;
}
-int eos_gt911_cfg_print(void) {
+int gt911_cfg_print(void) {
int i, rv;
uint8_t cfg_buf[GT911_SIZE_CFG];
- rv = eos_gt911_cfg_read(cfg_buf);
+ rv = gt911_cfg_read(cfg_buf);
if (rv) return rv;
printf("GT911 CFG:\n");
@@ -165,61 +163,61 @@ int eos_gt911_cfg_print(void) {
printf("GT911 FW VER:%.2X%.2X\n", cfg_buf[1], cfg_buf[0]);
- return EOS_OK;
+ return DRV_OK;
}
-void eos_gt911_set_reg(uint8_t *cfg_buf, uint16_t reg, uint8_t val) {
+void gt911_set_reg(uint8_t *cfg_buf, uint16_t reg, uint8_t val) {
cfg_buf[reg - REG_CFG] = val;
}
-uint8_t eos_gt911_get_reg(uint8_t *cfg_buf, uint16_t reg) {
+uint8_t gt911_get_reg(uint8_t *cfg_buf, uint16_t reg) {
return cfg_buf[reg - REG_CFG];
}
-int eos_gt911_configure(void) {
+int gt911_configure(void) {
int rv;
uint8_t cfg_buf[GT911_SIZE_CFG];
uint8_t reg;
- rv = eos_gt911_cfg_read(cfg_buf);
+ rv = gt911_cfg_read(cfg_buf);
if (rv) return rv;
/* XY coordinate output threshold: 1 */
- eos_gt911_set_reg(cfg_buf, REG_X_THR, 1);
- eos_gt911_set_reg(cfg_buf, REG_Y_THR, 1);
+ gt911_set_reg(cfg_buf, REG_X_THR, 1);
+ gt911_set_reg(cfg_buf, REG_Y_THR, 1);
/* INT triggering mechanism: falling edge */
- reg = eos_gt911_get_reg(cfg_buf, REG_MOD_SW1);
+ reg = gt911_get_reg(cfg_buf, REG_MOD_SW1);
reg &= 0xFC;
reg |= 1;
- eos_gt911_set_reg(cfg_buf, REG_MOD_SW1, reg);
+ gt911_set_reg(cfg_buf, REG_MOD_SW1, reg);
/* Coordinates report rate: 5 ms */
- reg = eos_gt911_get_reg(cfg_buf, REG_REF_RATE);
+ reg = gt911_get_reg(cfg_buf, REG_REF_RATE);
reg &= 0xF0;
- eos_gt911_set_reg(cfg_buf, REG_REF_RATE, reg);
+ gt911_set_reg(cfg_buf, REG_REF_RATE, reg);
- rv = eos_gt911_cfg_write(cfg_buf);
+ rv = gt911_cfg_write(cfg_buf);
return rv;
}
-int eos_gt911_set_status(uint8_t status) {
+int gt911_set_status(uint8_t status) {
int rv;
- rv = eos_i2c_write16(GT911_ADDR, REG_STATUS, &status, 1);
+ rv = drv_i2c_write16(GT911_ADDR, REG_STATUS, &status, 1);
return rv;
}
-int eos_gt911_get_status(uint8_t *status) {
+int gt911_get_status(uint8_t *status) {
int rv;
- rv = eos_i2c_read16(GT911_ADDR, REG_STATUS, status, 1);
+ rv = drv_i2c_read16(GT911_ADDR, REG_STATUS, status, 1);
return rv;
}
-int eos_gt911_get_points(int num_points, uint8_t *points) {
+int gt911_get_points(int num_points, uint8_t *points) {
int rv;
- rv = eos_i2c_read16(GT911_ADDR, REG_POINTS, points, GT911_SIZE_PBUF * num_points);
+ rv = drv_i2c_read16(GT911_ADDR, REG_POINTS, points, GT911_SIZE_PBUF * num_points);
return rv;
}
diff --git a/fw/fe310/eos/dev/drv/gt911.h b/fw/fe310/eos/dev/drv/gt911.h
index 46f8132..9db6981 100644
--- a/fw/fe310/eos/dev/drv/gt911.h
+++ b/fw/fe310/eos/dev/drv/gt911.h
@@ -7,18 +7,18 @@
#define GT911_SIZE_PBUF 8
#define GT911_MAX_POINTS 5
-void eos_gt911_reset(void);
-int eos_gt911_sleep(void);
-void eos_gt911_wake(void);
+void gt911_reset(void);
+int gt911_sleep(void);
+void gt911_wake(void);
-int eos_gt911_cfg_read(uint8_t *cfg_buf);
-int eos_gt911_cfg_write(uint8_t *cfg_buf);
-int eos_gt911_cfg_print(void);
+int gt911_cfg_read(uint8_t *cfg_buf);
+int gt911_cfg_write(uint8_t *cfg_buf);
+int gt911_cfg_print(void);
-void eos_gt911_set_reg(uint8_t *cfg_buf, uint16_t reg, uint8_t val);
-uint8_t eos_gt911_get_reg(uint8_t *cfg_buf, uint16_t reg);
-int eos_gt911_configure(void);
+void gt911_set_reg(uint8_t *cfg_buf, uint16_t reg, uint8_t val);
+uint8_t gt911_get_reg(uint8_t *cfg_buf, uint16_t reg);
+int gt911_configure(void);
-int eos_gt911_set_status(uint8_t status);
-int eos_gt911_get_status(uint8_t *status);
-int eos_gt911_get_points(int num_points, uint8_t *points); \ No newline at end of file
+int gt911_set_status(uint8_t status);
+int gt911_get_status(uint8_t *status);
+int gt911_get_points(int num_points, uint8_t *points); \ No newline at end of file
diff --git a/fw/fe310/eos/dev/drv/ili9806e.c b/fw/fe310/eos/dev/drv/ili9806e.c
index ff7a8cb..45aabb7 100644
--- a/fw/fe310/eos/dev/drv/ili9806e.c
+++ b/fw/fe310/eos/dev/drv/ili9806e.c
@@ -2,15 +2,10 @@
#include <stdint.h>
#include <string.h>
-#include "eos.h"
-
-#include "soc/spi.h"
-#include "soc/spi9bit.h"
-#include "soc/timer.h"
-
+#include "platform.h"
#include "ili9806e.h"
-#ifdef EOS_DEBUG
+#ifdef DRV_DEBUG
#include <stdio.h>
#endif
@@ -18,419 +13,419 @@ int ili9806e_init(void) {
int rv;
uint8_t chip_id[3];
- eos_spi_cs_set();
+ drv_spi_cs_set();
/* LCD Setting */
- eos_spi9bit_write(0, 0xFF); // change to Page 1 CMD
- eos_spi9bit_write(1, 0xFF);
- eos_spi9bit_write(1, 0x98);
- eos_spi9bit_write(1, 0x06);
- eos_spi9bit_write(1, 0x04);
- eos_spi9bit_write(1, 0x01);
+ drv_spi9bit_write(0, 0xFF); // change to Page 1 CMD
+ drv_spi9bit_write(1, 0xFF);
+ drv_spi9bit_write(1, 0x98);
+ drv_spi9bit_write(1, 0x06);
+ drv_spi9bit_write(1, 0x04);
+ drv_spi9bit_write(1, 0x01);
- // eos_spi9bit_write(0, 0x08); // Output SDA
- // eos_spi9bit_write(1, 0x10);
+ // drv_spi9bit_write(0, 0x08); // Output SDA
+ // drv_spi9bit_write(1, 0x10);
- eos_spi9bit_write(0, 0xFE); // enable read
- eos_spi9bit_write(1, 0x81);
+ drv_spi9bit_write(0, 0xFE); // enable read
+ drv_spi9bit_write(1, 0x81);
- eos_spi9bit_write(0, 0x00); // RDID4
- eos_spi9bit_read(&chip_id[0]);
+ drv_spi9bit_write(0, 0x00); // RDID4
+ drv_spi9bit_read(&chip_id[0]);
- eos_spi9bit_write(0, 0x01);
- eos_spi9bit_read(&chip_id[1]);
+ drv_spi9bit_write(0, 0x01);
+ drv_spi9bit_read(&chip_id[1]);
- eos_spi9bit_write(0, 0x02);
- eos_spi9bit_read(&chip_id[2]);
+ drv_spi9bit_write(0, 0x02);
+ drv_spi9bit_read(&chip_id[2]);
-#ifdef EOS_DEBUG
+#ifdef DRV_DEBUG
printf("LCD CHIP ID: %.2x%.2x%.2x\n", chip_id[0], chip_id[1], chip_id[2]);
#endif
- eos_spi9bit_write(0, 0xFE); // disable read
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0xFE); // disable read
+ drv_spi9bit_write(1, 0x00);
if (memcmp(chip_id, "\x98\x06\x04", sizeof(chip_id))) {
- eos_spi_cs_clear();
- return EOS_ERR_NOTFOUND;
+ drv_spi_cs_clear();
+ return DRV_ERR_NOTFOUND;
}
- eos_spi9bit_write(0, 0x20); // set DE/VSYNC mode
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x20); // set DE/VSYNC mode
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x21); // DE = 1 Active
- eos_spi9bit_write(1, 0x01);
+ drv_spi9bit_write(0, 0x21); // DE = 1 Active
+ drv_spi9bit_write(1, 0x01);
- eos_spi9bit_write(0, 0x30); // resolution setting 480 X 854
- eos_spi9bit_write(1, 0x01);
+ drv_spi9bit_write(0, 0x30); // resolution setting 480 X 854
+ drv_spi9bit_write(1, 0x01);
- eos_spi9bit_write(0, 0x31); // inversion setting 2-dot
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x31); // inversion setting 2-dot
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x40); // BT AVDD,AVDD
- eos_spi9bit_write(1, 0x16);
+ drv_spi9bit_write(0, 0x40); // BT AVDD,AVDD
+ drv_spi9bit_write(1, 0x16);
- eos_spi9bit_write(0, 0x41);
- eos_spi9bit_write(1, 0x33); // 22
+ drv_spi9bit_write(0, 0x41);
+ drv_spi9bit_write(1, 0x33); // 22
- eos_spi9bit_write(0, 0x42);
- eos_spi9bit_write(1, 0x03); // VGL=DDVDH+VCIP-DDVDL, VGH=2DDVDL-VCIP
+ drv_spi9bit_write(0, 0x42);
+ drv_spi9bit_write(1, 0x03); // VGL=DDVDH+VCIP-DDVDL, VGH=2DDVDL-VCIP
- eos_spi9bit_write(0, 0x43);
- eos_spi9bit_write(1, 0x09); // set VGH clamp level
+ drv_spi9bit_write(0, 0x43);
+ drv_spi9bit_write(1, 0x09); // set VGH clamp level
- eos_spi9bit_write(0, 0x44);
- eos_spi9bit_write(1, 0x06); // set VGL clamp level
+ drv_spi9bit_write(0, 0x44);
+ drv_spi9bit_write(1, 0x06); // set VGL clamp level
- eos_spi9bit_write(0, 0x50); // VREG1
- eos_spi9bit_write(1, 0x88);
+ drv_spi9bit_write(0, 0x50); // VREG1
+ drv_spi9bit_write(1, 0x88);
- eos_spi9bit_write(0, 0x51); // VREG2
- eos_spi9bit_write(1, 0x88);
+ drv_spi9bit_write(0, 0x51); // VREG2
+ drv_spi9bit_write(1, 0x88);
- eos_spi9bit_write(0, 0x52); // flicker MSB
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x52); // flicker MSB
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x53); // flicker LSB
- eos_spi9bit_write(1, 0x49); // VCOM
+ drv_spi9bit_write(0, 0x53); // flicker LSB
+ drv_spi9bit_write(1, 0x49); // VCOM
- eos_spi9bit_write(0, 0x55); // flicker
- eos_spi9bit_write(1, 0x49);
+ drv_spi9bit_write(0, 0x55); // flicker
+ drv_spi9bit_write(1, 0x49);
- eos_spi9bit_write(0, 0x60);
- eos_spi9bit_write(1, 0x07);
+ drv_spi9bit_write(0, 0x60);
+ drv_spi9bit_write(1, 0x07);
- eos_spi9bit_write(0, 0x61);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x61);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x62);
- eos_spi9bit_write(1, 0x07);
+ drv_spi9bit_write(0, 0x62);
+ drv_spi9bit_write(1, 0x07);
- eos_spi9bit_write(0, 0x63);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x63);
+ drv_spi9bit_write(1, 0x00);
/* Gamma Setting */
- eos_spi9bit_write(0, 0xA0); // positive Gamma
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0xA0); // positive Gamma
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0xA1);
- eos_spi9bit_write(1, 0x09);
+ drv_spi9bit_write(0, 0xA1);
+ drv_spi9bit_write(1, 0x09);
- eos_spi9bit_write(0, 0xA2);
- eos_spi9bit_write(1, 0x11);
+ drv_spi9bit_write(0, 0xA2);
+ drv_spi9bit_write(1, 0x11);
- eos_spi9bit_write(0, 0xA3);
- eos_spi9bit_write(1, 0x0B);
+ drv_spi9bit_write(0, 0xA3);
+ drv_spi9bit_write(1, 0x0B);
- eos_spi9bit_write(0, 0xA4);
- eos_spi9bit_write(1, 0x05);
+ drv_spi9bit_write(0, 0xA4);
+ drv_spi9bit_write(1, 0x05);
- eos_spi9bit_write(0, 0xA5);
- eos_spi9bit_write(1, 0x08);
+ drv_spi9bit_write(0, 0xA5);
+ drv_spi9bit_write(1, 0x08);
- eos_spi9bit_write(0, 0xA6);
- eos_spi9bit_write(1, 0x06);
+ drv_spi9bit_write(0, 0xA6);
+ drv_spi9bit_write(1, 0x06);
- eos_spi9bit_write(0, 0xA7);
- eos_spi9bit_write(1, 0x04);
+ drv_spi9bit_write(0, 0xA7);
+ drv_spi9bit_write(1, 0x04);
- eos_spi9bit_write(0, 0xA8);
- eos_spi9bit_write(1, 0x09);
+ drv_spi9bit_write(0, 0xA8);
+ drv_spi9bit_write(1, 0x09);
- eos_spi9bit_write(0, 0xA9);
- eos_spi9bit_write(1, 0x0C);
+ drv_spi9bit_write(0, 0xA9);
+ drv_spi9bit_write(1, 0x0C);
- eos_spi9bit_write(0, 0xAA);
- eos_spi9bit_write(1, 0x15);
+ drv_spi9bit_write(0, 0xAA);
+ drv_spi9bit_write(1, 0x15);
- eos_spi9bit_write(0, 0xAB);
- eos_spi9bit_write(1, 0x08);
+ drv_spi9bit_write(0, 0xAB);
+ drv_spi9bit_write(1, 0x08);
- eos_spi9bit_write(0, 0xAC);
- eos_spi9bit_write(1, 0x0F);
+ drv_spi9bit_write(0, 0xAC);
+ drv_spi9bit_write(1, 0x0F);
- eos_spi9bit_write(0, 0xAD);
- eos_spi9bit_write(1, 0x12);
+ drv_spi9bit_write(0, 0xAD);
+ drv_spi9bit_write(1, 0x12);
- eos_spi9bit_write(0, 0xAE);
- eos_spi9bit_write(1, 0x09);
+ drv_spi9bit_write(0, 0xAE);
+ drv_spi9bit_write(1, 0x09);
- eos_spi9bit_write(0, 0xAF);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0xAF);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0xC0); // negative Gamma
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0xC0); // negative Gamma
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0xC1);
- eos_spi9bit_write(1, 0x09);
+ drv_spi9bit_write(0, 0xC1);
+ drv_spi9bit_write(1, 0x09);
- eos_spi9bit_write(0, 0xC2);
- eos_spi9bit_write(1, 0x10);
+ drv_spi9bit_write(0, 0xC2);
+ drv_spi9bit_write(1, 0x10);
- eos_spi9bit_write(0, 0xC3);
- eos_spi9bit_write(1, 0x0C);
+ drv_spi9bit_write(0, 0xC3);
+ drv_spi9bit_write(1, 0x0C);
- eos_spi9bit_write(0, 0xC4);
- eos_spi9bit_write(1, 0x05);
+ drv_spi9bit_write(0, 0xC4);
+ drv_spi9bit_write(1, 0x05);
- eos_spi9bit_write(0, 0xC5);
- eos_spi9bit_write(1, 0x08);
+ drv_spi9bit_write(0, 0xC5);
+ drv_spi9bit_write(1, 0x08);
- eos_spi9bit_write(0, 0xC6);
- eos_spi9bit_write(1, 0x06);
+ drv_spi9bit_write(0, 0xC6);
+ drv_spi9bit_write(1, 0x06);
- eos_spi9bit_write(0, 0xC7);
- eos_spi9bit_write(1, 0x04);
+ drv_spi9bit_write(0, 0xC7);
+ drv_spi9bit_write(1, 0x04);
- eos_spi9bit_write(0, 0xC8);
- eos_spi9bit_write(1, 0x08);
+ drv_spi9bit_write(0, 0xC8);
+ drv_spi9bit_write(1, 0x08);
- eos_spi9bit_write(0, 0xC9);
- eos_spi9bit_write(1, 0x0C);
+ drv_spi9bit_write(0, 0xC9);
+ drv_spi9bit_write(1, 0x0C);
- eos_spi9bit_write(0, 0xCA);
- eos_spi9bit_write(1, 0x14);
+ drv_spi9bit_write(0, 0xCA);
+ drv_spi9bit_write(1, 0x14);
- eos_spi9bit_write(0, 0xCB);
- eos_spi9bit_write(1, 0x08);
+ drv_spi9bit_write(0, 0xCB);
+ drv_spi9bit_write(1, 0x08);
- eos_spi9bit_write(0, 0xCC);
- eos_spi9bit_write(1, 0x0F);
+ drv_spi9bit_write(0, 0xCC);
+ drv_spi9bit_write(1, 0x0F);
- eos_spi9bit_write(0, 0xCD);
- eos_spi9bit_write(1, 0x11);
+ drv_spi9bit_write(0, 0xCD);
+ drv_spi9bit_write(1, 0x11);
- eos_spi9bit_write(0, 0xCE);
- eos_spi9bit_write(1, 0x09);
+ drv_spi9bit_write(0, 0xCE);
+ drv_spi9bit_write(1, 0x09);
- eos_spi9bit_write(0, 0xCF);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0xCF);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0xFF); // change to Page 6 CMD for GIP timing
- eos_spi9bit_write(1, 0xFF);
- eos_spi9bit_write(1, 0x98);
- eos_spi9bit_write(1, 0x06);
- eos_spi9bit_write(1, 0x04);
- eos_spi9bit_write(1, 0x06);
+ drv_spi9bit_write(0, 0xFF); // change to Page 6 CMD for GIP timing
+ drv_spi9bit_write(1, 0xFF);
+ drv_spi9bit_write(1, 0x98);
+ drv_spi9bit_write(1, 0x06);
+ drv_spi9bit_write(1, 0x04);
+ drv_spi9bit_write(1, 0x06);
- eos_spi9bit_write(0, 0x00);
- eos_spi9bit_write(1, 0x20);
+ drv_spi9bit_write(0, 0x00);
+ drv_spi9bit_write(1, 0x20);
- eos_spi9bit_write(0, 0x01);
- eos_spi9bit_write(1, 0x0A);
+ drv_spi9bit_write(0, 0x01);
+ drv_spi9bit_write(1, 0x0A);
- eos_spi9bit_write(0, 0x02);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x02);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x03);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x03);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x04);
- eos_spi9bit_write(1, 0x01);
+ drv_spi9bit_write(0, 0x04);
+ drv_spi9bit_write(1, 0x01);
- eos_spi9bit_write(0, 0x05);
- eos_spi9bit_write(1, 0x01);
+ drv_spi9bit_write(0, 0x05);
+ drv_spi9bit_write(1, 0x01);
- eos_spi9bit_write(0, 0x06);
- eos_spi9bit_write(1, 0x98);
+ drv_spi9bit_write(0, 0x06);
+ drv_spi9bit_write(1, 0x98);
- eos_spi9bit_write(0, 0x07);
- eos_spi9bit_write(1, 0x06);
+ drv_spi9bit_write(0, 0x07);
+ drv_spi9bit_write(1, 0x06);
- eos_spi9bit_write(0, 0x08);
- eos_spi9bit_write(1, 0x01);
+ drv_spi9bit_write(0, 0x08);
+ drv_spi9bit_write(1, 0x01);
- eos_spi9bit_write(0, 0x09);
- eos_spi9bit_write(1, 0x80);
+ drv_spi9bit_write(0, 0x09);
+ drv_spi9bit_write(1, 0x80);
- eos_spi9bit_write(0, 0x0A);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x0A);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x0B);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x0B);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x0C);
- eos_spi9bit_write(1, 0x01);
+ drv_spi9bit_write(0, 0x0C);
+ drv_spi9bit_write(1, 0x01);
- eos_spi9bit_write(0, 0x0D);
- eos_spi9bit_write(1, 0x01);
+ drv_spi9bit_write(0, 0x0D);
+ drv_spi9bit_write(1, 0x01);
- eos_spi9bit_write(0, 0x0E);
- eos_spi9bit_write(1, 0x05);
+ drv_spi9bit_write(0, 0x0E);
+ drv_spi9bit_write(1, 0x05);
- eos_spi9bit_write(0, 0x0F);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x0F);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x10);
- eos_spi9bit_write(1, 0xF0);
+ drv_spi9bit_write(0, 0x10);
+ drv_spi9bit_write(1, 0xF0);
- eos_spi9bit_write(0, 0x11);
- eos_spi9bit_write(1, 0xF4);
+ drv_spi9bit_write(0, 0x11);
+ drv_spi9bit_write(1, 0xF4);
- eos_spi9bit_write(0, 0x12);
- eos_spi9bit_write(1, 0x01);
+ drv_spi9bit_write(0, 0x12);
+ drv_spi9bit_write(1, 0x01);
- eos_spi9bit_write(0, 0x13);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x13);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x14);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x14);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x15);
- eos_spi9bit_write(1, 0xC0);
+ drv_spi9bit_write(0, 0x15);
+ drv_spi9bit_write(1, 0xC0);
- eos_spi9bit_write(0, 0x16);
- eos_spi9bit_write(1, 0x08);
+ drv_spi9bit_write(0, 0x16);
+ drv_spi9bit_write(1, 0x08);
- eos_spi9bit_write(0, 0x17);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x17);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x18);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x18);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x19);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x19);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x1A);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x1A);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x1B);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x1B);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x1C);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x1C);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x1D);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x1D);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x20);
- eos_spi9bit_write(1, 0x01);
+ drv_spi9bit_write(0, 0x20);
+ drv_spi9bit_write(1, 0x01);
- eos_spi9bit_write(0, 0x21);
- eos_spi9bit_write(1, 0x23);
+ drv_spi9bit_write(0, 0x21);
+ drv_spi9bit_write(1, 0x23);
- eos_spi9bit_write(0, 0x22);
- eos_spi9bit_write(1, 0x45);
+ drv_spi9bit_write(0, 0x22);
+ drv_spi9bit_write(1, 0x45);
- eos_spi9bit_write(0, 0x23);
- eos_spi9bit_write(1, 0x67);
+ drv_spi9bit_write(0, 0x23);
+ drv_spi9bit_write(1, 0x67);
- eos_spi9bit_write(0, 0x24);
- eos_spi9bit_write(1, 0x01);
+ drv_spi9bit_write(0, 0x24);
+ drv_spi9bit_write(1, 0x01);
- eos_spi9bit_write(0, 0x25);
- eos_spi9bit_write(1, 0x23);
+ drv_spi9bit_write(0, 0x25);
+ drv_spi9bit_write(1, 0x23);
- eos_spi9bit_write(0, 0x26);
- eos_spi9bit_write(1, 0x45);
+ drv_spi9bit_write(0, 0x26);
+ drv_spi9bit_write(1, 0x45);
- eos_spi9bit_write(0, 0x27);
- eos_spi9bit_write(1, 0x67);
+ drv_spi9bit_write(0, 0x27);
+ drv_spi9bit_write(1, 0x67);
- eos_spi9bit_write(0, 0x30);
- eos_spi9bit_write(1, 0x11);
+ drv_spi9bit_write(0, 0x30);
+ drv_spi9bit_write(1, 0x11);
- eos_spi9bit_write(0, 0x31);
- eos_spi9bit_write(1, 0x11);
+ drv_spi9bit_write(0, 0x31);
+ drv_spi9bit_write(1, 0x11);
- eos_spi9bit_write(0, 0x32);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0x32);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x33);
- eos_spi9bit_write(1, 0xEE);
+ drv_spi9bit_write(0, 0x33);
+ drv_spi9bit_write(1, 0xEE);
- eos_spi9bit_write(0, 0x34);
- eos_spi9bit_write(1, 0xFF);
+ drv_spi9bit_write(0, 0x34);
+ drv_spi9bit_write(1, 0xFF);
- eos_spi9bit_write(0, 0x35);
- eos_spi9bit_write(1, 0xBB);
+ drv_spi9bit_write(0, 0x35);
+ drv_spi9bit_write(1, 0xBB);
- eos_spi9bit_write(0, 0x36);
- eos_spi9bit_write(1, 0xAA);
+ drv_spi9bit_write(0, 0x36);
+ drv_spi9bit_write(1, 0xAA);
- eos_spi9bit_write(0, 0x37);
- eos_spi9bit_write(1, 0xDD);
+ drv_spi9bit_write(0, 0x37);
+ drv_spi9bit_write(1, 0xDD);
- eos_spi9bit_write(0, 0x38);
- eos_spi9bit_write(1, 0xCC);
+ drv_spi9bit_write(0, 0x38);
+ drv_spi9bit_write(1, 0xCC);
- eos_spi9bit_write(0, 0x39);
- eos_spi9bit_write(1, 0x66);
+ drv_spi9bit_write(0, 0x39);
+ drv_spi9bit_write(1, 0x66);
- eos_spi9bit_write(0, 0x3A);
- eos_spi9bit_write(1, 0x77);
+ drv_spi9bit_write(0, 0x3A);
+ drv_spi9bit_write(1, 0x77);
- eos_spi9bit_write(0, 0x3B);
- eos_spi9bit_write(1, 0x22);
+ drv_spi9bit_write(0, 0x3B);
+ drv_spi9bit_write(1, 0x22);
- eos_spi9bit_write(0, 0x3C);
- eos_spi9bit_write(1, 0x22);
+ drv_spi9bit_write(0, 0x3C);
+ drv_spi9bit_write(1, 0x22);
- eos_spi9bit_write(0, 0x3D);
- eos_spi9bit_write(1, 0x22);
+ drv_spi9bit_write(0, 0x3D);
+ drv_spi9bit_write(1, 0x22);
- eos_spi9bit_write(0, 0x3E);
- eos_spi9bit_write(1, 0x22);
+ drv_spi9bit_write(0, 0x3E);
+ drv_spi9bit_write(1, 0x22);
- eos_spi9bit_write(0, 0x3F);
- eos_spi9bit_write(1, 0x22);
+ drv_spi9bit_write(0, 0x3F);
+ drv_spi9bit_write(1, 0x22);
- eos_spi9bit_write(0, 0x40);
- eos_spi9bit_write(1, 0x22);
+ drv_spi9bit_write(0, 0x40);
+ drv_spi9bit_write(1, 0x22);
- eos_spi9bit_write(0, 0xFF); // change to Page 7 CMD for GIP timing
- eos_spi9bit_write(1, 0xFF);
- eos_spi9bit_write(1, 0x98);
- eos_spi9bit_write(1, 0x06);
- eos_spi9bit_write(1, 0x04);
- eos_spi9bit_write(1, 0x07);
+ drv_spi9bit_write(0, 0xFF); // change to Page 7 CMD for GIP timing
+ drv_spi9bit_write(1, 0xFF);
+ drv_spi9bit_write(1, 0x98);
+ drv_spi9bit_write(1, 0x06);
+ drv_spi9bit_write(1, 0x04);
+ drv_spi9bit_write(1, 0x07);
- eos_spi9bit_write(0, 0x17);
- eos_spi9bit_write(1, 0x22);
+ drv_spi9bit_write(0, 0x17);
+ drv_spi9bit_write(1, 0x22);
- eos_spi9bit_write(0, 0x02);
- eos_spi9bit_write(1, 0x77);
+ drv_spi9bit_write(0, 0x02);
+ drv_spi9bit_write(1, 0x77);
- eos_spi9bit_write(0, 0x26);
- eos_spi9bit_write(1, 0xB2);
+ drv_spi9bit_write(0, 0x26);
+ drv_spi9bit_write(1, 0xB2);
- eos_spi9bit_write(0, 0xFF); // change to Page 0 CMD for normal command
- eos_spi9bit_write(1, 0xFF);
- eos_spi9bit_write(1, 0x98);
- eos_spi9bit_write(1, 0x06);
- eos_spi9bit_write(1, 0x04);
- eos_spi9bit_write(1, 0x00);
+ drv_spi9bit_write(0, 0xFF); // change to Page 0 CMD for normal command
+ drv_spi9bit_write(1, 0xFF);
+ drv_spi9bit_write(1, 0x98);
+ drv_spi9bit_write(1, 0x06);
+ drv_spi9bit_write(1, 0x04);
+ drv_spi9bit_write(1, 0x00);
- eos_spi9bit_write(0, 0x3A);
- eos_spi9bit_write(1, 0x70); // 24BIT
+ drv_spi9bit_write(0, 0x3A);
+ drv_spi9bit_write(1, 0x70); // 24BIT
- eos_spi9bit_write(0, 0x11);
- eos_sleep(120);
- eos_spi9bit_write(0, 0x29);
- eos_sleep(25);
+ drv_spi9bit_write(0, 0x11);
+ drv_sleep(120);
+ drv_spi9bit_write(0, 0x29);
+ drv_sleep(25);
- eos_spi_cs_clear();
+ drv_spi_cs_clear();
- return EOS_OK;
+ return DRV_OK;
}
void ili9806e_sleep(void) {
- eos_spi_cs_set();
+ drv_spi_cs_set();
- eos_spi9bit_write(0, 0x28);
- eos_sleep(10);
- eos_spi9bit_write(0, 0x10);
+ drv_spi9bit_write(0, 0x28);
+ drv_sleep(10);
+ drv_spi9bit_write(0, 0x10);
- eos_spi_cs_clear();
+ drv_spi_cs_clear();
}
void ili9806e_wake(void) {
- eos_spi_cs_set();
+ drv_spi_cs_set();
- eos_spi9bit_write(0, 0x11);
- eos_sleep(120);
- eos_spi9bit_write(0, 0x29);
+ drv_spi9bit_write(0, 0x11);
+ drv_sleep(120);
+ drv_spi9bit_write(0, 0x29);
- eos_spi_cs_clear();
+ drv_spi_cs_clear();
}
diff --git a/fw/fe310/eos/dev/drv/ov2640.c b/fw/fe310/eos/dev/drv/ov2640.c
index b801e20..5ed0b3e 100644
--- a/fw/fe310/eos/dev/drv/ov2640.c
+++ b/fw/fe310/eos/dev/drv/ov2640.c
@@ -1,17 +1,17 @@
+/*
+ * Sensor driver adapted from OpenMV project.
+*/
+
#include <stdlib.h>
#include <stdint.h>
#include <math.h>
-#include "eos.h"
-#include "soc/timer.h"
-#include "soc/i2c.h"
-
+#include "platform.h"
+#include "ov2640_platform.h"
#include "ov2640_regs.h"
+#include "ov2640_imlib.h"
#include "ov2640.h"
-#define XCLK_FREQ 24000000
-//#define XCLK_FREQ 12000000
-
#define CIF_WIDTH (400)
#define CIF_HEIGHT (296)
@@ -21,18 +21,6 @@
#define UXGA_WIDTH (1600)
#define UXGA_HEIGHT (1200)
-#define IM_LOG2_2(x) (((x) & 0x2ULL) ? ( 2 ) : 1) // NO ({ ... }) !
-#define IM_LOG2_4(x) (((x) & 0xCULL) ? ( 2 + IM_LOG2_2((x) >> 2)) : IM_LOG2_2(x)) // NO ({ ... }) !
-#define IM_LOG2_8(x) (((x) & 0xF0ULL) ? ( 4 + IM_LOG2_4((x) >> 4)) : IM_LOG2_4(x)) // NO ({ ... }) !
-#define IM_LOG2_16(x) (((x) & 0xFF00ULL) ? ( 8 + IM_LOG2_8((x) >> 8)) : IM_LOG2_8(x)) // NO ({ ... }) !
-#define IM_LOG2_32(x) (((x) & 0xFFFF0000ULL) ? (16 + IM_LOG2_16((x) >> 16)) : IM_LOG2_16(x)) // NO ({ ... }) !
-#define IM_LOG2(x) (((x) & 0xFFFFFFFF00000000ULL) ? (32 + IM_LOG2_32((x) >> 32)) : IM_LOG2_32(x)) // NO ({ ... }) !
-
-#define IM_MAX(a,b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _a > _b ? _a : _b; })
-#define IM_MIN(a,b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _a < _b ? _a : _b; })
-#define IM_DIV(a,b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _b ? (_a / _b) : 0; })
-#define IM_MOD(a,b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _b ? (_a % _b) : 0; })
-
static const int resolution_arr[][2] = {
{0, 0 },
// C/SIF Resolutions
@@ -391,18 +379,18 @@ static const uint8_t saturation_regs[NUM_SATURATION_LEVELS + 1][5] = {
};
static int reg_read(int8_t reg, uint8_t *data) {
- return eos_i2c_read8(OV2640_ADDR, reg, data, 1);
+ return drv_i2c_read8(OV2640_ADDR, reg, data, 1);
}
static int reg_write(uint8_t reg, uint8_t data) {
- return eos_i2c_write8(OV2640_ADDR, reg, &data, 1);
+ return drv_i2c_write8(OV2640_ADDR, reg, &data, 1);
}
static int regarr_write(const uint8_t (*regs)[2]) {
int i, rv;
i = 0;
- rv = EOS_OK;
+ rv = DRV_OK;
while ((regs[i][0] != 0xff) || (regs[i][1] != 0xff)) {
if (!rv) rv = reg_write(regs[i][0], regs[i][1]);
@@ -423,16 +411,16 @@ int ov2640_init(void) {
if (rv) return rv;
// Delay 5 ms
- eos_sleep(5);
+ drv_sleep(5);
// Write default regsiters
rv = regarr_write(default_regs);
if (rv) return rv;
// Delay 300 ms
- eos_sleep(300);
+ drv_sleep(300);
- return EOS_OK;
+ return DRV_OK;
}
int ov2640_sleep(int enable) {
@@ -473,7 +461,7 @@ int ov2640_set_pixfmt(cam_pixformat_t fmt) {
regs = jpeg_regs;
break;
default:
- return EOS_ERR;
+ return DRV_ERR;
}
return regarr_write(regs);
@@ -488,7 +476,7 @@ int ov2640_set_framesize(cam_framesize_t framesize) {
int rv;
if ((w % 4) || (h % 4) || (w > UXGA_WIDTH) || (h > UXGA_HEIGHT)) { // w/h must be divisble by 4
- return EOS_ERR;
+ return DRV_ERR;
}
// Looks really bad.
@@ -518,7 +506,7 @@ int ov2640_set_framesize(cam_framesize_t framesize) {
uint16_t x_off = (sensor_w - w_mul) / 2;
uint16_t y_off = (sensor_h - h_mul) / 2;
- rv = EOS_OK;
+ rv = DRV_OK;
if (!rv) rv = reg_write(CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(log_div) | CTRLI_H_DIV_SET(log_div));
if (!rv) rv = reg_write(HSIZE, HSIZE_SET(w_mul));
if (!rv) rv = reg_write(VSIZE, VSIZE_SET(h_mul));
@@ -536,11 +524,11 @@ int ov2640_set_framesize(cam_framesize_t framesize) {
}
int ov2640_set_contrast(int level) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
level += (NUM_CONTRAST_LEVELS / 2) + 1;
if (level <= 0 || level > NUM_CONTRAST_LEVELS) {
- return EOS_ERR;
+ return DRV_ERR;
}
/* Switch to DSP register bank */
@@ -555,11 +543,11 @@ int ov2640_set_contrast(int level) {
}
int ov2640_set_brightness(int level) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
level += (NUM_BRIGHTNESS_LEVELS / 2) + 1;
if (level <= 0 || level > NUM_BRIGHTNESS_LEVELS) {
- return EOS_ERR;
+ return DRV_ERR;
}
/* Switch to DSP register bank */
@@ -574,11 +562,11 @@ int ov2640_set_brightness(int level) {
}
int ov2640_set_saturation(int level) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
level += (NUM_SATURATION_LEVELS / 2) + 1;
if (level <= 0 || level > NUM_SATURATION_LEVELS) {
- return EOS_ERR;
+ return DRV_ERR;
}
/* Switch to DSP register bank */
@@ -593,7 +581,7 @@ int ov2640_set_saturation(int level) {
}
int ov2640_set_gainceiling(cam_gainceiling_t gainceiling) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
/* Switch to SENSOR register bank */
rv = reg_write(BANK_SEL, BANK_SEL_SENSOR);
@@ -605,7 +593,7 @@ int ov2640_set_gainceiling(cam_gainceiling_t gainceiling) {
}
int ov2640_set_quality(int qs) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
/* Switch to DSP register bank */
rv = reg_write(BANK_SEL, BANK_SEL_DSP);
@@ -617,7 +605,7 @@ int ov2640_set_quality(int qs) {
}
int ov2640_set_colorbar(int enable) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
uint8_t reg;
rv = reg_write(BANK_SEL, BANK_SEL_SENSOR);
@@ -636,7 +624,7 @@ int ov2640_set_colorbar(int enable) {
}
int ov2640_set_auto_gain(int enable, float gain_db, float gain_db_ceiling) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
uint8_t reg;
rv = reg_write(BANK_SEL, BANK_SEL_SENSOR);
@@ -648,7 +636,7 @@ int ov2640_set_auto_gain(int enable, float gain_db, float gain_db_ceiling) {
rv = reg_write(COM8, (reg & (~COM8_AGC_EN)) | (enable ? COM8_AGC_EN : 0));
if (rv) return rv;
- rv = EOS_OK;
+ rv = DRV_OK;
if (enable && (!isnanf(gain_db_ceiling)) && (!isinff(gain_db_ceiling))) {
float gain_ceiling = IM_MAX(IM_MIN(expf((gain_db_ceiling / 20.0) * logf(10.0)), 128.0), 2.0);
@@ -670,7 +658,7 @@ int ov2640_set_auto_gain(int enable, float gain_db, float gain_db_ceiling) {
}
int ov2640_get_gain_db(float *gain_db) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
uint8_t reg, gain;
rv = reg_write(BANK_SEL, BANK_SEL_SENSOR);
@@ -700,11 +688,11 @@ int ov2640_get_gain_db(float *gain_db) {
float lo_gain = 1.0 + (((gain >> 0) & 0xF) / 16.0);
*gain_db = 20.0 * (logf(hi_gain * lo_gain) / logf(10.0));
- return EOS_OK;
+ return DRV_OK;
}
int ov2640_set_auto_exposure(int enable, int exposure_us) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
uint8_t reg;
rv = reg_write(BANK_SEL, BANK_SEL_SENSOR);
@@ -744,7 +732,7 @@ int ov2640_set_auto_exposure(int enable, int exposure_us) {
if (IMAGE_MODE_GET_FMT(reg) == IMAGE_MODE_RAW10) t_pclk = 1;
if (IMAGE_MODE_GET_FMT(reg) == IMAGE_MODE_RGB565) t_pclk = 2;
- int exposure = IM_MAX(IM_MIN(((exposure_us*(((XCLK_FREQ/clk_rc)*pll_mult)/1000000))/t_pclk)/t_line,0xFFFF),0x0000);
+ int exposure = IM_MAX(IM_MIN(((exposure_us*(((OV2640_CLK_FREQ/clk_rc)*pll_mult)/1000000))/t_pclk)/t_line,0xFFFF),0x0000);
if (!rv) rv = reg_write(BANK_SEL, BANK_SEL_SENSOR);
@@ -762,7 +750,7 @@ int ov2640_set_auto_exposure(int enable, int exposure_us) {
}
int ov2640_get_exposure_us(int *exposure_us) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
uint8_t reg, aec_10, aec_92, aec_1510;
rv = reg_write(BANK_SEL, BANK_SEL_SENSOR);
@@ -822,13 +810,13 @@ int ov2640_get_exposure_us(int *exposure_us) {
if (IMAGE_MODE_GET_FMT(reg) == IMAGE_MODE_RGB565) t_pclk = 2;
uint16_t exposure = ((aec_1510 & 0x3F) << 10) + ((aec_92 & 0xFF) << 2) + ((aec_10 & 0x3) << 0);
- *exposure_us = (exposure*t_line*t_pclk)/(((XCLK_FREQ/clk_rc)*pll_mult)/1000000);
+ *exposure_us = (exposure*t_line*t_pclk)/(((OV2640_CLK_FREQ/clk_rc)*pll_mult)/1000000);
- return EOS_OK;
+ return DRV_OK;
}
int ov2640_set_auto_whitebal(int enable, float r_gain_db, float g_gain_db, float b_gain_db) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
uint8_t reg;
rv = reg_write(BANK_SEL, BANK_SEL_DSP);
@@ -848,7 +836,7 @@ int ov2640_set_auto_whitebal(int enable, float r_gain_db, float g_gain_db, float
}
int ov2640_set_hmirror(int enable) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
uint8_t reg;
rv = reg_write(BANK_SEL, BANK_SEL_SENSOR);
@@ -867,7 +855,7 @@ int ov2640_set_hmirror(int enable) {
}
int ov2640_set_vflip(int enable) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
uint8_t reg;
rv = reg_write(BANK_SEL, BANK_SEL_SENSOR);
@@ -886,7 +874,7 @@ int ov2640_set_vflip(int enable) {
}
int ov2640_set_effect(cam_sde_t sde) {
- int rv = EOS_OK;
+ int rv = DRV_OK;
switch (sde) {
case CAM_SDE_NEGATIVE:
@@ -906,7 +894,7 @@ int ov2640_set_effect(cam_sde_t sde) {
if (!rv) rv = reg_write(BPDATA, 0x80);
break;
default:
- return EOS_ERR;
+ return DRV_ERR;
}
return rv;
diff --git a/fw/fe310/eos/dev/drv/ov2640.h b/fw/fe310/eos/dev/drv/ov2640.h
index af282e0..8294d6f 100644
--- a/fw/fe310/eos/dev/drv/ov2640.h
+++ b/fw/fe310/eos/dev/drv/ov2640.h
@@ -1,74 +1,9 @@
#include <stdint.h>
-#define OV2640_ADDR 0x30
+#define OV2640_ADDR 0x30
-typedef enum {
- CAM_PIXFORMAT_INVALID = 0,
- CAM_PIXFORMAT_BINARY, // 1BPP/BINARY
- CAM_PIXFORMAT_GRAYSCALE, // 1BPP/GRAYSCALE
- CAM_PIXFORMAT_RGB565, // 2BPP/RGB565
- CAM_PIXFORMAT_YUV422, // 2BPP/YUV422
- CAM_PIXFORMAT_BAYER, // 1BPP/RAW
- CAM_PIXFORMAT_JPEG, // JPEG/COMPRESSED
-} cam_pixformat_t;
-
-typedef enum {
- CAM_FRAMESIZE_INVALID = 0,
- // C/SIF Resolutions
- CAM_FRAMESIZE_QQCIF, // 88x72
- CAM_FRAMESIZE_QCIF, // 176x144
- CAM_FRAMESIZE_CIF, // 352x288
- CAM_FRAMESIZE_QQSIF, // 88x60
- CAM_FRAMESIZE_QSIF, // 176x120
- CAM_FRAMESIZE_SIF, // 352x240
- // VGA Resolutions
- CAM_FRAMESIZE_QQQQVGA, // 40x30
- CAM_FRAMESIZE_QQQVGA, // 80x60
- CAM_FRAMESIZE_QQVGA, // 160x120
- CAM_FRAMESIZE_QVGA, // 320x240
- CAM_FRAMESIZE_VGA, // 640x480
- CAM_FRAMESIZE_HQQQVGA, // 60x40
- CAM_FRAMESIZE_HQQVGA, // 120x80
- CAM_FRAMESIZE_HQVGA, // 240x160
- // FFT Resolutions
- CAM_FRAMESIZE_64X32, // 64x32
- CAM_FRAMESIZE_64X64, // 64x64
- CAM_FRAMESIZE_128X64, // 128x64
- CAM_FRAMESIZE_128X128, // 128x128
- CAM_FRAMESIZE_320X320, // 320x320
- // Other
- CAM_FRAMESIZE_LCD, // 128x160
- CAM_FRAMESIZE_QQVGA2, // 128x160
- CAM_FRAMESIZE_WVGA, // 720x480
- CAM_FRAMESIZE_WVGA2, // 752x480
- CAM_FRAMESIZE_SVGA, // 800x600
- CAM_FRAMESIZE_XGA, // 1024x768
- CAM_FRAMESIZE_SXGA, // 1280x1024
- CAM_FRAMESIZE_UXGA, // 1600x1200
- CAM_FRAMESIZE_HD, // 1280x720
- CAM_FRAMESIZE_FHD, // 1920x1080
- CAM_FRAMESIZE_QHD, // 2560x1440
- CAM_FRAMESIZE_QXGA, // 2048x1536
- CAM_FRAMESIZE_WQXGA, // 2560x1600
- CAM_FRAMESIZE_WQXGA2, // 2592x1944
-} cam_framesize_t;
-
-typedef enum {
- CAM_GAINCEILING_2X,
- CAM_GAINCEILING_4X,
- CAM_GAINCEILING_8X,
- CAM_GAINCEILING_16X,
- CAM_GAINCEILING_32X,
- CAM_GAINCEILING_64X,
- CAM_GAINCEILING_128X,
-} cam_gainceiling_t;
-
-typedef enum {
- SDE_NORMAL,
- SDE_NEGATIVE,
-} cam_sde_t;
+#define OV2640_CLK_FREQ 24000000
int ov2640_init(void);
-int ov2640_sleep(int enable);
int ov2640_set_pixfmt(cam_pixformat_t fmt);
int ov2640_set_framesize(cam_framesize_t framesize);
diff --git a/fw/fe310/eos/dev/drv/ov2640_imlib.h b/fw/fe310/eos/dev/drv/ov2640_imlib.h
new file mode 100644
index 0000000..b32a79f
--- /dev/null
+++ b/fw/fe310/eos/dev/drv/ov2640_imlib.h
@@ -0,0 +1,12 @@
+/* from OpenMV imlib.h */
+#define IM_LOG2_2(x) (((x) & 0x2ULL) ? ( 2 ) : 1) // NO ({ ... }) !
+#define IM_LOG2_4(x) (((x) & 0xCULL) ? ( 2 + IM_LOG2_2((x) >> 2)) : IM_LOG2_2(x)) // NO ({ ... }) !
+#define IM_LOG2_8(x) (((x) & 0xF0ULL) ? ( 4 + IM_LOG2_4((x) >> 4)) : IM_LOG2_4(x)) // NO ({ ... }) !
+#define IM_LOG2_16(x) (((x) & 0xFF00ULL) ? ( 8 + IM_LOG2_8((x) >> 8)) : IM_LOG2_8(x)) // NO ({ ... }) !
+#define IM_LOG2_32(x) (((x) & 0xFFFF0000ULL) ? (16 + IM_LOG2_16((x) >> 16)) : IM_LOG2_16(x)) // NO ({ ... }) !
+#define IM_LOG2(x) (((x) & 0xFFFFFFFF00000000ULL) ? (32 + IM_LOG2_32((x) >> 32)) : IM_LOG2_32(x)) // NO ({ ... }) !
+
+#define IM_MAX(a,b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _a > _b ? _a : _b; })
+#define IM_MIN(a,b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _a < _b ? _a : _b; })
+#define IM_DIV(a,b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _b ? (_a / _b) : 0; })
+#define IM_MOD(a,b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _b ? (_a % _b) : 0; })
diff --git a/fw/fe310/eos/dev/drv/ov2640_platform.h b/fw/fe310/eos/dev/drv/ov2640_platform.h
new file mode 100644
index 0000000..4c11844
--- /dev/null
+++ b/fw/fe310/eos/dev/drv/ov2640_platform.h
@@ -0,0 +1 @@
+#include "dev/cam_def.h"
diff --git a/fw/fe310/eos/dev/drv/pcm1770.c b/fw/fe310/eos/dev/drv/pcm1770.c
new file mode 100644
index 0000000..c617ae9
--- /dev/null
+++ b/fw/fe310/eos/dev/drv/pcm1770.c
@@ -0,0 +1,12 @@
+#include <stdlib.h>
+#include <stdint.h>
+
+#include "platform.h"
+#include "pcm1770.h"
+
+void pcm1770_reg_write(uint8_t addr, uint8_t val) {
+ drv_spi_cs_set();
+ drv_spi_xchg8(addr, 0);
+ drv_spi_xchg8(val, 0);
+ drv_spi_cs_clear();
+}
diff --git a/fw/fe310/eos/dev/drv/pcm1770.h b/fw/fe310/eos/dev/drv/pcm1770.h
new file mode 100644
index 0000000..22f0f59
--- /dev/null
+++ b/fw/fe310/eos/dev/drv/pcm1770.h
@@ -0,0 +1,3 @@
+#include <stdint.h>
+
+void pcm1770_reg_write(uint8_t addr, uint8_t val);
diff --git a/fw/fe310/eos/dev/drv/platform.h b/fw/fe310/eos/dev/drv/platform.h
new file mode 100644
index 0000000..d1f7248
--- /dev/null
+++ b/fw/fe310/eos/dev/drv/platform.h
@@ -0,0 +1,42 @@
+#include "board.h"
+
+#include "eos.h"
+#include "soc/timer.h"
+#include "soc/i2c.h"
+#include "soc/spi.h"
+#include "soc/spi9bit.h"
+#include "soc/gpio.h"
+#include "sifive/devices/gpio.h"
+
+#ifdef EOS_DEBUG
+#define DRV_DEBUG
+#endif
+
+#define DRV_OK EOS_OK
+#define DRV_ERR EOS_ERR
+#define DRV_ERR_NOTFOUND EOS_ERR_NOTFOUND
+
+/* should define theese for non-EOS platforms:
+#define GPIO_INPUT_EN
+#define GPIO_OUTPUT_EN
+#define GPIO_OUTPUT_VAL
+*/
+
+#define GT911_PIN_INT CTP_PIN_INT
+#define GT911_PIN_RST CTP_PIN_RST
+
+#define drv_spi_cs_set eos_spi_cs_set
+#define drv_spi_cs_clear eos_spi_cs_clear
+#define drv_spi_xchg8 eos_spi_xchg8
+#define drv_spi9bit_read eos_spi9bit_read
+#define drv_spi9bit_write eos_spi9bit_write
+
+#define drv_i2c_read8 eos_i2c_read8
+#define drv_i2c_read16 eos_i2c_read16
+#define drv_i2c_write8 eos_i2c_write8
+#define drv_i2c_write16 eos_i2c_write16
+
+#define drv_sleep eos_sleep
+
+#define drv_gpio_set eos_gpio_set
+#define drv_gpio_clear eos_gpio_clear
diff --git a/fw/fe310/eos/dev/drv/sdc_platform.h b/fw/fe310/eos/dev/drv/sdc_platform.h
new file mode 100644
index 0000000..5d562c2
--- /dev/null
+++ b/fw/fe310/eos/dev/drv/sdc_platform.h
@@ -0,0 +1,22 @@
+/* included from sdcard.h - needs relative includes */
+#include "../../eos.h"
+#include "../../soc/timer.h"
+#include "../../soc/spi.h"
+
+#include "../sdc_crypto.h"
+
+#define SDC_OK EOS_OK
+#define SDC_ERR EOS_ERR
+#define SDC_ERR_BUSY EOS_ERR_BUSY
+
+#define sdc_spi_xchg8 eos_spi_xchg8
+#define sdc_spi_xchg16 eos_spi_xchg16
+#define sdc_spi_xchg32 eos_spi_xchg32
+#define sdc_spi_cs_set eos_spi_cs_set
+#define sdc_spi_cs_clear eos_spi_cs_clear
+#define sdc_sleep eos_sleep
+#define sdc_get_tick eos_get_tick
+#define sdc_tdelta_ms eos_tdelta_ms
+
+#define sdc_encrypt eos_sdc_encrypt
+#define sdc_decrypt eos_sdc_decrypt
diff --git a/fw/fe310/eos/dev/drv/sdcard.c b/fw/fe310/eos/dev/drv/sdcard.c
index bc6b999..96b01ae 100644
--- a/fw/fe310/eos/dev/drv/sdcard.c
+++ b/fw/fe310/eos/dev/drv/sdcard.c
@@ -3,7 +3,6 @@
#include "eos.h"
-#include "sdc_platform.h"
#include "sdcard.h"
#ifdef SDC_DEBUG
@@ -67,7 +66,7 @@
#define SET_WR_BLK_ERASE_COUNT 23
#define SD_APP_OP_COND 41
-static uint8_t sdc_type = 0;
+static uint8_t sdc_type = SDC_TYPE_NONE;
static uint8_t sdc_crc7(uint8_t crc, uint8_t b) {
int i;
@@ -355,26 +354,6 @@ int sdc_init(uint32_t timeout) {
return SDC_OK;
}
-#include "board.h"
-#include "spi.h"
-
-int sdc_init(uint8_t wakeup_cause) {
- int rv;
-
- sdc_spi_set_div(SDC_SPI_DEV_SDC, 1024); // 100 - 400 kHz
-
- rv = sdc_spi_select(SDC_SPI_DEV_SDC);
- if (rv) goto sdc_init_fin;
-
- rv = sdc_init(1000);
- sdc_spi_deselect();
-
-sdc_init_fin:
- sdc_spi_set_div(SDC_SPI_DEV_SDC, SPI_DIV_SDC);
-
- return rv;
-}
-
uint8_t sdc_get_type(void) {
return sdc_type & SDC_TYPE_MASK;
}
@@ -383,6 +362,10 @@ uint8_t sdc_get_cap(void) {
return sdc_type & SDC_CAP_MASK;
}
+void sdc_clear(void) {
+ sdc_type = SDC_TYPE_NONE;
+}
+
int sdc_get_sect_count(uint32_t timeout, uint32_t *sectors) {
int rv;
uint8_t csd[16];
diff --git a/fw/fe310/eos/dev/drv/sdcard.h b/fw/fe310/eos/dev/drv/sdcard.h
index ec453f4..39891bb 100644
--- a/fw/fe310/eos/dev/drv/sdcard.h
+++ b/fw/fe310/eos/dev/drv/sdcard.h
@@ -1,5 +1,9 @@
#include <stdint.h>
+#include "sdc_platform.h"
+
+#define SDC_TYPE_NONE 0x00
+
#define SDC_TYPE_MMC 0x01
#define SDC_TYPE_SDC1 0x04
@@ -12,11 +16,13 @@
#define SDC_CAP_MASK 0xf0
int sdc_init(uint32_t timeout);
-uint8_t eos_sdc_type(void);
-uint8_t eos_sdc_cap(void);
-int eos_sdc_get_sect_count(uint32_t timeout, uint32_t *sectors);
-int eos_sdc_get_blk_size(uint32_t timeout, uint32_t *size);
-int eos_sdc_sync(uint32_t timeout);
-int eos_sdc_erase(uint32_t blk_start, uint32_t blk_end, uint32_t timeout);
-int eos_sdc_sect_read(uint32_t sect, unsigned int count, uint8_t *buffer);
-int eos_sdc_sect_write(uint32_t sect, unsigned int count, uint8_t *buffer);
+uint8_t sdc_get_type(void);
+uint8_t sdc_get_cap(void);
+void sdc_clear(void);
+
+int sdc_get_sect_count(uint32_t timeout, uint32_t *sectors);
+int sdc_get_blk_size(uint32_t timeout, uint32_t *size);
+int sdc_sync(uint32_t timeout);
+int sdc_erase(uint32_t blk_start, uint32_t blk_end, uint32_t timeout);
+int sdc_sect_read(uint32_t sect, unsigned int count, uint8_t *buffer);
+int sdc_sect_write(uint32_t sect, unsigned int count, uint8_t *buffer);
diff --git a/fw/fe310/eos/dev/drv/tps61052.c b/fw/fe310/eos/dev/drv/tps61052.c
index 2908a45..405c8af 100644
--- a/fw/fe310/eos/dev/drv/tps61052.c
+++ b/fw/fe310/eos/dev/drv/tps61052.c
@@ -1,9 +1,7 @@
#include <stdlib.h>
#include <stdint.h>
-#include "eos.h"
-#include "soc/i2c.h"
-
+#include "platform.h"
#include "tps61052.h"
#define TPS61052_ADDR 0x33
@@ -11,14 +9,14 @@
static int reg_read(uint8_t reg, uint8_t *data) {
int rv;
- rv = eos_i2c_read8(TPS61052_ADDR, reg, data, 1);
+ rv = drv_i2c_read8(TPS61052_ADDR, reg, data, 1);
return rv;
}
static int reg_write(uint8_t reg, uint8_t data) {
int rv;
- rv = eos_i2c_write8(TPS61052_ADDR, reg, &data, 1);
+ rv = drv_i2c_write8(TPS61052_ADDR, reg, &data, 1);
return rv;
}
@@ -30,7 +28,7 @@ int tps61052_get_tc(uint8_t *tc) {
if (rv) return rv;
*tc &= 0x07;
- return EOS_OK;
+ return DRV_OK;
}
int tps61052_set_tc(uint8_t tc) {
@@ -55,7 +53,7 @@ int tps61052_get_dim(uint8_t *dim) {
*dim = *dim >> 3;
*dim &= 0x01;
- return EOS_OK;
+ return DRV_OK;
}
int tps61052_set_dim(uint8_t dim) {
@@ -81,7 +79,7 @@ int tps61052_get_ov(uint8_t *ov) {
*ov = *ov >> 4;
*ov &= 0x03;
- return EOS_OK;
+ return DRV_OK;
}
int tps61052_set_ov(uint8_t ov) {
@@ -107,7 +105,7 @@ int tps61052_get_mode0(uint8_t *mode) {
*mode = *mode >> 6;
*mode &= 0x03;
- return EOS_OK;
+ return DRV_OK;
}
int tps61052_set_mode0(uint8_t mode) {
@@ -133,7 +131,7 @@ int tps61052_get_fc(uint8_t *fc) {
if (rv) return rv;
*fc &= 0x07;
- return EOS_OK;
+ return DRV_OK;
}
int tps61052_set_fc(uint8_t fc) {
@@ -158,7 +156,7 @@ int tps61052_get_sft(uint8_t *sft) {
*sft = *sft >> 3;
*sft &= 0x01;
- return EOS_OK;
+ return DRV_OK;
}
int tps61052_set_sft(uint8_t sft) {
@@ -184,7 +182,7 @@ int tps61052_get_stt(uint8_t *stt) {
*stt = *stt >> 4;
*stt &= 0x01;
- return EOS_OK;
+ return DRV_OK;
}
int tps61052_set_stt(uint8_t stt) {
@@ -210,7 +208,7 @@ int tps61052_get_to(uint8_t *to) {
*to = *to >> 5;
*to &= 0x01;
- return EOS_OK;
+ return DRV_OK;
}
int tps61052_get_mode1(uint8_t *mode) {
@@ -221,7 +219,7 @@ int tps61052_get_mode1(uint8_t *mode) {
*mode = *mode >> 6;
*mode &= 0x03;
- return EOS_OK;
+ return DRV_OK;
}
int tps61052_set_mode1(uint8_t mode) {
@@ -248,7 +246,7 @@ int tps61052_get_adc(uint8_t *adc) {
*adc = *adc >> 3;
*adc &= 0x07;
- return EOS_OK;
+ return DRV_OK;
}
int tps61052_get_lf(uint8_t *lf) {
@@ -259,7 +257,7 @@ int tps61052_get_lf(uint8_t *lf) {
*lf = *lf >> 6;
*lf &= 0x01;
- return EOS_OK;
+ return DRV_OK;
}
int tps61052_get_ot(uint8_t *ot) {
@@ -270,7 +268,7 @@ int tps61052_get_ot(uint8_t *ot) {
*ot = *ot >> 7;
*ot &= 0x01;
- return EOS_OK;
+ return DRV_OK;
}
int tps61052_set_ilim(uint8_t ilim) {
@@ -296,7 +294,7 @@ int tps61052_get_stim(uint8_t *stim) {
if (rv) return rv;
*stim &= 0x1F;
- return EOS_OK;
+ return DRV_OK;
}
int tps61052_set_stim(uint8_t stim) {
@@ -321,7 +319,7 @@ int tps61052_get_dctim(uint8_t *dctim) {
*dctim = *dctim >> 5;
*dctim &= 0x07;
- return EOS_OK;
+ return DRV_OK;
}
int tps61052_set_dctim(uint8_t dctim) {
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-22 22:13:06 +0000