code layout

1 files changed, 84 insertions, 121 deletions

diff --git a/fw/fe310/eos/soc/trap_entry.S b/fw/fe310/eos/soc/trap_entry.S
index fb2b121..96024cb 100644
--- a/fw/fe310/eos/soc/trap_entry.S
+++ b/fw/fe310/eos/soc/trap_entry.S
@@ -25,18 +25,6 @@
 #define INT_PWM1_BASE     44
 #define INT_PWM2_BASE     48
 
-#define I2S_MIC_BUF     (0*4)
-#define I2S_SPK_BUF     (1*4)
-#define I2S_FMT         (2*4)
-#define I2S_MODE        (3*4)
-#define I2S_MIC_WM      (4*4)
-#define I2S_SPK_WM      (5*4)
-#define I2S_MIC_EVT     (6*4)
-#define I2S_SPK_EVT     (7*4)
-#define I2S_MIC_CMP2    (8*4)
-#define I2S_MIC_CMP3    (9*4)
-#define I2S_SAMPLE      (10*4)
-
 #include "board.h"
 #include "irq_def.h"
 #include "evt_def.h"
@@ -49,7 +37,7 @@
 
 .global eos_trap_entry
 eos_trap_entry:
-  addi sp, sp, -12*REGBYTES
+  addi sp, sp, -8*REGBYTES
   STORE x8, 0*REGBYTES(sp)
   STORE x9, 1*REGBYTES(sp)
   STORE x18, 2*REGBYTES(sp)
@@ -58,10 +46,6 @@ eos_trap_entry:
   STORE x21, 5*REGBYTES(sp)
   STORE x22, 6*REGBYTES(sp)
   STORE x23, 7*REGBYTES(sp)
-  STORE x24, 8*REGBYTES(sp)     # format:   0 - PCM16;  1 - ALAW
-  STORE x25, 9*REGBYTES(sp)     # mode:     0 - stereo; 1 - mono
-  STORE x26, 10*REGBYTES(sp)    # channel:  0 - left;   1 - right
-  STORE x27, 11*REGBYTES(sp)    # _eos_event_q addr
 
   csrr x8, mcause
   li x18, MCAUSE_EXT
@@ -100,68 +84,34 @@ evtq_push:
   jalr x0, x21
 
 i2s_handle_sd:
-  li x8, I2S_CTRL_ADDR_WS_SPK
-  lw x18, PWM_COUNT(x8)
-  lw x19, PWM_CMP3(x8)
-
   # exit if too early
-  bltu x18, x19, i2s_sd_exit
-
-  la x27, _eos_i2s_drvr
-
-  # move CMPs for next channel and store channel bit to x26
-  lw x20, I2S_MIC_CMP2(x27)
-  lw x21, I2S_MIC_CMP3(x27) # 16-bit period
-
-  add x23, x19, x20
-  add x24, x23, x21
-  slli x20, x21, 1      # 32-bit period
-  slli x21, x20, 1      # 64-bit period
-  bltu x24, x21, 0f
-  neg x21, x21
-  add x23, x23, x21
-  add x24, x24, x21
-0:
-  li x26, 0
-  bltu x23, x20, 0f
-  li x26, 1
-0:
-  bltu x19, x20, 0f
-  neg x20, x20
+  li x18, I2S_CTRL_ADDR_WS_SPK
+  lw x8, PWM_COUNT(x18)
+  lw x9, PWM_CMP3(x18)
+  bltu x8, x9, i2s_handle_sd_exit
+
+  # disable sd irq
   li x18, PLIC_PRIORITY
   sw x0, 4*I2S_IRQ_SD_ID(x18)
-0:
-  add x19, x19, x20
 
-  li x9, I2S_CTRL_ADDR_WS_MIC
-  sw x19, PWM_CMP3(x8)
-  sw x23, PWM_CMP2(x9)
-  sw x24, PWM_CMP3(x9)
-
-  lw x24, I2S_FMT(x27)
-  lw x25, I2S_MODE(x27)
+  la x9, _eos_i2s_fmt
+  lw x23, 0(x9)
 
 i2s_abuf_pop:
-  and x8, x25, x26
-  beqz x8, 0f
-
-  lw x8, I2S_SAMPLE(x27)
-  j i2s_sd_xchg
-0:
   # pop from spk buf -> x8
-  lw x9, I2S_SPK_BUF(x27)
-  beqz x9, i2s_sd_xchg
+  mv x8, x0
+  la x9, _eos_i2s_spk_buf
   lhu x18, I2S_ABUF_OFF_IDXR(x9)
   lhu x19, I2S_ABUF_OFF_IDXW(x9)
   lhu x20, I2S_ABUF_OFF_SIZE(x9)
 
-  beq x18, x19, 2f
+  beq x18, x19, i2s_handle_sd_xchg
 
   addi x20, x20, -1
   and x20, x20, x18
   lw x21, I2S_ABUF_OFF_ARRAY(x9)
   add x21, x21, x20
-  beqz x24, 0f
+  beqz x23, 0f
   lbu x8, 0(x21)
   addi x18, x18, 1
   j 1f
@@ -174,18 +124,20 @@ i2s_abuf_pop:
 1:
   sh x18, I2S_ABUF_OFF_IDXR(x9)
 
-2:
   li x21, 0xffff
   sub x18, x19, x18
   and x18, x18, x21
 
   # check for push to event queue
-  lw x9, I2S_SPK_WM(x27)
-  bgtu x18, x9, i2s_decode
+  la x9, _eos_i2s_spk_wm
+  lw x20, 0(x9)
+  beqz x20, i2s_decode
+  bgtu x18, x20, i2s_decode
 
-  lw x9, I2S_SPK_EVT(x27)
-  beqz x9, i2s_decode
-  sw x0, I2S_SPK_EVT(x27)
+  la x9, _eos_i2s_spk_evt_enable
+  lw x18, 0(x9)
+  beqz x18, i2s_decode
+  sw x0, 0(x9)
 
   # push to event queue
   jal x22, evtq_push
@@ -194,7 +146,7 @@ i2s_abuf_pop:
   sb x18, MSGQ_ITEM_OFF_TYPE(x21)
 
 i2s_decode:
-  beqz x24, 3f
+  beqz x23, i2s_handle_sd_xchg
   # aLaw decode -> x8
   xori x8, x8, 0x55
   andi x9, x8, 0x80
@@ -229,13 +181,10 @@ i2s_decode:
   slli x8, x8, 1
   ori x8, x8, 1
 2:
-  beqz x9, 3f
+  beqz x9, i2s_handle_sd_xchg
   mul x8, x8, x9
-3:
-  beqz x25, i2s_sd_xchg
-  sw x8, I2S_SAMPLE(x27)
 
-i2s_sd_xchg:
+i2s_handle_sd_xchg:
   # read/write shift reg: x8 -> sr -> x8
   li x18, GPIO_CTRL_ADDR
   li x19, (0x1 << I2S_PIN_SD_IN)
@@ -285,15 +234,17 @@ i2s_sd_xchg:
   xor x22, x22, x21
   sw x22, GPIO_OUTPUT_VAL(x18)
 
-  addi x23, x23, -1
-  bnez x23, 0b
-
   # idle
   li x9, I2S_IDLE_CYCLES
 1:
   addi x9, x9, -1
   bnez x9, 1b
 
+  addi x23, x23, -1
+  beqz x23, 2f
+  j 0b
+
+2:
   # 74HC595 ck low (I2S_PIN_CK_SR high)
   xor x22, x22, x21
   sw x22, GPIO_OUTPUT_VAL(x18)
@@ -305,8 +256,11 @@ i2s_sd_xchg:
   slli x8, x8, 16
   srai x8, x8, 16
 
+  la x9, _eos_i2s_fmt
+  lw x23, 0(x9)
+
 i2s_encode:
-  beqz x24, i2s_abuf_push
+  beqz x23, i2s_abuf_push
   # aLaw encode -> x8
   li x18, 0x800
   li x19, 7
@@ -338,12 +292,8 @@ i2s_encode:
   andi x8, x8, 0xff
 
 i2s_abuf_push:
-  # check channel
-  # bnez x26, i2s_sd_exit
-
   # push to mic buf
-  lw x9, I2S_MIC_BUF(x27)
-  beqz x9, i2s_sd_exit
+  la x9, _eos_i2s_mic_buf
   lhu x18, I2S_ABUF_OFF_IDXR(x9)
   lhu x19, I2S_ABUF_OFF_IDXW(x9)
   lhu x20, I2S_ABUF_OFF_SIZE(x9)
@@ -351,13 +301,13 @@ i2s_abuf_push:
 
   sub x18, x19, x18
   and x18, x18, x21
-  beq x18, x20, 2f
+  beq x18, x20, i2s_handle_sd_exit
 
   addi x20, x20, -1
   and x20, x20, x19
   lw x21, I2S_ABUF_OFF_ARRAY(x9)
   add x21, x21, x20
-  beqz x24, 0f
+  beqz x23, 0f
   sb x8, 0(x21)
   addi x19, x19, 1
   addi x18, x18, 1
@@ -371,22 +321,24 @@ i2s_abuf_push:
 1:
   sh x19, I2S_ABUF_OFF_IDXW(x9)
 
-2:
   # check for push to event queue
-  lw x9, I2S_MIC_WM(x27)
-  bltu x18, x9, i2s_sd_exit
+  la x9, _eos_i2s_mic_wm
+  lw x20, 0(x9)
+  beqz x20, i2s_handle_sd_exit
+  bltu x18, x20, i2s_handle_sd_exit
 
-  lw x9, I2S_MIC_EVT(x27)
-  beqz x9, i2s_sd_exit
-  sw x0, I2S_MIC_EVT(x27)
+  la x9, _eos_i2s_mic_evt_enable
+  lw x18, 0(x9)
+  beqz x18, i2s_handle_sd_exit
+  sw x0, 0(x9)
 
   # push to event queue
   jal x22, evtq_push
-  beqz x21, i2s_sd_exit
+  beqz x21, i2s_handle_sd_exit
   li x18, (EOS_EVT_I2S | EOS_I2S_ETYPE_MIC)
   sb x18, MSGQ_ITEM_OFF_TYPE(x21)
 
-i2s_sd_exit:
+i2s_handle_sd_exit:
   # complete
   li x18, I2S_IRQ_SD_ID
   li x19, PLIC_CLAIM
@@ -443,6 +395,16 @@ _eos_i2s_start_pwm:
 
   ret
 
+.global _eos_flash_set
+_eos_flash_set:
+  li a3, SPI0_CTRL_ADDR
+  sw x0, SPI_REG_FCTRL(a3)
+  sw a0, SPI_REG_SCKDIV(a3)
+  sw a1, SPI_REG_FFMT(a3)
+  li a0, 1
+  sw a0, SPI_REG_FCTRL(a3)
+  ret
+
 trap_exit_data:
   # Remain in M-mode after mret
   li x18, MSTATUS_MPP
@@ -456,11 +418,7 @@ trap_exit_data:
   LOAD x21, 5*REGBYTES(sp)
   LOAD x22, 6*REGBYTES(sp)
   LOAD x23, 7*REGBYTES(sp)
-  LOAD x24, 8*REGBYTES(sp)
-  LOAD x25, 9*REGBYTES(sp)
-  LOAD x26, 10*REGBYTES(sp)
-  LOAD x27, 11*REGBYTES(sp)
-  addi sp, sp, 12*REGBYTES
+  addi sp, sp, 8*REGBYTES
 
   mret
 
@@ -473,7 +431,7 @@ handle_intr:
   .align 4
 
 trap_entry_text:
-  addi sp, sp, -20*REGBYTES
+  addi sp, sp, -24*REGBYTES
 
   STORE x1, 0*REGBYTES(sp)
   STORE x2, 1*REGBYTES(sp)
@@ -490,10 +448,14 @@ trap_entry_text:
   STORE x15, 12*REGBYTES(sp)
   STORE x16, 13*REGBYTES(sp)
   STORE x17, 14*REGBYTES(sp)
-  STORE x28, 15*REGBYTES(sp)
-  STORE x29, 16*REGBYTES(sp)
-  STORE x30, 17*REGBYTES(sp)
-  STORE x31, 18*REGBYTES(sp)
+  STORE x24, 15*REGBYTES(sp)
+  STORE x25, 16*REGBYTES(sp)
+  STORE x26, 17*REGBYTES(sp)
+  STORE x27, 18*REGBYTES(sp)
+  STORE x28, 19*REGBYTES(sp)
+  STORE x29, 20*REGBYTES(sp)
+  STORE x30, 21*REGBYTES(sp)
+  STORE x31, 22*REGBYTES(sp)
 
   li x18, MCAUSE_TIMER
   beq x8, x18, handle_timer
@@ -511,6 +473,7 @@ handle_ext:
   call eos_intr_handle
   li x18, PLIC_CLAIM
   sw a0, 0(x18)
+  j trap_exit_text
 
 trap_exit_text:
   # Remain in M-mode after mret
@@ -532,23 +495,23 @@ trap_exit_text:
   LOAD x15, 12*REGBYTES(sp)
   LOAD x16, 13*REGBYTES(sp)
   LOAD x17, 14*REGBYTES(sp)
-  LOAD x28, 15*REGBYTES(sp)
-  LOAD x29, 16*REGBYTES(sp)
-  LOAD x30, 17*REGBYTES(sp)
-  LOAD x31, 18*REGBYTES(sp)
-
-  LOAD x8, 20*REGBYTES(sp)
-  LOAD x9, 21*REGBYTES(sp)
-  LOAD x18, 22*REGBYTES(sp)
-  LOAD x19, 23*REGBYTES(sp)
-  LOAD x20, 24*REGBYTES(sp)
-  LOAD x21, 25*REGBYTES(sp)
-  LOAD x22, 26*REGBYTES(sp)
-  LOAD x23, 27*REGBYTES(sp)
-  LOAD x24, 28*REGBYTES(sp)
-  LOAD x25, 29*REGBYTES(sp)
-  LOAD x26, 30*REGBYTES(sp)
-  LOAD x27, 31*REGBYTES(sp)
+  LOAD x24, 15*REGBYTES(sp)
+  LOAD x25, 16*REGBYTES(sp)
+  LOAD x26, 17*REGBYTES(sp)
+  LOAD x27, 18*REGBYTES(sp)
+  LOAD x28, 19*REGBYTES(sp)
+  LOAD x29, 20*REGBYTES(sp)
+  LOAD x30, 21*REGBYTES(sp)
+  LOAD x31, 22*REGBYTES(sp)
+
+  LOAD x8, 24*REGBYTES(sp)
+  LOAD x9, 25*REGBYTES(sp)
+  LOAD x18, 26*REGBYTES(sp)
+  LOAD x19, 27*REGBYTES(sp)
+  LOAD x20, 28*REGBYTES(sp)
+  LOAD x21, 29*REGBYTES(sp)
+  LOAD x22, 30*REGBYTES(sp)
+  LOAD x23, 31*REGBYTES(sp)
 
   addi sp, sp, 32*REGBYTES
   mret